1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/taskqueue.h> 46 #include <sys/bus.h> 47 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include "miibus_if.h" 60 61 #include <machine/bus.h> 62 #include <dev/rl/if_rlreg.h> 63 64 static int rgephy_probe(device_t); 65 static int rgephy_attach(device_t); 66 67 static device_method_t rgephy_methods[] = { 68 /* device interface */ 69 DEVMETHOD(device_probe, rgephy_probe), 70 DEVMETHOD(device_attach, rgephy_attach), 71 DEVMETHOD(device_detach, mii_phy_detach), 72 DEVMETHOD(device_shutdown, bus_generic_shutdown), 73 DEVMETHOD_END 74 }; 75 76 static devclass_t rgephy_devclass; 77 78 static driver_t rgephy_driver = { 79 "rgephy", 80 rgephy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 85 86 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 87 static void rgephy_status(struct mii_softc *); 88 static int rgephy_mii_phy_auto(struct mii_softc *, int); 89 static void rgephy_reset(struct mii_softc *); 90 static int rgephy_linkup(struct mii_softc *); 91 static void rgephy_loop(struct mii_softc *); 92 static void rgephy_load_dspcode(struct mii_softc *); 93 94 static const struct mii_phydesc rgephys[] = { 95 MII_PHY_DESC(REALTEK, RTL8169S), 96 MII_PHY_DESC(REALTEK, RTL8251), 97 MII_PHY_END 98 }; 99 100 static const struct mii_phy_funcs rgephy_funcs = { 101 rgephy_service, 102 rgephy_status, 103 rgephy_reset 104 }; 105 106 static int 107 rgephy_probe(device_t dev) 108 { 109 110 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 111 } 112 113 static int 114 rgephy_attach(device_t dev) 115 { 116 struct mii_softc *sc; 117 u_int flags; 118 119 sc = device_get_softc(dev); 120 flags = 0; 121 if (mii_dev_mac_match(dev, "re")) 122 flags |= MIIF_PHYPRIV0; 123 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0); 124 125 /* RTL8169S do not report auto-sense; add manually. */ 126 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 127 sc->mii_capmask; 128 if (sc->mii_capabilities & BMSR_EXTSTAT) 129 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 130 device_printf(dev, " "); 131 mii_phy_add_media(sc); 132 printf("\n"); 133 /* 134 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with 135 * manual configuration, which is used to work around issues with 136 * certain setups by default, should not be triggered as it may in 137 * turn cause harm in some edge cases. 138 */ 139 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0; 140 141 PHY_RESET(sc); 142 143 MIIBUS_MEDIAINIT(sc->mii_dev); 144 return (0); 145 } 146 147 static int 148 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 149 { 150 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 151 int speed, gig, anar; 152 153 switch (cmd) { 154 case MII_POLLSTAT: 155 break; 156 157 case MII_MEDIACHG: 158 PHY_RESET(sc); /* XXX hardware bug work-around */ 159 160 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 161 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 162 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 163 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 164 165 switch (IFM_SUBTYPE(ife->ifm_media)) { 166 case IFM_AUTO: 167 #ifdef foo 168 /* 169 * If we're already in auto mode, just return. 170 */ 171 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 172 return (0); 173 #endif 174 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 175 break; 176 case IFM_1000_T: 177 speed = RGEPHY_S1000; 178 goto setit; 179 case IFM_100_TX: 180 speed = RGEPHY_S100; 181 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 182 goto setit; 183 case IFM_10_T: 184 speed = RGEPHY_S10; 185 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 186 setit: 187 if ((ife->ifm_media & IFM_FLOW) != 0 && 188 (mii->mii_media.ifm_media & IFM_FLAG0) != 0) 189 return (EINVAL); 190 191 if ((ife->ifm_media & IFM_FDX) != 0) { 192 speed |= RGEPHY_BMCR_FDX; 193 gig = RGEPHY_1000CTL_AFD; 194 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 195 if ((ife->ifm_media & IFM_FLOW) != 0 || 196 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 197 anar |= 198 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 199 } else { 200 gig = RGEPHY_1000CTL_AHD; 201 anar &= 202 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 203 } 204 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 205 gig |= RGEPHY_1000CTL_MSE; 206 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 207 gig |= RGEPHY_1000CTL_MSC; 208 } else { 209 gig = 0; 210 anar &= ~RGEPHY_ANAR_ASP; 211 } 212 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) 213 speed |= 214 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; 215 rgephy_loop(sc); 216 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 217 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 218 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 219 break; 220 case IFM_NONE: 221 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 222 break; 223 default: 224 return (EINVAL); 225 } 226 break; 227 228 case MII_TICK: 229 /* 230 * Only used for autonegotiation. 231 */ 232 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 233 sc->mii_ticks = 0; 234 break; 235 } 236 237 /* 238 * Check to see if we have link. If we do, we don't 239 * need to restart the autonegotiation process. 240 */ 241 if (rgephy_linkup(sc) != 0) { 242 sc->mii_ticks = 0; 243 break; 244 } 245 246 /* Announce link loss right after it happens. */ 247 if (sc->mii_ticks++ == 0) 248 break; 249 250 /* Only retry autonegotiation every mii_anegticks seconds. */ 251 if (sc->mii_ticks <= sc->mii_anegticks) 252 return (0); 253 254 sc->mii_ticks = 0; 255 rgephy_mii_phy_auto(sc, ife->ifm_media); 256 break; 257 } 258 259 /* Update the media status. */ 260 PHY_STATUS(sc); 261 262 /* 263 * Callback if something changed. Note that we need to poke 264 * the DSP on the RealTek PHYs if the media changes. 265 * 266 */ 267 if (sc->mii_media_active != mii->mii_media_active || 268 sc->mii_media_status != mii->mii_media_status || 269 cmd == MII_MEDIACHG) { 270 rgephy_load_dspcode(sc); 271 } 272 mii_phy_update(sc, cmd); 273 return (0); 274 } 275 276 static int 277 rgephy_linkup(struct mii_softc *sc) 278 { 279 int linkup; 280 uint16_t reg; 281 282 linkup = 0; 283 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && 284 sc->mii_mpd_rev >= RGEPHY_8211B) { 285 if (sc->mii_mpd_rev == RGEPHY_8211F) { 286 reg = PHY_READ(sc, RGEPHY_F_MII_SSR); 287 if (reg & RGEPHY_F_SSR_LINK) 288 linkup++; 289 } else { 290 reg = PHY_READ(sc, RGEPHY_MII_SSR); 291 if (reg & RGEPHY_SSR_LINK) 292 linkup++; 293 } 294 } else { 295 reg = PHY_READ(sc, RL_GMEDIASTAT); 296 if (reg & RL_GMEDIASTAT_LINK) 297 linkup++; 298 } 299 300 return (linkup); 301 } 302 303 static void 304 rgephy_status(struct mii_softc *sc) 305 { 306 struct mii_data *mii = sc->mii_pdata; 307 int bmsr, bmcr; 308 uint16_t ssr; 309 310 mii->mii_media_status = IFM_AVALID; 311 mii->mii_media_active = IFM_ETHER; 312 313 if (rgephy_linkup(sc) != 0) 314 mii->mii_media_status |= IFM_ACTIVE; 315 316 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 317 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 318 if (bmcr & RGEPHY_BMCR_ISO) { 319 mii->mii_media_active |= IFM_NONE; 320 mii->mii_media_status = 0; 321 return; 322 } 323 324 if (bmcr & RGEPHY_BMCR_LOOP) 325 mii->mii_media_active |= IFM_LOOP; 326 327 if (bmcr & RGEPHY_BMCR_AUTOEN) { 328 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 329 /* Erg, still trying, I guess... */ 330 mii->mii_media_active |= IFM_NONE; 331 return; 332 } 333 } 334 335 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && 336 sc->mii_mpd_rev >= RGEPHY_8211B) { 337 if (sc->mii_mpd_rev == RGEPHY_8211F) { 338 ssr = PHY_READ(sc, RGEPHY_F_MII_SSR); 339 switch (ssr & RGEPHY_F_SSR_SPD_MASK) { 340 case RGEPHY_F_SSR_S1000: 341 mii->mii_media_active |= IFM_1000_T; 342 break; 343 case RGEPHY_F_SSR_S100: 344 mii->mii_media_active |= IFM_100_TX; 345 break; 346 case RGEPHY_F_SSR_S10: 347 mii->mii_media_active |= IFM_10_T; 348 break; 349 default: 350 mii->mii_media_active |= IFM_NONE; 351 break; 352 } 353 if (ssr & RGEPHY_F_SSR_FDX) 354 mii->mii_media_active |= IFM_FDX; 355 else 356 mii->mii_media_active |= IFM_HDX; 357 358 } else { 359 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 360 switch (ssr & RGEPHY_SSR_SPD_MASK) { 361 case RGEPHY_SSR_S1000: 362 mii->mii_media_active |= IFM_1000_T; 363 break; 364 case RGEPHY_SSR_S100: 365 mii->mii_media_active |= IFM_100_TX; 366 break; 367 case RGEPHY_SSR_S10: 368 mii->mii_media_active |= IFM_10_T; 369 break; 370 default: 371 mii->mii_media_active |= IFM_NONE; 372 break; 373 } 374 if (ssr & RGEPHY_SSR_FDX) 375 mii->mii_media_active |= IFM_FDX; 376 else 377 mii->mii_media_active |= IFM_HDX; 378 } 379 } else { 380 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 381 if (bmsr & RL_GMEDIASTAT_1000MBPS) 382 mii->mii_media_active |= IFM_1000_T; 383 else if (bmsr & RL_GMEDIASTAT_100MBPS) 384 mii->mii_media_active |= IFM_100_TX; 385 else if (bmsr & RL_GMEDIASTAT_10MBPS) 386 mii->mii_media_active |= IFM_10_T; 387 else 388 mii->mii_media_active |= IFM_NONE; 389 if (bmsr & RL_GMEDIASTAT_FDX) 390 mii->mii_media_active |= IFM_FDX; 391 else 392 mii->mii_media_active |= IFM_HDX; 393 } 394 395 if ((mii->mii_media_active & IFM_FDX) != 0) 396 mii->mii_media_active |= mii_phy_flowstatus(sc); 397 398 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 399 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 400 mii->mii_media_active |= IFM_ETH_MASTER; 401 } 402 403 static int 404 rgephy_mii_phy_auto(struct mii_softc *sc, int media) 405 { 406 int anar; 407 408 rgephy_loop(sc); 409 PHY_RESET(sc); 410 411 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 412 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 413 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 414 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 415 DELAY(1000); 416 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 417 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 418 DELAY(1000); 419 PHY_WRITE(sc, RGEPHY_MII_BMCR, 420 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 421 DELAY(100); 422 423 return (EJUSTRETURN); 424 } 425 426 static void 427 rgephy_loop(struct mii_softc *sc) 428 { 429 int i; 430 431 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 432 sc->mii_mpd_rev < RGEPHY_8211B) { 433 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 434 DELAY(1000); 435 } 436 437 for (i = 0; i < 15000; i++) { 438 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 439 #if 0 440 device_printf(sc->mii_dev, "looped %d\n", i); 441 #endif 442 break; 443 } 444 DELAY(10); 445 } 446 } 447 448 #define PHY_SETBIT(x, y, z) \ 449 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 450 #define PHY_CLRBIT(x, y, z) \ 451 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 452 453 /* 454 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 455 * existing revisions of the 8169S/8110S chips need to be tuned in 456 * order to reliably negotiate a 1000Mbps link. This is only needed 457 * for rev 0 and rev 1 of the PHY. Later versions work without 458 * any fixups. 459 */ 460 static void 461 rgephy_load_dspcode(struct mii_softc *sc) 462 { 463 int val; 464 465 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 466 sc->mii_mpd_rev >= RGEPHY_8211B) 467 return; 468 469 PHY_WRITE(sc, 31, 0x0001); 470 PHY_WRITE(sc, 21, 0x1000); 471 PHY_WRITE(sc, 24, 0x65C7); 472 PHY_CLRBIT(sc, 4, 0x0800); 473 val = PHY_READ(sc, 4) & 0xFFF; 474 PHY_WRITE(sc, 4, val); 475 PHY_WRITE(sc, 3, 0x00A1); 476 PHY_WRITE(sc, 2, 0x0008); 477 PHY_WRITE(sc, 1, 0x1020); 478 PHY_WRITE(sc, 0, 0x1000); 479 PHY_SETBIT(sc, 4, 0x0800); 480 PHY_CLRBIT(sc, 4, 0x0800); 481 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 482 PHY_WRITE(sc, 4, val); 483 PHY_WRITE(sc, 3, 0xFF41); 484 PHY_WRITE(sc, 2, 0xDE60); 485 PHY_WRITE(sc, 1, 0x0140); 486 PHY_WRITE(sc, 0, 0x0077); 487 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 488 PHY_WRITE(sc, 4, val); 489 PHY_WRITE(sc, 3, 0xDF01); 490 PHY_WRITE(sc, 2, 0xDF20); 491 PHY_WRITE(sc, 1, 0xFF95); 492 PHY_WRITE(sc, 0, 0xFA00); 493 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 494 PHY_WRITE(sc, 4, val); 495 PHY_WRITE(sc, 3, 0xFF41); 496 PHY_WRITE(sc, 2, 0xDE20); 497 PHY_WRITE(sc, 1, 0x0140); 498 PHY_WRITE(sc, 0, 0x00BB); 499 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 500 PHY_WRITE(sc, 4, val); 501 PHY_WRITE(sc, 3, 0xDF01); 502 PHY_WRITE(sc, 2, 0xDF20); 503 PHY_WRITE(sc, 1, 0xFF95); 504 PHY_WRITE(sc, 0, 0xBF00); 505 PHY_SETBIT(sc, 4, 0x0800); 506 PHY_CLRBIT(sc, 4, 0x0800); 507 PHY_WRITE(sc, 31, 0x0000); 508 509 DELAY(40); 510 } 511 512 static void 513 rgephy_reset(struct mii_softc *sc) 514 { 515 uint16_t pcr, ssr; 516 517 switch (sc->mii_mpd_rev) { 518 case RGEPHY_8211F: 519 pcr = PHY_READ(sc, RGEPHY_F_MII_PCR1); 520 if ((pcr & RGEPHY_F_PCR1_MDI_MM) != 0) { 521 pcr &= ~RGEPHY_F_PCR1_MDI_MM; 522 PHY_WRITE(sc, RGEPHY_F_MII_PCR1, pcr); 523 } 524 break; 525 case RGEPHY_8211C: 526 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0) { 527 /* RTL8211C(L) */ 528 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 529 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 530 ssr &= ~RGEPHY_SSR_ALDPS; 531 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 532 } 533 } 534 /* FALLTHROUGH */ 535 default: 536 if (sc->mii_mpd_rev >= RGEPHY_8211B) { 537 pcr = PHY_READ(sc, RGEPHY_MII_PCR); 538 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { 539 pcr &= ~RGEPHY_PCR_MDI_MASK; 540 pcr |= RGEPHY_PCR_MDIX_AUTO; 541 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); 542 } 543 } 544 break; 545 } 546 547 mii_phy_reset(sc); 548 DELAY(1000); 549 rgephy_load_dspcode(sc); 550 } 551