1 /*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/rgephyreg.h> 56 57 #include "miibus_if.h" 58 59 #include <machine/bus.h> 60 #include <pci/if_rlreg.h> 61 62 static int rgephy_probe(device_t); 63 static int rgephy_attach(device_t); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 int mii_model; 68 int mii_revision; 69 }; 70 71 static device_method_t rgephy_methods[] = { 72 /* device interface */ 73 DEVMETHOD(device_probe, rgephy_probe), 74 DEVMETHOD(device_attach, rgephy_attach), 75 DEVMETHOD(device_detach, mii_phy_detach), 76 DEVMETHOD(device_shutdown, bus_generic_shutdown), 77 { 0, 0 } 78 }; 79 80 static devclass_t rgephy_devclass; 81 82 static driver_t rgephy_driver = { 83 "rgephy", 84 rgephy_methods, 85 sizeof(struct rgephy_softc) 86 }; 87 88 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 89 90 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 91 static void rgephy_status(struct mii_softc *); 92 static int rgephy_mii_phy_auto(struct mii_softc *, int); 93 static void rgephy_reset(struct mii_softc *); 94 static void rgephy_loop(struct mii_softc *); 95 static void rgephy_load_dspcode(struct mii_softc *); 96 97 static const struct mii_phydesc rgephys[] = { 98 MII_PHY_DESC(xxREALTEK, RTL8169S), 99 MII_PHY_END 100 }; 101 102 static int 103 rgephy_probe(device_t dev) 104 { 105 106 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 107 } 108 109 static int 110 rgephy_attach(device_t dev) 111 { 112 struct rgephy_softc *rsc; 113 struct mii_softc *sc; 114 struct mii_attach_args *ma; 115 struct mii_data *mii; 116 117 rsc = device_get_softc(dev); 118 sc = &rsc->mii_sc; 119 ma = device_get_ivars(dev); 120 sc->mii_dev = device_get_parent(dev); 121 mii = ma->mii_data; 122 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 123 124 sc->mii_flags = miibus_get_flags(dev); 125 sc->mii_inst = mii->mii_instance++; 126 sc->mii_phy = ma->mii_phyno; 127 sc->mii_service = rgephy_service; 128 sc->mii_pdata = mii; 129 130 rsc->mii_model = MII_MODEL(ma->mii_id2); 131 rsc->mii_revision = MII_REV(ma->mii_id2); 132 133 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 134 135 #if 0 136 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 137 MII_MEDIA_100_TX); 138 #endif 139 140 /* RTL8169S do not report auto-sense; add manually. */ 141 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 142 ma->mii_capmask; 143 if (sc->mii_capabilities & BMSR_EXTSTAT) 144 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 145 device_printf(dev, " "); 146 mii_phy_add_media(sc); 147 printf("\n"); 148 #undef ADD 149 150 rgephy_reset(sc); 151 MIIBUS_MEDIAINIT(sc->mii_dev); 152 return (0); 153 } 154 155 static int 156 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 157 { 158 struct rgephy_softc *rsc; 159 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 160 int reg, speed, gig, anar; 161 162 rsc = (struct rgephy_softc *)sc; 163 164 switch (cmd) { 165 case MII_POLLSTAT: 166 break; 167 168 case MII_MEDIACHG: 169 /* 170 * If the interface is not up, don't do anything. 171 */ 172 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 173 break; 174 175 rgephy_reset(sc); /* XXX hardware bug work-around */ 176 177 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 178 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 179 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 180 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 181 182 switch (IFM_SUBTYPE(ife->ifm_media)) { 183 case IFM_AUTO: 184 #ifdef foo 185 /* 186 * If we're already in auto mode, just return. 187 */ 188 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 189 return (0); 190 #endif 191 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 192 break; 193 case IFM_1000_T: 194 speed = RGEPHY_S1000; 195 goto setit; 196 case IFM_100_TX: 197 speed = RGEPHY_S100; 198 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 199 goto setit; 200 case IFM_10_T: 201 speed = RGEPHY_S10; 202 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 203 setit: 204 rgephy_loop(sc); 205 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 206 speed |= RGEPHY_BMCR_FDX; 207 gig = RGEPHY_1000CTL_AFD; 208 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 209 } else { 210 gig = RGEPHY_1000CTL_AHD; 211 anar &= 212 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 213 } 214 215 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 216 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 217 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 218 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 219 RGEPHY_BMCR_AUTOEN | 220 RGEPHY_BMCR_STARTNEG); 221 break; 222 } 223 224 if ((ife->ifm_media & IFM_FLOW) != 0 || 225 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 226 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 227 228 gig |= RGEPHY_1000CTL_MSE; 229 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 230 gig |= RGEPHY_1000CTL_MSC; 231 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 232 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 233 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 234 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 235 break; 236 case IFM_NONE: 237 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 238 break; 239 default: 240 return (EINVAL); 241 } 242 break; 243 244 case MII_TICK: 245 /* 246 * Is the interface even up? 247 */ 248 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 249 return (0); 250 251 /* 252 * Only used for autonegotiation. 253 */ 254 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 255 sc->mii_ticks = 0; 256 break; 257 } 258 259 /* 260 * Check to see if we have link. If we do, we don't 261 * need to restart the autonegotiation process. Read 262 * the BMSR twice in case it's latched. 263 */ 264 if (rsc->mii_revision >= 2) { 265 /* RTL8211B(L) */ 266 reg = PHY_READ(sc, RGEPHY_MII_SSR); 267 if (reg & RGEPHY_SSR_LINK) { 268 sc->mii_ticks = 0; 269 break; 270 } 271 } else { 272 reg = PHY_READ(sc, RL_GMEDIASTAT); 273 if (reg & RL_GMEDIASTAT_LINK) { 274 sc->mii_ticks = 0; 275 break; 276 } 277 } 278 279 /* Announce link loss right after it happens. */ 280 if (sc->mii_ticks++ == 0) 281 break; 282 283 /* Only retry autonegotiation every mii_anegticks seconds. */ 284 if (sc->mii_ticks <= sc->mii_anegticks) 285 return (0); 286 287 sc->mii_ticks = 0; 288 rgephy_mii_phy_auto(sc, ife->ifm_media); 289 break; 290 } 291 292 /* Update the media status. */ 293 rgephy_status(sc); 294 295 /* 296 * Callback if something changed. Note that we need to poke 297 * the DSP on the RealTek PHYs if the media changes. 298 * 299 */ 300 if (sc->mii_media_active != mii->mii_media_active || 301 sc->mii_media_status != mii->mii_media_status || 302 cmd == MII_MEDIACHG) { 303 rgephy_load_dspcode(sc); 304 } 305 mii_phy_update(sc, cmd); 306 return (0); 307 } 308 309 static void 310 rgephy_status(struct mii_softc *sc) 311 { 312 struct rgephy_softc *rsc; 313 struct mii_data *mii = sc->mii_pdata; 314 int bmsr, bmcr; 315 uint16_t ssr; 316 317 mii->mii_media_status = IFM_AVALID; 318 mii->mii_media_active = IFM_ETHER; 319 320 rsc = (struct rgephy_softc *)sc; 321 if (rsc->mii_revision >= 2) { 322 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 323 if (ssr & RGEPHY_SSR_LINK) 324 mii->mii_media_status |= IFM_ACTIVE; 325 } else { 326 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 327 if (bmsr & RL_GMEDIASTAT_LINK) 328 mii->mii_media_status |= IFM_ACTIVE; 329 } 330 331 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 332 333 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 334 if (bmcr & RGEPHY_BMCR_ISO) { 335 mii->mii_media_active |= IFM_NONE; 336 mii->mii_media_status = 0; 337 return; 338 } 339 340 if (bmcr & RGEPHY_BMCR_LOOP) 341 mii->mii_media_active |= IFM_LOOP; 342 343 if (bmcr & RGEPHY_BMCR_AUTOEN) { 344 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 345 /* Erg, still trying, I guess... */ 346 mii->mii_media_active |= IFM_NONE; 347 return; 348 } 349 } 350 351 if (rsc->mii_revision >= 2) { 352 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 353 switch (ssr & RGEPHY_SSR_SPD_MASK) { 354 case RGEPHY_SSR_S1000: 355 mii->mii_media_active |= IFM_1000_T; 356 break; 357 case RGEPHY_SSR_S100: 358 mii->mii_media_active |= IFM_100_TX; 359 break; 360 case RGEPHY_SSR_S10: 361 mii->mii_media_active |= IFM_10_T; 362 break; 363 default: 364 mii->mii_media_active |= IFM_NONE; 365 break; 366 } 367 if (ssr & RGEPHY_SSR_FDX) 368 mii->mii_media_active |= IFM_FDX; 369 else 370 mii->mii_media_active |= IFM_HDX; 371 } else { 372 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 373 if (bmsr & RL_GMEDIASTAT_1000MBPS) 374 mii->mii_media_active |= IFM_1000_T; 375 else if (bmsr & RL_GMEDIASTAT_100MBPS) 376 mii->mii_media_active |= IFM_100_TX; 377 else if (bmsr & RL_GMEDIASTAT_10MBPS) 378 mii->mii_media_active |= IFM_10_T; 379 else 380 mii->mii_media_active |= IFM_NONE; 381 if (bmsr & RL_GMEDIASTAT_FDX) 382 mii->mii_media_active |= IFM_FDX; 383 else 384 mii->mii_media_active |= IFM_HDX; 385 } 386 387 if ((mii->mii_media_active & IFM_FDX) != 0) 388 mii->mii_media_active |= mii_phy_flowstatus(sc); 389 390 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 391 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 392 mii->mii_media_active |= IFM_ETH_MASTER; 393 } 394 395 static int 396 rgephy_mii_phy_auto(struct mii_softc *sc, int media) 397 { 398 int anar; 399 400 rgephy_loop(sc); 401 rgephy_reset(sc); 402 403 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 404 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 405 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 406 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 407 DELAY(1000); 408 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 409 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 410 DELAY(1000); 411 PHY_WRITE(sc, RGEPHY_MII_BMCR, 412 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 413 DELAY(100); 414 415 return (EJUSTRETURN); 416 } 417 418 static void 419 rgephy_loop(struct mii_softc *sc) 420 { 421 struct rgephy_softc *rsc; 422 int i; 423 424 rsc = (struct rgephy_softc *)sc; 425 if (rsc->mii_revision < 2) { 426 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 427 DELAY(1000); 428 } 429 430 for (i = 0; i < 15000; i++) { 431 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 432 #if 0 433 device_printf(sc->mii_dev, "looped %d\n", i); 434 #endif 435 break; 436 } 437 DELAY(10); 438 } 439 } 440 441 #define PHY_SETBIT(x, y, z) \ 442 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 443 #define PHY_CLRBIT(x, y, z) \ 444 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 445 446 /* 447 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 448 * existing revisions of the 8169S/8110S chips need to be tuned in 449 * order to reliably negotiate a 1000Mbps link. This is only needed 450 * for rev 0 and rev 1 of the PHY. Later versions work without 451 * any fixups. 452 */ 453 static void 454 rgephy_load_dspcode(struct mii_softc *sc) 455 { 456 struct rgephy_softc *rsc; 457 int val; 458 459 rsc = (struct rgephy_softc *)sc; 460 if (rsc->mii_revision >= 2) 461 return; 462 463 PHY_WRITE(sc, 31, 0x0001); 464 PHY_WRITE(sc, 21, 0x1000); 465 PHY_WRITE(sc, 24, 0x65C7); 466 PHY_CLRBIT(sc, 4, 0x0800); 467 val = PHY_READ(sc, 4) & 0xFFF; 468 PHY_WRITE(sc, 4, val); 469 PHY_WRITE(sc, 3, 0x00A1); 470 PHY_WRITE(sc, 2, 0x0008); 471 PHY_WRITE(sc, 1, 0x1020); 472 PHY_WRITE(sc, 0, 0x1000); 473 PHY_SETBIT(sc, 4, 0x0800); 474 PHY_CLRBIT(sc, 4, 0x0800); 475 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 476 PHY_WRITE(sc, 4, val); 477 PHY_WRITE(sc, 3, 0xFF41); 478 PHY_WRITE(sc, 2, 0xDE60); 479 PHY_WRITE(sc, 1, 0x0140); 480 PHY_WRITE(sc, 0, 0x0077); 481 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 482 PHY_WRITE(sc, 4, val); 483 PHY_WRITE(sc, 3, 0xDF01); 484 PHY_WRITE(sc, 2, 0xDF20); 485 PHY_WRITE(sc, 1, 0xFF95); 486 PHY_WRITE(sc, 0, 0xFA00); 487 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 488 PHY_WRITE(sc, 4, val); 489 PHY_WRITE(sc, 3, 0xFF41); 490 PHY_WRITE(sc, 2, 0xDE20); 491 PHY_WRITE(sc, 1, 0x0140); 492 PHY_WRITE(sc, 0, 0x00BB); 493 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 494 PHY_WRITE(sc, 4, val); 495 PHY_WRITE(sc, 3, 0xDF01); 496 PHY_WRITE(sc, 2, 0xDF20); 497 PHY_WRITE(sc, 1, 0xFF95); 498 PHY_WRITE(sc, 0, 0xBF00); 499 PHY_SETBIT(sc, 4, 0x0800); 500 PHY_CLRBIT(sc, 4, 0x0800); 501 PHY_WRITE(sc, 31, 0x0000); 502 503 DELAY(40); 504 } 505 506 static void 507 rgephy_reset(struct mii_softc *sc) 508 { 509 struct rgephy_softc *rsc; 510 uint16_t ssr; 511 512 rsc = (struct rgephy_softc *)sc; 513 if (rsc->mii_revision == 3) { 514 /* RTL8211C(L) */ 515 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 516 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 517 ssr &= ~RGEPHY_SSR_ALDPS; 518 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 519 } 520 } 521 522 mii_phy_reset(sc); 523 DELAY(1000); 524 rgephy_load_dspcode(sc); 525 } 526