1 /* $NetBSD: nsphyreg.h,v 1.1 1998/08/10 23:58:39 thorpej Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause-NetBSD 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 11 * NASA Ames Research Center. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 #ifndef _DEV_MII_NSPHYREG_H_ 38 #define _DEV_MII_NSPHYREG_H_ 39 40 /* 41 * DP83840 registers. 42 */ 43 44 #define MII_NSPHY_DCR 0x12 /* Disconnect counter */ 45 46 #define MII_NSPHY_FCSCR 0x13 /* False carrier sense counter */ 47 48 #define MII_NSPHY_RECR 0x15 /* Receive error counter */ 49 50 #define MII_NSPHY_SRR 0x16 /* Silicon revision */ 51 52 #define MII_NSPHY_PCR 0x17 /* PCS sub-layer configuration */ 53 #define PCR_NRZI 0x8000 /* NRZI encoding enabled for 100TX */ 54 #define PCR_DESCRTOSEL 0x4000 /* descrambler t/o select (2ms) */ 55 #define PCR_DESCRTODIS 0x2000 /* descrambler t/o disable */ 56 #define PCR_REPEATER 0x1000 /* repeater mode */ 57 #define PCR_ENCSEL 0x0800 /* encoder mode select */ 58 #define PCR_CLK25MDIS 0x0080 /* CLK25M disable */ 59 #define PCR_FLINK100 0x0040 /* force good link in 100mbps */ 60 #define PCR_CIMDIS 0x0020 /* carrier integrity monitor disable */ 61 #define PCR_TXOFF 0x0010 /* force transmit off */ 62 #define PCR_LED1MODE 0x0004 /* LED1 mode: see below */ 63 #define PCR_LED4MODE 0x0002 /* LED4 mode: see below */ 64 65 /* 66 * LED1 Mode: 67 * 68 * 1 LED1 output configured to PAR's CON_STATUS, useful for 69 * network management in 100baseTX mode. 70 * 71 * 0 Normal LED1 operation - 10baseTX and 100baseTX transmission 72 * activity. 73 * 74 * LED4 Mode: 75 * 76 * 1 LED4 output configured to indicate full-duplex in both 77 * 10baseT and 100baseTX modes. 78 * 79 * 0 LED4 output configured to indicate polarity in 10baseT 80 * mode and full-duplex in 100baseTX mode. 81 */ 82 83 #define MII_NSPHY_LBREMR 0x18 /* Loopback, bypass, error mask */ 84 #define LBREMR_BADSSDEN 0x8000 /* enable bad SSD detection */ 85 #define LBREMR_BP4B5B 0x4000 /* bypass 4b/5b encoding */ 86 #define LBREMR_BPSCR 0x2000 /* bypass scrambler */ 87 #define LBREMR_BPALIGN 0x1000 /* bypass alignment function */ 88 #define LBREMR_10LOOP 0x0800 /* 10baseT loopback */ 89 #define LBREMR_LB1 0x0200 /* loopback ctl 1 */ 90 #define LBREMR_LB0 0x0100 /* loopback ctl 0 */ 91 #define LBREMR_ALTCRS 0x0040 /* alt crs operation */ 92 #define LBREMR_LOOPXMTDIS 0x0020 /* disable transmit in 100TX loopbk */ 93 #define LBREMR_CODEERR 0x0010 /* code errors */ 94 #define LBREMR_PEERR 0x0008 /* premature end errors */ 95 #define LBREMR_LINKERR 0x0004 /* link errors */ 96 #define LBREMR_PKTERR 0x0002 /* packet errors */ 97 98 #define MII_NSPHY_PAR 0x19 /* Physical address and status */ 99 #define PAR_DISCRSJAB 0x0800 /* disable car sense during jab */ 100 #define PAR_ANENSTAT 0x0400 /* autoneg mode status */ 101 #define PAR_FEFIEN 0x0100 /* far end fault enable */ 102 #define PAR_FDX 0x0080 /* full duplex status */ 103 #define PAR_10 0x0040 /* 10mbps mode */ 104 #define PAR_CON 0x0020 /* connect status */ 105 #define PAR_AMASK 0x001f /* PHY address bits */ 106 107 #define MII_NSPHY_10BTSR 0x1b /* 10baseT status */ 108 #define MII_NSPHY_10BTCR 0x1c /* 10baseT configuration */ 109 110 #endif /* _DEV_MII_NSPHYREG_H_ */ 111