xref: /freebsd/sys/dev/mii/mii.h (revision 1aad4b2a52d2ae9ed13cadaaa9bc7c75774aa596)
11aad4b2aSPoul-Henning Kamp /*	$NetBSD: mii.h,v 1.9 2001/05/31 03:07:14 thorpej Exp $	*/
2d0027533SBill Paul 
3d0027533SBill Paul /*
4d0027533SBill Paul  * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
5d0027533SBill Paul  *
6d0027533SBill Paul  * Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe,
7d0027533SBill Paul  * Numerical Aerospace Simulation Facility, NASA Ames Research Center.
8d0027533SBill Paul  *
9d0027533SBill Paul  * Redistribution and use in source and binary forms, with or without
10d0027533SBill Paul  * modification, are permitted provided that the following conditions
11d0027533SBill Paul  * are met:
12d0027533SBill Paul  * 1. Redistributions of source code must retain the above copyright
13d0027533SBill Paul  *    notice, this list of conditions and the following disclaimer.
14d0027533SBill Paul  * 2. Redistributions in binary form must reproduce the above copyright
15d0027533SBill Paul  *    notice, this list of conditions and the following disclaimer in the
16d0027533SBill Paul  *    documentation and/or other materials provided with the distribution.
17d0027533SBill Paul  * 3. All advertising materials mentioning features or use of this software
18d0027533SBill Paul  *    must display the following acknowledgement:
19d0027533SBill Paul  *	This product includes software developed by Manuel Bouyer.
20d0027533SBill Paul  * 4. The name of the author may not be used to endorse or promote products
21d0027533SBill Paul  *    derived from this software without specific prior written permission.
22d0027533SBill Paul  *
23d0027533SBill Paul  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24d0027533SBill Paul  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25d0027533SBill Paul  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26d0027533SBill Paul  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27d0027533SBill Paul  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28d0027533SBill Paul  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29d0027533SBill Paul  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30d0027533SBill Paul  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31d0027533SBill Paul  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32d0027533SBill Paul  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33d0027533SBill Paul  *
34c3aac50fSPeter Wemm  * $FreeBSD$
35d0027533SBill Paul  */
36d0027533SBill Paul 
37d0027533SBill Paul #ifndef _DEV_MII_MII_H_
38d0027533SBill Paul #define	_DEV_MII_MII_H_
39d0027533SBill Paul 
40d0027533SBill Paul /*
41d0027533SBill Paul  * Registers common to all PHYs.
42d0027533SBill Paul  */
43d0027533SBill Paul 
44d0027533SBill Paul #define	MII_NPHY	32	/* max # of PHYs per MII */
45d0027533SBill Paul 
46d0027533SBill Paul /*
47d0027533SBill Paul  * MII commands, used if a device must drive the MII lines
48d0027533SBill Paul  * manually.
49d0027533SBill Paul  */
50d0027533SBill Paul #define	MII_COMMAND_START	0x01
51d0027533SBill Paul #define	MII_COMMAND_READ	0x02
52d0027533SBill Paul #define	MII_COMMAND_WRITE	0x01
53d0027533SBill Paul #define	MII_COMMAND_ACK		0x02
54d0027533SBill Paul 
55d0027533SBill Paul #define	MII_BMCR	0x00 	/* Basic mode control register (rw) */
56d0027533SBill Paul #define	BMCR_RESET	0x8000	/* reset */
57d0027533SBill Paul #define	BMCR_LOOP	0x4000	/* loopback */
581aad4b2aSPoul-Henning Kamp #define	BMCR_SPEED0	0x2000	/* speed selection (LSB) */
59d0027533SBill Paul #define	BMCR_AUTOEN	0x1000	/* autonegotiation enable */
60d0027533SBill Paul #define	BMCR_PDOWN	0x0800	/* power down */
61d0027533SBill Paul #define	BMCR_ISO	0x0400	/* isolate */
62d0027533SBill Paul #define	BMCR_STARTNEG	0x0200	/* restart autonegotiation */
63d0027533SBill Paul #define	BMCR_FDX	0x0100	/* Set duplex mode */
64d0027533SBill Paul #define	BMCR_CTEST	0x0080	/* collision test */
651aad4b2aSPoul-Henning Kamp #define	BMCR_SPEED1	0x0040	/* speed selection (MSB) */
661aad4b2aSPoul-Henning Kamp 
671aad4b2aSPoul-Henning Kamp #define	BMCR_S10	0x0000		/* 10 Mb/s */
681aad4b2aSPoul-Henning Kamp #define	BMCR_S100	BMCR_SPEED0	/* 100 Mb/s */
691aad4b2aSPoul-Henning Kamp #define	BMCR_S1000	BMCR_SPEED1	/* 1000 Mb/s */
701aad4b2aSPoul-Henning Kamp 
711aad4b2aSPoul-Henning Kamp #define	BMCR_SPEED(x)	((x) & (BMCR_SPEED0|BMCR_SPEED1))
72d0027533SBill Paul 
73d0027533SBill Paul #define	MII_BMSR	0x01	/* Basic mode status register (ro) */
74d0027533SBill Paul #define	BMSR_100T4	0x8000	/* 100 base T4 capable */
75d0027533SBill Paul #define	BMSR_100TXFDX	0x4000	/* 100 base Tx full duplex capable */
76d0027533SBill Paul #define	BMSR_100TXHDX	0x2000	/* 100 base Tx half duplex capable */
77d0027533SBill Paul #define	BMSR_10TFDX	0x1000	/* 10 base T full duplex capable */
78d0027533SBill Paul #define	BMSR_10THDX	0x0800	/* 10 base T half duplex capable */
791aad4b2aSPoul-Henning Kamp #define	BMSR_100T2FDX	0x0400	/* 100 base T2 full duplex capable */
801aad4b2aSPoul-Henning Kamp #define	BMSR_100T2HDX	0x0200	/* 100 base T2 half duplex capable */
811aad4b2aSPoul-Henning Kamp #define	BMSR_EXTSTAT	0x0100	/* Extended status in register 15 */
821aad4b2aSPoul-Henning Kamp #define	BMSR_MFPS	0x0040	/* MII Frame Preamble Suppression */
83d0027533SBill Paul #define	BMSR_ACOMP	0x0020	/* Autonegotiation complete */
84d0027533SBill Paul #define	BMSR_RFAULT	0x0010	/* Link partner fault */
85d0027533SBill Paul #define	BMSR_ANEG	0x0008	/* Autonegotiation capable */
86d0027533SBill Paul #define	BMSR_LINK	0x0004	/* Link status */
87d0027533SBill Paul #define	BMSR_JABBER	0x0002	/* Jabber detected */
881aad4b2aSPoul-Henning Kamp #define	BMSR_EXTCAP	0x0001	/* Extended capability */
89d0027533SBill Paul 
901aad4b2aSPoul-Henning Kamp /*
911aad4b2aSPoul-Henning Kamp  * Note that the EXTSTAT bit indicates that there is extended status
921aad4b2aSPoul-Henning Kamp  * info available in register 15, but 802.3 section 22.2.4.3 also
931aad4b2aSPoul-Henning Kamp  * states that that all 1000 Mb/s capable PHYs will set this bit to 1.
941aad4b2aSPoul-Henning Kamp  */
951aad4b2aSPoul-Henning Kamp #if 1
96d0027533SBill Paul #define	BMSR_MEDIAMASK	(BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX|BMSR_10TFDX| \
97d0027533SBill Paul 			 BMSR_10THDX|BMSR_ANEG)
98d0027533SBill Paul 
991aad4b2aSPoul-Henning Kamp #else
1001aad4b2aSPoul-Henning Kamp /* NetBSD uses: */
1011aad4b2aSPoul-Henning Kamp #define	BMSR_MEDIAMASK	(BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \
1021aad4b2aSPoul-Henning Kamp 			 BMSR_10TFDX|BMSR_10THDX|BMSR_100T2FDX|BMSR_100T2HDX)
1031aad4b2aSPoul-Henning Kamp #endif
1041aad4b2aSPoul-Henning Kamp 
105d0027533SBill Paul /*
106d0027533SBill Paul  * Convert BMSR media capabilities to ANAR bits for autonegotiation.
107d0027533SBill Paul  * Note the shift chopps off the BMSR_ANEG bit.
108d0027533SBill Paul  */
109d0027533SBill Paul #define	BMSR_MEDIA_TO_ANAR(x)	(((x) & BMSR_MEDIAMASK) >> 6)
110d0027533SBill Paul 
111d0027533SBill Paul #define	MII_PHYIDR1	0x02	/* ID register 1 (ro) */
112d0027533SBill Paul 
113d0027533SBill Paul #define	MII_PHYIDR2	0x03	/* ID register 2 (ro) */
114d0027533SBill Paul #define	IDR2_OUILSB	0xfc00	/* OUI LSB */
115d0027533SBill Paul #define	IDR2_MODEL	0x03f0	/* vendor model */
116d0027533SBill Paul #define	IDR2_REV	0x000f	/* vendor revision */
117d0027533SBill Paul 
118d0027533SBill Paul #define	MII_OUI(id1, id2)	(((id1) << 6) | ((id2) >> 10))
119d0027533SBill Paul #define	MII_MODEL(id2)		(((id2) & IDR2_MODEL) >> 4)
120d0027533SBill Paul #define	MII_REV(id2)		((id2) & IDR2_REV)
121d0027533SBill Paul 
122d0027533SBill Paul #define	MII_ANAR	0x04	/* Autonegotiation advertisement (rw) */
1231aad4b2aSPoul-Henning Kamp 		/* section 28.2.4.1 and 37.2.6.1 */
124d0027533SBill Paul #define ANAR_NP		0x8000	/* Next page (ro) */
125d0027533SBill Paul #define	ANAR_ACK	0x4000	/* link partner abilities acknowledged (ro) */
126d0027533SBill Paul #define ANAR_RF		0x2000	/* remote fault (ro) */
1271aad4b2aSPoul-Henning Kamp #define	ANAR_FC		0x0400	/* local device supports PAUSE */
128d0027533SBill Paul #define ANAR_T4		0x0200	/* local device supports 100bT4 */
129d0027533SBill Paul #define ANAR_TX_FD	0x0100	/* local device supports 100bTx FD */
130d0027533SBill Paul #define ANAR_TX		0x0080	/* local device supports 100bTx */
131d0027533SBill Paul #define ANAR_10_FD	0x0040	/* local device supports 10bT FD */
132d0027533SBill Paul #define ANAR_10		0x0020	/* local device supports 10bT */
133d0027533SBill Paul #define	ANAR_CSMA	0x0001	/* protocol selector CSMA/CD */
134d0027533SBill Paul 
1351aad4b2aSPoul-Henning Kamp #define	ANAR_X_FD	0x0020	/* local device supports 1000BASE-X FD */
1361aad4b2aSPoul-Henning Kamp #define	ANAR_X_HD	0x0040	/* local device supports 1000BASE-X HD */
1371aad4b2aSPoul-Henning Kamp #define	ANAR_X_PAUSE_NONE	(0 << 7)
1381aad4b2aSPoul-Henning Kamp #define	ANAR_X_PAUSE_SYM	(1 << 7)
1391aad4b2aSPoul-Henning Kamp #define	ANAR_X_PAUSE_ASYM	(2 << 7)
1401aad4b2aSPoul-Henning Kamp #define	ANAR_X_PAUSE_TOWARDS	(3 << 7)
1411aad4b2aSPoul-Henning Kamp 
142d0027533SBill Paul #define	MII_ANLPAR	0x05	/* Autonegotiation lnk partner abilities (rw) */
1431aad4b2aSPoul-Henning Kamp 		/* section 28.2.4.1 and 37.2.6.1 */
144d0027533SBill Paul #define ANLPAR_NP	0x8000	/* Next page (ro) */
145d0027533SBill Paul #define	ANLPAR_ACK	0x4000	/* link partner accepted ACK (ro) */
146d0027533SBill Paul #define ANLPAR_RF	0x2000	/* remote fault (ro) */
1471aad4b2aSPoul-Henning Kamp #define	ANLPAR_FC	0x0400	/* link partner supports PAUSE */
148d0027533SBill Paul #define ANLPAR_T4	0x0200	/* link partner supports 100bT4 */
149d0027533SBill Paul #define ANLPAR_TX_FD	0x0100	/* link partner supports 100bTx FD */
150d0027533SBill Paul #define ANLPAR_TX	0x0080	/* link partner supports 100bTx */
151d0027533SBill Paul #define ANLPAR_10_FD	0x0040	/* link partner supports 10bT FD */
152d0027533SBill Paul #define ANLPAR_10	0x0020	/* link partner supports 10bT */
153d0027533SBill Paul #define	ANLPAR_CSMA	0x0001	/* protocol selector CSMA/CD */
154d0027533SBill Paul 
1551aad4b2aSPoul-Henning Kamp #define	ANLPAR_X_FD	0x0020	/* local device supports 1000BASE-X FD */
1561aad4b2aSPoul-Henning Kamp #define	ANLPAR_X_HD	0x0040	/* local device supports 1000BASE-X HD */
1571aad4b2aSPoul-Henning Kamp #define	ANLPAR_X_PAUSE_MASK	(3 << 7)
1581aad4b2aSPoul-Henning Kamp #define	ANLPAR_X_PAUSE_NONE	(0 << 7)
1591aad4b2aSPoul-Henning Kamp #define	ANLPAR_X_PAUSE_SYM	(1 << 7)
1601aad4b2aSPoul-Henning Kamp #define	ANLPAR_X_PAUSE_ASYM	(2 << 7)
1611aad4b2aSPoul-Henning Kamp #define	ANLPAR_X_PAUSE_TOWARDS	(3 << 7)
1621aad4b2aSPoul-Henning Kamp 
163d0027533SBill Paul #define	MII_ANER	0x06	/* Autonegotiation expansion (ro) */
1641aad4b2aSPoul-Henning Kamp 		/* section 28.2.4.1 and 37.2.6.1 */
165d0027533SBill Paul #define ANER_MLF	0x0010	/* multiple link detection fault */
166d0027533SBill Paul #define ANER_LPNP	0x0008	/* link parter next page-able */
167d0027533SBill Paul #define ANER_NP		0x0004	/* next page-able */
168d0027533SBill Paul #define ANER_PAGE_RX	0x0002	/* Page received */
169d0027533SBill Paul #define ANER_LPAN	0x0001	/* link parter autoneg-able */
170d0027533SBill Paul 
1711aad4b2aSPoul-Henning Kamp #define	MII_ANNP	0x07	/* Autonegotiation next page */
1721aad4b2aSPoul-Henning Kamp 		/* section 28.2.4.1 and 37.2.6.1 */
1731aad4b2aSPoul-Henning Kamp 
1741aad4b2aSPoul-Henning Kamp #define	MII_ANLPRNP	0x08	/* Autonegotiation link partner rx next page */
1751aad4b2aSPoul-Henning Kamp 		/* section 32.5.1 and 37.2.6.1 */
1761aad4b2aSPoul-Henning Kamp 
1771aad4b2aSPoul-Henning Kamp 			/* This is also the 1000baseT control register */
1781aad4b2aSPoul-Henning Kamp #define	MII_100T2CR	0x09	/* 100base-T2 control register */
1791aad4b2aSPoul-Henning Kamp #define	GTCR_TEST_MASK	0xe000	/* see 802.3ab ss. 40.6.1.1.2 */
1801aad4b2aSPoul-Henning Kamp #define	GTCR_MAN_MS	0x1000	/* enable manual master/slave control */
1811aad4b2aSPoul-Henning Kamp #define	GTCR_ADV_MS	0x0800	/* 1 = adv. master, 0 = adv. slave */
1821aad4b2aSPoul-Henning Kamp #define	GTCR_PORT_TYPE	0x0400	/* 1 = DCE, 0 = DTE (NIC) */
1831aad4b2aSPoul-Henning Kamp #define	GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */
1841aad4b2aSPoul-Henning Kamp #define	GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */
1851aad4b2aSPoul-Henning Kamp 
1861aad4b2aSPoul-Henning Kamp 			/* This is also the 1000baseT status register */
1871aad4b2aSPoul-Henning Kamp #define	MII_100T2SR	0x0a	/* 100base-T2 status register */
1881aad4b2aSPoul-Henning Kamp #define	GTSR_MAN_MS_FLT	0x8000	/* master/slave config fault */
1891aad4b2aSPoul-Henning Kamp #define	GTSR_MS_RES	0x4000	/* result: 1 = master, 0 = slave */
1901aad4b2aSPoul-Henning Kamp #define	GTSR_LRS	0x2000	/* local rx status, 1 = ok */
1911aad4b2aSPoul-Henning Kamp #define	GTSR_RRS	0x1000	/* remove rx status, 1 = ok */
1921aad4b2aSPoul-Henning Kamp #define	GTSR_LP_1000TFDX 0x0800	/* link partner 1000baseT FDX capable */
1931aad4b2aSPoul-Henning Kamp #define	GTSR_LP_1000THDX 0x0400	/* link partner 1000baseT HDX capable */
1941aad4b2aSPoul-Henning Kamp #define	GTSR_LP_ASM_DIR	0x0200	/* link partner asym. pause dir. capable */
1951aad4b2aSPoul-Henning Kamp #define	GTSR_IDLE_ERR	0x00ff	/* IDLE error count */
1961aad4b2aSPoul-Henning Kamp 
1971aad4b2aSPoul-Henning Kamp #define	MII_EXTSR	0x0f	/* Extended status register */
1981aad4b2aSPoul-Henning Kamp #define	EXTSR_1000XFDX	0x8000	/* 1000X full-duplex capable */
1991aad4b2aSPoul-Henning Kamp #define	EXTSR_1000XHDX	0x4000	/* 1000X half-duplex capable */
2001aad4b2aSPoul-Henning Kamp #define	EXTSR_1000TFDX	0x2000	/* 1000T full-duplex capable */
2011aad4b2aSPoul-Henning Kamp #define	EXTSR_1000THDX	0x1000	/* 1000T half-duplex capable */
2021aad4b2aSPoul-Henning Kamp 
2031aad4b2aSPoul-Henning Kamp #define	EXTSR_MEDIAMASK	(EXTSR_1000XFDX|EXTSR_1000XHDX| \
2041aad4b2aSPoul-Henning Kamp 			 EXTSR_1000TFDX|EXTSR_1000THDX)
2051aad4b2aSPoul-Henning Kamp 
206d0027533SBill Paul #endif /* _DEV_MII_MII_H_ */
207