1 /* 2 * Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca> 3 * Copyright (c) 2022 Soren Schmidt <sos@deepcore.dk> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 16 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Motorcomm YT8511C / YT8511H Integrated 10/100/1000 Gigabit Ethernet phy 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/socket.h> 37 #include <sys/errno.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <net/if.h> 42 #include <net/if_media.h> 43 44 #include <dev/mii/mii.h> 45 #include <dev/mii/miivar.h> 46 47 #include "miibus_if.h" 48 49 #define MCOMMPHY_OUI 0x000000 50 #define MCOMMPHY_MODEL 0x10 51 #define MCOMMPHY_REV 0x0a 52 53 #define EXT_REG_ADDR 0x1e 54 #define EXT_REG_DATA 0x1f 55 56 /* Extended registers */ 57 #define PHY_CLOCK_GATING_REG 0x0c 58 #define RX_CLK_DELAY_EN 0x0001 59 #define CLK_25M_SEL 0x0006 60 #define CLK_25M_SEL_125M 3 61 #define TX_CLK_DELAY_SEL 0x00f0 62 #define PHY_SLEEP_CONTROL1_REG 0x27 63 #define PLLON_IN_SLP 0x4000 64 65 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask)) 66 #define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask)) 67 68 static int 69 mcommphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 70 { 71 switch (cmd) { 72 case MII_POLLSTAT: 73 break; 74 75 case MII_MEDIACHG: 76 mii_phy_setmedia(sc); 77 break; 78 79 case MII_TICK: 80 if (mii_phy_tick(sc) == EJUSTRETURN) 81 return (0); 82 break; 83 } 84 85 /* Update the media status. */ 86 PHY_STATUS(sc); 87 88 /* Callback if something changed. */ 89 mii_phy_update(sc, cmd); 90 91 return (0); 92 } 93 94 static const struct mii_phy_funcs mcommphy_funcs = { 95 mcommphy_service, 96 ukphy_status, 97 mii_phy_reset 98 }; 99 100 static int 101 mcommphy_probe(device_t dev) 102 { 103 struct mii_attach_args *ma = device_get_ivars(dev); 104 105 /* 106 * The YT8511C reports an OUI of 0. Best we can do here is to match 107 * exactly the contents of the PHY identification registers. 108 */ 109 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MCOMMPHY_OUI && 110 MII_MODEL(ma->mii_id2) == MCOMMPHY_MODEL && 111 MII_REV(ma->mii_id2) == MCOMMPHY_REV) { 112 device_set_desc(dev, "Motorcomm YT8511 media interface"); 113 return BUS_PROBE_DEFAULT; 114 } 115 return (ENXIO); 116 } 117 118 static int 119 mcommphy_attach(device_t dev) 120 { 121 struct mii_softc *sc = device_get_softc(dev); 122 uint16_t oldaddr, data; 123 124 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &mcommphy_funcs, 0); 125 126 PHY_RESET(sc); 127 128 /* begin chip stuff */ 129 oldaddr = PHY_READ(sc, EXT_REG_ADDR); 130 131 PHY_WRITE(sc, EXT_REG_ADDR, PHY_CLOCK_GATING_REG); 132 data = PHY_READ(sc, EXT_REG_DATA); 133 data &= ~CLK_25M_SEL; 134 data |= SHIFTIN(CLK_25M_SEL_125M, CLK_25M_SEL);; 135 if (sc->mii_flags & MIIF_RX_DELAY) { 136 data |= RX_CLK_DELAY_EN; 137 } else { 138 data &= ~RX_CLK_DELAY_EN; 139 } 140 data &= ~TX_CLK_DELAY_SEL; 141 if (sc->mii_flags & MIIF_TX_DELAY) { 142 data |= SHIFTIN(0xf, TX_CLK_DELAY_SEL); 143 } else { 144 data |= SHIFTIN(0x2, TX_CLK_DELAY_SEL); 145 } 146 PHY_WRITE(sc, EXT_REG_DATA, data); 147 148 PHY_WRITE(sc, EXT_REG_ADDR, PHY_SLEEP_CONTROL1_REG); 149 data = PHY_READ(sc, EXT_REG_DATA); 150 data |= PLLON_IN_SLP; 151 PHY_WRITE(sc, EXT_REG_DATA, data); 152 153 PHY_WRITE(sc, EXT_REG_ADDR, oldaddr); 154 /* end chip stuff */ 155 156 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 157 if (sc->mii_capabilities & BMSR_EXTSTAT) 158 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 159 device_printf(dev, " "); 160 mii_phy_add_media(sc); 161 printf("\n"); 162 163 MIIBUS_MEDIAINIT(sc->mii_dev); 164 165 return (0); 166 } 167 168 169 static device_method_t mcommphy_methods[] = { 170 /* device interface */ 171 DEVMETHOD(device_probe, mcommphy_probe), 172 DEVMETHOD(device_attach, mcommphy_attach), 173 DEVMETHOD(device_detach, mii_phy_detach), 174 DEVMETHOD(device_shutdown, bus_generic_shutdown), 175 DEVMETHOD_END 176 }; 177 178 static driver_t mcommphy_driver = { 179 "mcommphy", 180 mcommphy_methods, 181 sizeof(struct mii_softc) 182 }; 183 184 DRIVER_MODULE(mcommphy, miibus, mcommphy_driver, 0, 0); 185