xref: /freebsd/sys/dev/mii/jmphyreg.h (revision 9a14aa017b21c292740c00ee098195cd46642730)
1 /*-
2  * Copyright (c) 2008, Pyun YongHyeon
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD$
28  */
29 
30 #ifndef	_DEV_MII_JMPHYREG_H_
31 #define	_DEV_MII_JMPHYREG_H_
32 
33 /*
34  * Registers for the JMicron JMC250 Gigabit PHY.
35  */
36 
37 /* PHY specific status register. */
38 #define JMPHY_SSR			0x11
39 #define JMPHY_SSR_SPEED_1000		0x8000
40 #define JMPHY_SSR_SPEED_100		0x4000
41 #define JMPHY_SSR_SPEED_10		0x0000
42 #define JMPHY_SSR_SPEED_MASK		0xC000
43 #define JMPHY_SSR_DUPLEX		0x2000
44 #define JMPHY_SSR_SPD_DPLX_RESOLVED	0x0800
45 #define JMPHY_SSR_LINK_UP		0x0400
46 #define JMPHY_SSR_MDI_XOVER		0x0040
47 #define	JMPHY_SSR_INV_POLARITY		0x0002
48 
49 /* PHY specific cable length status register. */
50 #define	JMPHY_SCL			0x17
51 #define	JMPHY_SCL_CHAN_D_MASK		0xF000
52 #define	JMPHY_SCL_CHAN_C_MASK		0x0F00
53 #define	JMPHY_SCL_CHAN_B_MASK		0x00F0
54 #define	JMPHY_SCL_CHAN_A_MASK		0x000F
55 #define	JMPHY_SCL_LEN_35		0
56 #define	JMPHY_SCL_LEN_40		1
57 #define	JMPHY_SCL_LEN_50		2
58 #define	JMPHY_SCL_LEN_60		3
59 #define	JMPHY_SCL_LEN_70		4
60 #define	JMPHY_SCL_LEN_80		5
61 #define	JMPHY_SCL_LEN_90		6
62 #define	JMPHY_SCL_LEN_100		7
63 #define	JMPHY_SCL_LEN_110		8
64 #define	JMPHY_SCL_LEN_120		9
65 #define	JMPHY_SCL_LEN_130		10
66 #define	JMPHY_SCL_LEN_140		11
67 #define	JMPHY_SCL_LEN_150		12
68 #define	JMPHY_SCL_LEN_160		13
69 #define	JMPHY_SCL_LEN_170		14
70 #define	JMPHY_SCL_RSVD			15
71 
72 /* PHY specific LED control register 1. */
73 #define	JMPHY_LED_CTL1			0x18
74 #define	JMPHY_LED_BLINK_42MS		0x0000
75 #define	JMPHY_LED_BLINK_84MS		0x2000
76 #define	JMPHY_LED_BLINK_170MS		0x4000
77 #define	JMPHY_LED_BLINK_340MS		0x6000
78 #define	JMPHY_LED_BLINK_670MS		0x8000
79 #define	JMPHY_LED_BLINK_MASK		0xE000
80 #define	JMPHY_LED_FLP_GAP_MASK		0x1F00
81 #define	JMPHY_LED_FLP_GAP_DEFULT	0x1000
82 #define	JMPHY_LED2_POLARITY_MASK	0x0030
83 #define	JMPHY_LED1_POLARITY_MASK	0x000C
84 #define	JMPHY_LED0_POLARITY_MASK	0x0003
85 #define	JMPHY_LED_ON_LO_OFF_HI		0
86 #define	JMPHY_LED_ON_HI_OFF_HI		1
87 #define	JMPHY_LED_ON_LO_OFF_TS		2
88 #define	JMPHY_LED_ON_HI_OFF_TS		3
89 
90 /* PHY specific LED control register 2. */
91 #define	JMPHY_LED_CTL2			0x19
92 #define	JMPHY_LED_NO_STRETCH		0x0000
93 #define	JMPHY_LED_STRETCH_42MS		0x2000
94 #define	JMPHY_LED_STRETCH_84MS		0x4000
95 #define	JMPHY_LED_STRETCH_170MS		0x6000
96 #define	JMPHY_LED_STRETCH_340MS		0x8000
97 #define	JMPHY_LED_STRETCH_670MS		0xB000
98 #define	JMPHY_LED_STRETCH_1300MS	0xC000
99 #define	JMPHY_LED_STRETCH_2700MS	0xE000
100 #define	JMPHY_LED2_MODE_MASK		0x0F00
101 #define	JMPHY_LED1_MODE_MASK		0x00F0
102 #define	JMPHY_LED0_MODE_MASK		0x000F
103 
104 /* PHY specific test mode control register. */
105 #define	JMPHY_TMCTL			0x1A
106 #define	JMPHY_TMCTL_SLEEP_ENB		0x1000
107 
108 /* PHY specific configuration register. */
109 #define	JMPHY_SPEC_ADDR			0x1E
110 #define	JMPHY_SPEC_ADDR_READ		0x4000
111 #define	JMPHY_SPEC_ADDR_WRITE		0x8000
112 
113 #define	JMPHY_SPEC_DATA			0x1F
114 
115 #define	JMPHY_EXT_COMM_2		0x32
116 
117 #endif	/* _DEV_MII_JMPHYREG_H_ */
118