1 /*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Cicada CS8201 10/100/1000 copper PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/ciphyreg.h> 56 57 #include "miibus_if.h" 58 59 #include <machine/bus.h> 60 /* 61 #include <dev/vge/if_vgereg.h> 62 */ 63 static int ciphy_probe(device_t); 64 static int ciphy_attach(device_t); 65 66 static device_method_t ciphy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, ciphy_probe), 69 DEVMETHOD(device_attach, ciphy_attach), 70 DEVMETHOD(device_detach, mii_phy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 { 0, 0 } 73 }; 74 75 static devclass_t ciphy_devclass; 76 77 static driver_t ciphy_driver = { 78 "ciphy", 79 ciphy_methods, 80 sizeof(struct mii_softc) 81 }; 82 83 DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0); 84 85 static int ciphy_service(struct mii_softc *, struct mii_data *, int); 86 static void ciphy_status(struct mii_softc *); 87 static void ciphy_reset(struct mii_softc *); 88 static void ciphy_fixup(struct mii_softc *); 89 90 static const struct mii_phydesc ciphys[] = { 91 MII_PHY_DESC(CICADA, CS8201), 92 MII_PHY_DESC(CICADA, CS8201A), 93 MII_PHY_DESC(CICADA, CS8201B), 94 MII_PHY_DESC(VITESSE, VSC8601), 95 MII_PHY_END 96 }; 97 98 static int 99 ciphy_probe(device_t dev) 100 { 101 102 return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT)); 103 } 104 105 static int 106 ciphy_attach(device_t dev) 107 { 108 struct mii_softc *sc; 109 struct mii_attach_args *ma; 110 struct mii_data *mii; 111 112 sc = device_get_softc(dev); 113 ma = device_get_ivars(dev); 114 sc->mii_dev = device_get_parent(dev); 115 mii = device_get_softc(sc->mii_dev); 116 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 117 118 sc->mii_inst = mii->mii_instance; 119 sc->mii_phy = ma->mii_phyno; 120 sc->mii_service = ciphy_service; 121 sc->mii_pdata = mii; 122 123 sc->mii_flags |= MIIF_NOISOLATE; 124 mii->mii_instance++; 125 126 ciphy_reset(sc); 127 128 sc->mii_capabilities = 129 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 130 if (sc->mii_capabilities & BMSR_EXTSTAT) 131 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 132 device_printf(dev, " "); 133 mii_phy_add_media(sc); 134 printf("\n"); 135 136 MIIBUS_MEDIAINIT(sc->mii_dev); 137 return (0); 138 } 139 140 static int 141 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 142 { 143 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 144 int reg, speed, gig; 145 146 switch (cmd) { 147 case MII_POLLSTAT: 148 /* 149 * If we're not polling our PHY instance, just return. 150 */ 151 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 152 return (0); 153 break; 154 155 case MII_MEDIACHG: 156 /* 157 * If the media indicates a different PHY instance, 158 * isolate ourselves. 159 */ 160 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 161 reg = PHY_READ(sc, MII_BMCR); 162 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 163 return (0); 164 } 165 166 /* 167 * If the interface is not up, don't do anything. 168 */ 169 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 170 break; 171 172 ciphy_fixup(sc); /* XXX hardware bug work-around */ 173 174 switch (IFM_SUBTYPE(ife->ifm_media)) { 175 case IFM_AUTO: 176 #ifdef foo 177 /* 178 * If we're already in auto mode, just return. 179 */ 180 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN) 181 return (0); 182 #endif 183 (void) mii_phy_auto(sc); 184 break; 185 case IFM_1000_T: 186 speed = CIPHY_S1000; 187 goto setit; 188 case IFM_100_TX: 189 speed = CIPHY_S100; 190 goto setit; 191 case IFM_10_T: 192 speed = CIPHY_S10; 193 setit: 194 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 195 speed |= CIPHY_BMCR_FDX; 196 gig = CIPHY_1000CTL_AFD; 197 } else { 198 gig = CIPHY_1000CTL_AHD; 199 } 200 201 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0); 202 PHY_WRITE(sc, CIPHY_MII_BMCR, speed); 203 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE); 204 205 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 206 break; 207 208 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig); 209 PHY_WRITE(sc, CIPHY_MII_BMCR, 210 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG); 211 212 /* 213 * When setting the link manually, one side must 214 * be the master and the other the slave. However 215 * ifmedia doesn't give us a good way to specify 216 * this, so we fake it by using one of the LINK 217 * flags. If LINK0 is set, we program the PHY to 218 * be a master, otherwise it's a slave. 219 */ 220 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 221 PHY_WRITE(sc, CIPHY_MII_1000CTL, 222 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC); 223 } else { 224 PHY_WRITE(sc, CIPHY_MII_1000CTL, 225 gig|CIPHY_1000CTL_MSE); 226 } 227 break; 228 case IFM_NONE: 229 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 230 break; 231 case IFM_100_T4: 232 default: 233 return (EINVAL); 234 } 235 break; 236 237 case MII_TICK: 238 /* 239 * If we're not currently selected, just return. 240 */ 241 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 242 return (0); 243 244 /* 245 * Is the interface even up? 246 */ 247 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 248 return (0); 249 250 /* 251 * Only used for autonegotiation. 252 */ 253 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 254 break; 255 256 /* 257 * Check to see if we have link. If we do, we don't 258 * need to restart the autonegotiation process. Read 259 * the BMSR twice in case it's latched. 260 */ 261 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 262 if (reg & BMSR_LINK) 263 break; 264 265 /* 266 * Only retry autonegotiation every 5 seconds. 267 */ 268 if (++sc->mii_ticks <= MII_ANEGTICKS) 269 break; 270 271 sc->mii_ticks = 0; 272 mii_phy_auto(sc); 273 return (0); 274 } 275 276 /* Update the media status. */ 277 ciphy_status(sc); 278 279 /* 280 * Callback if something changed. Note that we need to poke 281 * apply fixups for certain PHY revs. 282 */ 283 if (sc->mii_media_active != mii->mii_media_active || 284 sc->mii_media_status != mii->mii_media_status || 285 cmd == MII_MEDIACHG) { 286 ciphy_fixup(sc); 287 } 288 mii_phy_update(sc, cmd); 289 return (0); 290 } 291 292 static void 293 ciphy_status(struct mii_softc *sc) 294 { 295 struct mii_data *mii = sc->mii_pdata; 296 int bmsr, bmcr; 297 298 mii->mii_media_status = IFM_AVALID; 299 mii->mii_media_active = IFM_ETHER; 300 301 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 302 303 if (bmsr & BMSR_LINK) 304 mii->mii_media_status |= IFM_ACTIVE; 305 306 bmcr = PHY_READ(sc, CIPHY_MII_BMCR); 307 308 if (bmcr & CIPHY_BMCR_LOOP) 309 mii->mii_media_active |= IFM_LOOP; 310 311 if (bmcr & CIPHY_BMCR_AUTOEN) { 312 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) { 313 /* Erg, still trying, I guess... */ 314 mii->mii_media_active |= IFM_NONE; 315 return; 316 } 317 } 318 319 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR); 320 switch (bmsr & CIPHY_AUXCSR_SPEED) { 321 case CIPHY_SPEED10: 322 mii->mii_media_active |= IFM_10_T; 323 break; 324 case CIPHY_SPEED100: 325 mii->mii_media_active |= IFM_100_TX; 326 break; 327 case CIPHY_SPEED1000: 328 mii->mii_media_active |= IFM_1000_T; 329 break; 330 default: 331 device_printf(sc->mii_dev, "unknown PHY speed %x\n", 332 bmsr & CIPHY_AUXCSR_SPEED); 333 break; 334 } 335 336 if (bmsr & CIPHY_AUXCSR_FDX) 337 mii->mii_media_active |= IFM_FDX; 338 } 339 340 static void 341 ciphy_reset(struct mii_softc *sc) 342 { 343 344 mii_phy_reset(sc); 345 DELAY(1000); 346 } 347 348 #define PHY_SETBIT(x, y, z) \ 349 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 350 #define PHY_CLRBIT(x, y, z) \ 351 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 352 353 static void 354 ciphy_fixup(struct mii_softc *sc) 355 { 356 uint16_t model; 357 uint16_t status, speed; 358 uint16_t val; 359 360 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2)); 361 status = PHY_READ(sc, CIPHY_MII_AUXCSR); 362 speed = status & CIPHY_AUXCSR_SPEED; 363 364 if (strcmp(device_get_name(device_get_parent(sc->mii_dev)), 365 "nfe") == 0) { 366 /* need to set for 2.5V RGMII for NVIDIA adapters */ 367 val = PHY_READ(sc, CIPHY_MII_ECTL1); 368 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL); 369 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII); 370 PHY_WRITE(sc, CIPHY_MII_ECTL1, val); 371 /* From Linux. */ 372 val = PHY_READ(sc, CIPHY_MII_AUXCSR); 373 val |= CIPHY_AUXCSR_MDPPS; 374 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val); 375 val = PHY_READ(sc, CIPHY_MII_10BTCSR); 376 val |= CIPHY_10BTCSR_ECHO; 377 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val); 378 } 379 380 switch (model) { 381 case MII_MODEL_CICADA_CS8201: 382 383 /* Turn off "aux mode" (whatever that means) */ 384 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); 385 386 /* 387 * Work around speed polling bug in VT3119/VT3216 388 * when using MII in full duplex mode. 389 */ 390 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 391 (status & CIPHY_AUXCSR_FDX)) { 392 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 393 } else { 394 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 395 } 396 397 /* Enable link/activity LED blink. */ 398 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); 399 400 break; 401 402 case MII_MODEL_CICADA_CS8201A: 403 case MII_MODEL_CICADA_CS8201B: 404 405 /* 406 * Work around speed polling bug in VT3119/VT3216 407 * when using MII in full duplex mode. 408 */ 409 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 410 (status & CIPHY_AUXCSR_FDX)) { 411 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 412 } else { 413 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 414 } 415 416 break; 417 case MII_MODEL_VITESSE_VSC8601: 418 break; 419 default: 420 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n", 421 model); 422 break; 423 } 424 } 425