1 /*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Cicada CS8201/CS8204 10/100/1000 copper PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_arp.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/ciphyreg.h> 56 57 #include "miibus_if.h" 58 59 #include <machine/bus.h> 60 /* 61 #include <dev/vge/if_vgereg.h> 62 */ 63 static int ciphy_probe(device_t); 64 static int ciphy_attach(device_t); 65 66 static device_method_t ciphy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, ciphy_probe), 69 DEVMETHOD(device_attach, ciphy_attach), 70 DEVMETHOD(device_detach, mii_phy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 { 0, 0 } 73 }; 74 75 static devclass_t ciphy_devclass; 76 77 static driver_t ciphy_driver = { 78 "ciphy", 79 ciphy_methods, 80 sizeof(struct mii_softc) 81 }; 82 83 DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0); 84 85 static int ciphy_service(struct mii_softc *, struct mii_data *, int); 86 static void ciphy_status(struct mii_softc *); 87 static void ciphy_reset(struct mii_softc *); 88 static void ciphy_fixup(struct mii_softc *); 89 90 static const struct mii_phydesc ciphys[] = { 91 MII_PHY_DESC(CICADA, CS8201), 92 MII_PHY_DESC(CICADA, CS8201A), 93 MII_PHY_DESC(CICADA, CS8201B), 94 MII_PHY_DESC(CICADA, CS8204), 95 MII_PHY_DESC(VITESSE, VSC8601), 96 MII_PHY_END 97 }; 98 99 static int 100 ciphy_probe(device_t dev) 101 { 102 103 return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT)); 104 } 105 106 static int 107 ciphy_attach(device_t dev) 108 { 109 struct mii_softc *sc; 110 struct mii_attach_args *ma; 111 struct mii_data *mii; 112 113 sc = device_get_softc(dev); 114 ma = device_get_ivars(dev); 115 sc->mii_dev = device_get_parent(dev); 116 mii = device_get_softc(sc->mii_dev); 117 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 118 119 sc->mii_inst = mii->mii_instance; 120 sc->mii_phy = ma->mii_phyno; 121 sc->mii_service = ciphy_service; 122 sc->mii_pdata = mii; 123 124 sc->mii_flags |= MIIF_NOISOLATE; 125 mii->mii_instance++; 126 127 ciphy_reset(sc); 128 129 sc->mii_capabilities = 130 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 131 if (sc->mii_capabilities & BMSR_EXTSTAT) 132 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 133 device_printf(dev, " "); 134 mii_phy_add_media(sc); 135 printf("\n"); 136 137 MIIBUS_MEDIAINIT(sc->mii_dev); 138 return (0); 139 } 140 141 static int 142 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 143 { 144 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 145 int reg, speed, gig; 146 147 switch (cmd) { 148 case MII_POLLSTAT: 149 /* 150 * If we're not polling our PHY instance, just return. 151 */ 152 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 153 return (0); 154 break; 155 156 case MII_MEDIACHG: 157 /* 158 * If the media indicates a different PHY instance, 159 * isolate ourselves. 160 */ 161 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 162 reg = PHY_READ(sc, MII_BMCR); 163 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 164 return (0); 165 } 166 167 /* 168 * If the interface is not up, don't do anything. 169 */ 170 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 171 break; 172 173 ciphy_fixup(sc); /* XXX hardware bug work-around */ 174 175 switch (IFM_SUBTYPE(ife->ifm_media)) { 176 case IFM_AUTO: 177 #ifdef foo 178 /* 179 * If we're already in auto mode, just return. 180 */ 181 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN) 182 return (0); 183 #endif 184 (void) mii_phy_auto(sc); 185 break; 186 case IFM_1000_T: 187 speed = CIPHY_S1000; 188 goto setit; 189 case IFM_100_TX: 190 speed = CIPHY_S100; 191 goto setit; 192 case IFM_10_T: 193 speed = CIPHY_S10; 194 setit: 195 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 196 speed |= CIPHY_BMCR_FDX; 197 gig = CIPHY_1000CTL_AFD; 198 } else { 199 gig = CIPHY_1000CTL_AHD; 200 } 201 202 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0); 203 PHY_WRITE(sc, CIPHY_MII_BMCR, speed); 204 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE); 205 206 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 207 break; 208 209 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig); 210 PHY_WRITE(sc, CIPHY_MII_BMCR, 211 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG); 212 213 /* 214 * When setting the link manually, one side must 215 * be the master and the other the slave. However 216 * ifmedia doesn't give us a good way to specify 217 * this, so we fake it by using one of the LINK 218 * flags. If LINK0 is set, we program the PHY to 219 * be a master, otherwise it's a slave. 220 */ 221 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 222 PHY_WRITE(sc, CIPHY_MII_1000CTL, 223 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC); 224 } else { 225 PHY_WRITE(sc, CIPHY_MII_1000CTL, 226 gig|CIPHY_1000CTL_MSE); 227 } 228 break; 229 case IFM_NONE: 230 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 231 break; 232 case IFM_100_T4: 233 default: 234 return (EINVAL); 235 } 236 break; 237 238 case MII_TICK: 239 /* 240 * If we're not currently selected, just return. 241 */ 242 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 243 return (0); 244 245 /* 246 * Is the interface even up? 247 */ 248 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 249 return (0); 250 251 /* 252 * Only used for autonegotiation. 253 */ 254 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 255 break; 256 257 /* 258 * Check to see if we have link. If we do, we don't 259 * need to restart the autonegotiation process. Read 260 * the BMSR twice in case it's latched. 261 */ 262 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 263 if (reg & BMSR_LINK) 264 break; 265 266 /* 267 * Only retry autonegotiation every 5 seconds. 268 */ 269 if (++sc->mii_ticks <= MII_ANEGTICKS) 270 break; 271 272 sc->mii_ticks = 0; 273 mii_phy_auto(sc); 274 return (0); 275 } 276 277 /* Update the media status. */ 278 ciphy_status(sc); 279 280 /* 281 * Callback if something changed. Note that we need to poke 282 * apply fixups for certain PHY revs. 283 */ 284 if (sc->mii_media_active != mii->mii_media_active || 285 sc->mii_media_status != mii->mii_media_status || 286 cmd == MII_MEDIACHG) { 287 ciphy_fixup(sc); 288 } 289 mii_phy_update(sc, cmd); 290 return (0); 291 } 292 293 static void 294 ciphy_status(struct mii_softc *sc) 295 { 296 struct mii_data *mii = sc->mii_pdata; 297 int bmsr, bmcr; 298 299 mii->mii_media_status = IFM_AVALID; 300 mii->mii_media_active = IFM_ETHER; 301 302 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 303 304 if (bmsr & BMSR_LINK) 305 mii->mii_media_status |= IFM_ACTIVE; 306 307 bmcr = PHY_READ(sc, CIPHY_MII_BMCR); 308 309 if (bmcr & CIPHY_BMCR_LOOP) 310 mii->mii_media_active |= IFM_LOOP; 311 312 if (bmcr & CIPHY_BMCR_AUTOEN) { 313 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) { 314 /* Erg, still trying, I guess... */ 315 mii->mii_media_active |= IFM_NONE; 316 return; 317 } 318 } 319 320 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR); 321 switch (bmsr & CIPHY_AUXCSR_SPEED) { 322 case CIPHY_SPEED10: 323 mii->mii_media_active |= IFM_10_T; 324 break; 325 case CIPHY_SPEED100: 326 mii->mii_media_active |= IFM_100_TX; 327 break; 328 case CIPHY_SPEED1000: 329 mii->mii_media_active |= IFM_1000_T; 330 break; 331 default: 332 device_printf(sc->mii_dev, "unknown PHY speed %x\n", 333 bmsr & CIPHY_AUXCSR_SPEED); 334 break; 335 } 336 337 if (bmsr & CIPHY_AUXCSR_FDX) 338 mii->mii_media_active |= IFM_FDX; 339 } 340 341 static void 342 ciphy_reset(struct mii_softc *sc) 343 { 344 345 mii_phy_reset(sc); 346 DELAY(1000); 347 } 348 349 #define PHY_SETBIT(x, y, z) \ 350 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 351 #define PHY_CLRBIT(x, y, z) \ 352 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 353 354 static void 355 ciphy_fixup(struct mii_softc *sc) 356 { 357 uint16_t model; 358 uint16_t status, speed; 359 uint16_t val; 360 361 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2)); 362 status = PHY_READ(sc, CIPHY_MII_AUXCSR); 363 speed = status & CIPHY_AUXCSR_SPEED; 364 365 if (strcmp(device_get_name(device_get_parent(sc->mii_dev)), 366 "nfe") == 0) { 367 /* need to set for 2.5V RGMII for NVIDIA adapters */ 368 val = PHY_READ(sc, CIPHY_MII_ECTL1); 369 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL); 370 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII); 371 PHY_WRITE(sc, CIPHY_MII_ECTL1, val); 372 /* From Linux. */ 373 val = PHY_READ(sc, CIPHY_MII_AUXCSR); 374 val |= CIPHY_AUXCSR_MDPPS; 375 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val); 376 val = PHY_READ(sc, CIPHY_MII_10BTCSR); 377 val |= CIPHY_10BTCSR_ECHO; 378 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val); 379 } 380 381 switch (model) { 382 case MII_MODEL_CICADA_CS8204: 383 case MII_MODEL_CICADA_CS8201: 384 385 /* Turn off "aux mode" (whatever that means) */ 386 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); 387 388 /* 389 * Work around speed polling bug in VT3119/VT3216 390 * when using MII in full duplex mode. 391 */ 392 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 393 (status & CIPHY_AUXCSR_FDX)) { 394 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 395 } else { 396 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 397 } 398 399 /* Enable link/activity LED blink. */ 400 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); 401 402 break; 403 404 case MII_MODEL_CICADA_CS8201A: 405 case MII_MODEL_CICADA_CS8201B: 406 407 /* 408 * Work around speed polling bug in VT3119/VT3216 409 * when using MII in full duplex mode. 410 */ 411 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 412 (status & CIPHY_AUXCSR_FDX)) { 413 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 414 } else { 415 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 416 } 417 418 break; 419 case MII_MODEL_VITESSE_VSC8601: 420 break; 421 default: 422 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n", 423 model); 424 break; 425 } 426 } 427