xref: /freebsd/sys/dev/mii/ciphy.c (revision 3fcb7a5365f9de7824a2b5f8e8ab159c8d3d79a0)
1098ca2bdSWarner Losh /*-
2a07bd003SBill Paul  * Copyright (c) 2004
3a07bd003SBill Paul  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
4a07bd003SBill Paul  *
5a07bd003SBill Paul  * Redistribution and use in source and binary forms, with or without
6a07bd003SBill Paul  * modification, are permitted provided that the following conditions
7a07bd003SBill Paul  * are met:
8a07bd003SBill Paul  * 1. Redistributions of source code must retain the above copyright
9a07bd003SBill Paul  *    notice, this list of conditions and the following disclaimer.
10a07bd003SBill Paul  * 2. Redistributions in binary form must reproduce the above copyright
11a07bd003SBill Paul  *    notice, this list of conditions and the following disclaimer in the
12a07bd003SBill Paul  *    documentation and/or other materials provided with the distribution.
13a07bd003SBill Paul  * 3. All advertising materials mentioning features or use of this software
14a07bd003SBill Paul  *    must display the following acknowledgement:
15a07bd003SBill Paul  *	This product includes software developed by Bill Paul.
16a07bd003SBill Paul  * 4. Neither the name of the author nor the names of any co-contributors
17a07bd003SBill Paul  *    may be used to endorse or promote products derived from this software
18a07bd003SBill Paul  *    without specific prior written permission.
19a07bd003SBill Paul  *
20a07bd003SBill Paul  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21a07bd003SBill Paul  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a07bd003SBill Paul  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23a07bd003SBill Paul  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24a07bd003SBill Paul  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25a07bd003SBill Paul  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26a07bd003SBill Paul  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27a07bd003SBill Paul  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28a07bd003SBill Paul  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29a07bd003SBill Paul  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30a07bd003SBill Paul  * THE POSSIBILITY OF SUCH DAMAGE.
31a07bd003SBill Paul  */
32a07bd003SBill Paul 
33a07bd003SBill Paul #include <sys/cdefs.h>
34a07bd003SBill Paul __FBSDID("$FreeBSD$");
35a07bd003SBill Paul 
36a07bd003SBill Paul /*
37324eb733SRafal Jaworowski  * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
38a07bd003SBill Paul  */
39a07bd003SBill Paul 
40a07bd003SBill Paul #include <sys/param.h>
41a07bd003SBill Paul #include <sys/systm.h>
42a07bd003SBill Paul #include <sys/kernel.h>
43a07bd003SBill Paul #include <sys/module.h>
44a07bd003SBill Paul #include <sys/socket.h>
45a07bd003SBill Paul #include <sys/bus.h>
46a07bd003SBill Paul 
47a07bd003SBill Paul #include <net/if.h>
48a07bd003SBill Paul #include <net/if_arp.h>
49a07bd003SBill Paul #include <net/if_media.h>
50a07bd003SBill Paul 
51a07bd003SBill Paul #include <dev/mii/mii.h>
52a07bd003SBill Paul #include <dev/mii/miivar.h>
53a07bd003SBill Paul #include "miidevs.h"
54a07bd003SBill Paul 
55a07bd003SBill Paul #include <dev/mii/ciphyreg.h>
56a07bd003SBill Paul 
57a07bd003SBill Paul #include "miibus_if.h"
58a07bd003SBill Paul 
59a07bd003SBill Paul #include <machine/bus.h>
608e5d93dbSMarius Strobl 
61a07bd003SBill Paul static int ciphy_probe(device_t);
62a07bd003SBill Paul static int ciphy_attach(device_t);
63a07bd003SBill Paul 
64a07bd003SBill Paul static device_method_t ciphy_methods[] = {
65a07bd003SBill Paul 	/* device interface */
66a07bd003SBill Paul 	DEVMETHOD(device_probe,		ciphy_probe),
67a07bd003SBill Paul 	DEVMETHOD(device_attach,	ciphy_attach),
68a07bd003SBill Paul 	DEVMETHOD(device_detach,	mii_phy_detach),
69a07bd003SBill Paul 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
70a07bd003SBill Paul 	{ 0, 0 }
71a07bd003SBill Paul };
72a07bd003SBill Paul 
73a07bd003SBill Paul static devclass_t ciphy_devclass;
74a07bd003SBill Paul 
75a07bd003SBill Paul static driver_t ciphy_driver = {
76a07bd003SBill Paul 	"ciphy",
77a07bd003SBill Paul 	ciphy_methods,
78a07bd003SBill Paul 	sizeof(struct mii_softc)
79a07bd003SBill Paul };
80a07bd003SBill Paul 
81a07bd003SBill Paul DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
82a07bd003SBill Paul 
83a07bd003SBill Paul static int	ciphy_service(struct mii_softc *, struct mii_data *, int);
84a07bd003SBill Paul static void	ciphy_status(struct mii_softc *);
85a07bd003SBill Paul static void	ciphy_reset(struct mii_softc *);
86a07bd003SBill Paul static void	ciphy_fixup(struct mii_softc *);
87a07bd003SBill Paul 
88a35b9333SMarius Strobl static const struct mii_phydesc ciphys[] = {
89*3fcb7a53SMarius Strobl 	MII_PHY_DESC(xxCICADA, CS8201),
90*3fcb7a53SMarius Strobl 	MII_PHY_DESC(xxCICADA, CS8201A),
91*3fcb7a53SMarius Strobl 	MII_PHY_DESC(xxCICADA, CS8201B),
92*3fcb7a53SMarius Strobl 	MII_PHY_DESC(xxCICADA, CS8204),
93*3fcb7a53SMarius Strobl 	MII_PHY_DESC(xxCICADA, VSC8211),
94*3fcb7a53SMarius Strobl 	MII_PHY_DESC(xxCICADA, CS8244),
95*3fcb7a53SMarius Strobl 	MII_PHY_DESC(xxVITESSE, VSC8601),
96a35b9333SMarius Strobl 	MII_PHY_END
97a35b9333SMarius Strobl };
98a35b9333SMarius Strobl 
99*3fcb7a53SMarius Strobl static const struct mii_phy_funcs ciphy_funcs = {
100*3fcb7a53SMarius Strobl 	ciphy_service,
101*3fcb7a53SMarius Strobl 	ciphy_status,
102*3fcb7a53SMarius Strobl 	ciphy_reset
103*3fcb7a53SMarius Strobl };
104*3fcb7a53SMarius Strobl 
105a07bd003SBill Paul static int
1067d830ac9SWarner Losh ciphy_probe(device_t dev)
107a07bd003SBill Paul {
108a07bd003SBill Paul 
109a35b9333SMarius Strobl 	return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
110a07bd003SBill Paul }
111a07bd003SBill Paul 
112a07bd003SBill Paul static int
1137d830ac9SWarner Losh ciphy_attach(device_t dev)
114a07bd003SBill Paul {
115a07bd003SBill Paul 
116*3fcb7a53SMarius Strobl 	mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
117*3fcb7a53SMarius Strobl 	    &ciphy_funcs, 1);
118a07bd003SBill Paul 	return (0);
119a07bd003SBill Paul }
120a07bd003SBill Paul 
121a07bd003SBill Paul static int
1227d830ac9SWarner Losh ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
123a07bd003SBill Paul {
124a07bd003SBill Paul 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
125a07bd003SBill Paul 	int reg, speed, gig;
126a07bd003SBill Paul 
127a07bd003SBill Paul 	switch (cmd) {
128a07bd003SBill Paul 	case MII_POLLSTAT:
129a07bd003SBill Paul 		break;
130a07bd003SBill Paul 
131a07bd003SBill Paul 	case MII_MEDIACHG:
132a07bd003SBill Paul 		/*
133a07bd003SBill Paul 		 * If the interface is not up, don't do anything.
134a07bd003SBill Paul 		 */
135a07bd003SBill Paul 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
136a07bd003SBill Paul 			break;
137a07bd003SBill Paul 
138a07bd003SBill Paul 		ciphy_fixup(sc);	/* XXX hardware bug work-around */
139a07bd003SBill Paul 
140a07bd003SBill Paul 		switch (IFM_SUBTYPE(ife->ifm_media)) {
141a07bd003SBill Paul 		case IFM_AUTO:
142a07bd003SBill Paul #ifdef foo
143a07bd003SBill Paul 			/*
144a07bd003SBill Paul 			 * If we're already in auto mode, just return.
145a07bd003SBill Paul 			 */
146a07bd003SBill Paul 			if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
147a07bd003SBill Paul 				return (0);
148a07bd003SBill Paul #endif
149a07bd003SBill Paul 			(void)mii_phy_auto(sc);
150a07bd003SBill Paul 			break;
151a07bd003SBill Paul 		case IFM_1000_T:
152a07bd003SBill Paul 			speed = CIPHY_S1000;
153a07bd003SBill Paul 			goto setit;
154a07bd003SBill Paul 		case IFM_100_TX:
155a07bd003SBill Paul 			speed = CIPHY_S100;
156a07bd003SBill Paul 			goto setit;
157a07bd003SBill Paul 		case IFM_10_T:
158a07bd003SBill Paul 			speed = CIPHY_S10;
159a07bd003SBill Paul setit:
16087a303dcSMarius Strobl 			if ((ife->ifm_media & IFM_FDX) != 0) {
161a07bd003SBill Paul 				speed |= CIPHY_BMCR_FDX;
162a07bd003SBill Paul 				gig = CIPHY_1000CTL_AFD;
16387a303dcSMarius Strobl 			} else
164a07bd003SBill Paul 				gig = CIPHY_1000CTL_AHD;
165a07bd003SBill Paul 
16687a303dcSMarius Strobl 			if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
167efd4fc3fSMarius Strobl 				gig |= CIPHY_1000CTL_MSE;
168efd4fc3fSMarius Strobl 				if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
169efd4fc3fSMarius Strobl 					gig |= CIPHY_1000CTL_MSC;
17087a303dcSMarius Strobl 				speed |=
17187a303dcSMarius Strobl 				    CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG;
17287a303dcSMarius Strobl 			} else
17387a303dcSMarius Strobl 				gig = 0;
174a07bd003SBill Paul 			PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
17587a303dcSMarius Strobl 			PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
17687a303dcSMarius Strobl 			PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
177a07bd003SBill Paul 			break;
178a07bd003SBill Paul 		case IFM_NONE:
179a07bd003SBill Paul 			PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
180a07bd003SBill Paul 			break;
181a07bd003SBill Paul 		default:
182a07bd003SBill Paul 			return (EINVAL);
183a07bd003SBill Paul 		}
184a07bd003SBill Paul 		break;
185a07bd003SBill Paul 
186a07bd003SBill Paul 	case MII_TICK:
187a07bd003SBill Paul 		/*
188a07bd003SBill Paul 		 * Is the interface even up?
189a07bd003SBill Paul 		 */
190a07bd003SBill Paul 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
191a07bd003SBill Paul 			return (0);
192a07bd003SBill Paul 
193a07bd003SBill Paul 		/*
194a07bd003SBill Paul 		 * Only used for autonegotiation.
195a07bd003SBill Paul 		 */
196a07bd003SBill Paul 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
197a07bd003SBill Paul 			break;
198a07bd003SBill Paul 
199a07bd003SBill Paul 		/*
200a07bd003SBill Paul 		 * Check to see if we have link.  If we do, we don't
201a07bd003SBill Paul 		 * need to restart the autonegotiation process.  Read
202a07bd003SBill Paul 		 * the BMSR twice in case it's latched.
203a07bd003SBill Paul 		 */
204a07bd003SBill Paul 		reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
205a07bd003SBill Paul 		if (reg & BMSR_LINK)
206a07bd003SBill Paul 			break;
207a07bd003SBill Paul 
208138b38ffSPyun YongHyeon 		/* Announce link loss right after it happens. */
209138b38ffSPyun YongHyeon 		if (++sc->mii_ticks == 0)
210138b38ffSPyun YongHyeon 			break;
211a07bd003SBill Paul 		/*
212eb10e723SPyun YongHyeon 		 * Only retry autonegotiation every mii_anegticks seconds.
213a07bd003SBill Paul 		 */
214eb10e723SPyun YongHyeon 		if (sc->mii_ticks <= sc->mii_anegticks)
215a07bd003SBill Paul 			break;
216a07bd003SBill Paul 
217a07bd003SBill Paul 		sc->mii_ticks = 0;
218a07bd003SBill Paul 		mii_phy_auto(sc);
21993798224SPyun YongHyeon 		break;
220a07bd003SBill Paul 	}
221a07bd003SBill Paul 
222a07bd003SBill Paul 	/* Update the media status. */
223*3fcb7a53SMarius Strobl 	PHY_STATUS(sc);
224a07bd003SBill Paul 
225a07bd003SBill Paul 	/*
226a07bd003SBill Paul 	 * Callback if something changed. Note that we need to poke
227a07bd003SBill Paul 	 * apply fixups for certain PHY revs.
228a07bd003SBill Paul 	 */
229a07bd003SBill Paul 	if (sc->mii_media_active != mii->mii_media_active ||
230a07bd003SBill Paul 	    sc->mii_media_status != mii->mii_media_status ||
231a07bd003SBill Paul 	    cmd == MII_MEDIACHG) {
232a07bd003SBill Paul 		ciphy_fixup(sc);
233a07bd003SBill Paul 	}
234a07bd003SBill Paul 	mii_phy_update(sc, cmd);
235a07bd003SBill Paul 	return (0);
236a07bd003SBill Paul }
237a07bd003SBill Paul 
238a07bd003SBill Paul static void
2397d830ac9SWarner Losh ciphy_status(struct mii_softc *sc)
240a07bd003SBill Paul {
241a07bd003SBill Paul 	struct mii_data *mii = sc->mii_pdata;
242a07bd003SBill Paul 	int bmsr, bmcr;
243a07bd003SBill Paul 
244a07bd003SBill Paul 	mii->mii_media_status = IFM_AVALID;
245a07bd003SBill Paul 	mii->mii_media_active = IFM_ETHER;
246a07bd003SBill Paul 
247a07bd003SBill Paul 	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
248a07bd003SBill Paul 
249a07bd003SBill Paul 	if (bmsr & BMSR_LINK)
250a07bd003SBill Paul 		mii->mii_media_status |= IFM_ACTIVE;
251a07bd003SBill Paul 
252a07bd003SBill Paul 	bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
253a07bd003SBill Paul 
254a07bd003SBill Paul 	if (bmcr & CIPHY_BMCR_LOOP)
255a07bd003SBill Paul 		mii->mii_media_active |= IFM_LOOP;
256a07bd003SBill Paul 
257a07bd003SBill Paul 	if (bmcr & CIPHY_BMCR_AUTOEN) {
258a07bd003SBill Paul 		if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
259a07bd003SBill Paul 			/* Erg, still trying, I guess... */
260a07bd003SBill Paul 			mii->mii_media_active |= IFM_NONE;
261a07bd003SBill Paul 			return;
262a07bd003SBill Paul 		}
263a07bd003SBill Paul 	}
264a07bd003SBill Paul 
265a07bd003SBill Paul 	bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
266a07bd003SBill Paul 	switch (bmsr & CIPHY_AUXCSR_SPEED) {
267a07bd003SBill Paul 	case CIPHY_SPEED10:
268a07bd003SBill Paul 		mii->mii_media_active |= IFM_10_T;
269a07bd003SBill Paul 		break;
270a07bd003SBill Paul 	case CIPHY_SPEED100:
271a07bd003SBill Paul 		mii->mii_media_active |= IFM_100_TX;
272a07bd003SBill Paul 		break;
273a07bd003SBill Paul 	case CIPHY_SPEED1000:
274a07bd003SBill Paul 		mii->mii_media_active |= IFM_1000_T;
275a07bd003SBill Paul 		break;
276a07bd003SBill Paul 	default:
277a07bd003SBill Paul 		device_printf(sc->mii_dev, "unknown PHY speed %x\n",
278a07bd003SBill Paul 		    bmsr & CIPHY_AUXCSR_SPEED);
279a07bd003SBill Paul 		break;
280a07bd003SBill Paul 	}
281a07bd003SBill Paul 
282a07bd003SBill Paul 	if (bmsr & CIPHY_AUXCSR_FDX)
283*3fcb7a53SMarius Strobl 		mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
284f350b4e7SPyun YongHyeon 	else
285f350b4e7SPyun YongHyeon 		mii->mii_media_active |= IFM_HDX;
286efd4fc3fSMarius Strobl 
287efd4fc3fSMarius Strobl 	if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
288efd4fc3fSMarius Strobl 	   (PHY_READ(sc, CIPHY_MII_1000STS) & CIPHY_1000STS_MSR) != 0)
289efd4fc3fSMarius Strobl 		mii->mii_media_active |= IFM_ETH_MASTER;
290a07bd003SBill Paul }
291a07bd003SBill Paul 
292a07bd003SBill Paul static void
293a07bd003SBill Paul ciphy_reset(struct mii_softc *sc)
294a07bd003SBill Paul {
295028ccec4SMarius Strobl 
296a07bd003SBill Paul 	mii_phy_reset(sc);
297a07bd003SBill Paul 	DELAY(1000);
298a07bd003SBill Paul }
299a07bd003SBill Paul 
300a07bd003SBill Paul #define PHY_SETBIT(x, y, z) \
301a07bd003SBill Paul 	PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
302a07bd003SBill Paul #define PHY_CLRBIT(x, y, z) \
303a07bd003SBill Paul 	PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
304a07bd003SBill Paul 
305a07bd003SBill Paul static void
306a07bd003SBill Paul ciphy_fixup(struct mii_softc *sc)
307a07bd003SBill Paul {
308a07bd003SBill Paul 	uint16_t		model;
309a07bd003SBill Paul 	uint16_t		status, speed;
3109f6cc3adSPyun YongHyeon 	uint16_t		val;
311a07bd003SBill Paul 
312a07bd003SBill Paul 	model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
313a07bd003SBill Paul 	status = PHY_READ(sc, CIPHY_MII_AUXCSR);
314a07bd003SBill Paul 	speed = status & CIPHY_AUXCSR_SPEED;
315a07bd003SBill Paul 
3169f6cc3adSPyun YongHyeon 	if (strcmp(device_get_name(device_get_parent(sc->mii_dev)),
3179f6cc3adSPyun YongHyeon 	    "nfe") == 0) {
3189f6cc3adSPyun YongHyeon 		/* need to set for 2.5V RGMII for NVIDIA adapters */
3199f6cc3adSPyun YongHyeon 		val = PHY_READ(sc, CIPHY_MII_ECTL1);
3209f6cc3adSPyun YongHyeon 		val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
3219f6cc3adSPyun YongHyeon 		val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
3229f6cc3adSPyun YongHyeon 		PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
3239f6cc3adSPyun YongHyeon 		/* From Linux. */
3249f6cc3adSPyun YongHyeon 		val = PHY_READ(sc, CIPHY_MII_AUXCSR);
3259f6cc3adSPyun YongHyeon 		val |= CIPHY_AUXCSR_MDPPS;
3269f6cc3adSPyun YongHyeon 		PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
3279f6cc3adSPyun YongHyeon 		val = PHY_READ(sc, CIPHY_MII_10BTCSR);
3289f6cc3adSPyun YongHyeon 		val |= CIPHY_10BTCSR_ECHO;
3299f6cc3adSPyun YongHyeon 		PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
3309f6cc3adSPyun YongHyeon 	}
3319f6cc3adSPyun YongHyeon 
332a07bd003SBill Paul 	switch (model) {
333*3fcb7a53SMarius Strobl 	case MII_MODEL_xxCICADA_CS8204:
334*3fcb7a53SMarius Strobl 	case MII_MODEL_xxCICADA_CS8201:
335a07bd003SBill Paul 
336a07bd003SBill Paul 		/* Turn off "aux mode" (whatever that means) */
337a07bd003SBill Paul 		PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
338a07bd003SBill Paul 
339a07bd003SBill Paul 		/*
340a07bd003SBill Paul 		 * Work around speed polling bug in VT3119/VT3216
341a07bd003SBill Paul 		 * when using MII in full duplex mode.
342a07bd003SBill Paul 		 */
343a07bd003SBill Paul 		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
344a07bd003SBill Paul 		    (status & CIPHY_AUXCSR_FDX)) {
345a07bd003SBill Paul 			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
346a07bd003SBill Paul 		} else {
347a07bd003SBill Paul 			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
348a07bd003SBill Paul 		}
349a07bd003SBill Paul 
350a07bd003SBill Paul 		/* Enable link/activity LED blink. */
351a07bd003SBill Paul 		PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
352a07bd003SBill Paul 
353a07bd003SBill Paul 		break;
354a07bd003SBill Paul 
355*3fcb7a53SMarius Strobl 	case MII_MODEL_xxCICADA_CS8201A:
356*3fcb7a53SMarius Strobl 	case MII_MODEL_xxCICADA_CS8201B:
357a07bd003SBill Paul 
358a07bd003SBill Paul 		/*
359a07bd003SBill Paul 		 * Work around speed polling bug in VT3119/VT3216
360a07bd003SBill Paul 		 * when using MII in full duplex mode.
361a07bd003SBill Paul 		 */
362a07bd003SBill Paul 		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
363a07bd003SBill Paul 		    (status & CIPHY_AUXCSR_FDX)) {
364a07bd003SBill Paul 			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
365a07bd003SBill Paul 		} else {
366a07bd003SBill Paul 			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
367a07bd003SBill Paul 		}
368a07bd003SBill Paul 
369a07bd003SBill Paul 		break;
370*3fcb7a53SMarius Strobl 	case MII_MODEL_xxCICADA_VSC8211:
371*3fcb7a53SMarius Strobl 	case MII_MODEL_xxCICADA_CS8244:
372*3fcb7a53SMarius Strobl 	case MII_MODEL_xxVITESSE_VSC8601:
3739f6cc3adSPyun YongHyeon 		break;
374a07bd003SBill Paul 	default:
375a07bd003SBill Paul 		device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
376a07bd003SBill Paul 		    model);
377a07bd003SBill Paul 		break;
378a07bd003SBill Paul 	}
379a07bd003SBill Paul }
380