1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/brgphyreg.h> 56 #include <net/if_arp.h> 57 #include <machine/bus.h> 58 #include <dev/bge/if_bgereg.h> 59 #include <dev/bce/if_bcereg.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 #include "miibus_if.h" 65 66 static int brgphy_probe(device_t); 67 static int brgphy_attach(device_t); 68 69 static device_method_t brgphy_methods[] = { 70 /* device interface */ 71 DEVMETHOD(device_probe, brgphy_probe), 72 DEVMETHOD(device_attach, brgphy_attach), 73 DEVMETHOD(device_detach, mii_phy_detach), 74 DEVMETHOD(device_shutdown, bus_generic_shutdown), 75 { 0, 0 } 76 }; 77 78 static devclass_t brgphy_devclass; 79 80 static driver_t brgphy_driver = { 81 "brgphy", 82 brgphy_methods, 83 sizeof(struct mii_softc) 84 }; 85 86 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 87 88 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 89 static void brgphy_setmedia(struct mii_softc *, int, int); 90 static void brgphy_status(struct mii_softc *); 91 static int brgphy_mii_phy_auto(struct mii_softc *); 92 static void brgphy_reset(struct mii_softc *); 93 static void brgphy_loop(struct mii_softc *); 94 static void bcm5401_load_dspcode(struct mii_softc *); 95 static void bcm5411_load_dspcode(struct mii_softc *); 96 static void bcm5703_load_dspcode(struct mii_softc *); 97 static void bcm5750_load_dspcode(struct mii_softc *); 98 static int brgphy_mii_model; 99 100 static const struct mii_phydesc brgphys[] = { 101 MII_PHY_DESC(xxBROADCOM, BCM5400), 102 MII_PHY_DESC(xxBROADCOM, BCM5401), 103 MII_PHY_DESC(xxBROADCOM, BCM5411), 104 MII_PHY_DESC(xxBROADCOM, BCM5701), 105 MII_PHY_DESC(xxBROADCOM, BCM5703), 106 MII_PHY_DESC(xxBROADCOM, BCM5704), 107 MII_PHY_DESC(xxBROADCOM, BCM5705), 108 MII_PHY_DESC(xxBROADCOM, BCM5706C), 109 MII_PHY_DESC(xxBROADCOM, BCM5708C), 110 MII_PHY_DESC(xxBROADCOM, BCM5714), 111 MII_PHY_DESC(xxBROADCOM, BCM5750), 112 MII_PHY_DESC(xxBROADCOM, BCM5752), 113 MII_PHY_DESC(xxBROADCOM, BCM5754), 114 MII_PHY_DESC(xxBROADCOM, BCM5780), 115 MII_PHY_END 116 }; 117 118 static int 119 brgphy_probe(device_t dev) 120 { 121 122 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 123 } 124 125 static int 126 brgphy_attach(device_t dev) 127 { 128 struct mii_softc *sc; 129 struct mii_attach_args *ma; 130 struct mii_data *mii; 131 const char *sep = ""; 132 struct bge_softc *bge_sc = NULL; 133 struct bce_softc *bce_sc = NULL; 134 int fast_ether_only = FALSE; 135 136 sc = device_get_softc(dev); 137 ma = device_get_ivars(dev); 138 sc->mii_dev = device_get_parent(dev); 139 mii = device_get_softc(sc->mii_dev); 140 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 141 142 sc->mii_inst = mii->mii_instance; 143 sc->mii_phy = ma->mii_phyno; 144 sc->mii_service = brgphy_service; 145 sc->mii_pdata = mii; 146 147 sc->mii_flags |= MIIF_NOISOLATE; 148 mii->mii_instance++; 149 150 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 151 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 152 153 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 154 BMCR_ISO); 155 #if 0 156 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 157 BMCR_LOOP | BMCR_S100); 158 #endif 159 160 brgphy_mii_model = MII_MODEL(ma->mii_id2); 161 brgphy_reset(sc); 162 163 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 164 sc->mii_capabilities &= ~BMSR_ANEG; 165 device_printf(dev, " "); 166 mii_add_media(sc); 167 168 /* Find the driver associated with this PHY. */ 169 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) { 170 bge_sc = mii->mii_ifp->if_softc; 171 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) { 172 bce_sc = mii->mii_ifp->if_softc; 173 } 174 175 /* The 590x chips are 10/100 only. */ 176 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 177 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 178 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 179 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 180 fast_ether_only = TRUE; 181 182 if (fast_ether_only == FALSE) { 183 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 184 sc->mii_inst), BRGPHY_BMCR_FDX); 185 PRINT(", 1000baseTX"); 186 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 187 IFM_FDX, sc->mii_inst), 0); 188 PRINT("1000baseTX-FDX"); 189 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 190 } else 191 sc->mii_anegticks = MII_ANEGTICKS; 192 193 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 194 PRINT("auto"); 195 196 printf("\n"); 197 #undef ADD 198 #undef PRINT 199 200 MIIBUS_MEDIAINIT(sc->mii_dev); 201 return (0); 202 } 203 204 static int 205 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 206 { 207 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 208 209 switch (cmd) { 210 case MII_POLLSTAT: 211 /* If we're not polling our PHY instance, just return. */ 212 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 213 return (0); 214 break; 215 case MII_MEDIACHG: 216 /* 217 * If the media indicates a different PHY instance, 218 * isolate ourselves. 219 */ 220 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 221 PHY_WRITE(sc, MII_BMCR, 222 PHY_READ(sc, MII_BMCR) | BMCR_ISO); 223 return (0); 224 } 225 226 /* If the interface is not up, don't do anything. */ 227 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 228 break; 229 230 brgphy_reset(sc); /* XXX hardware bug work-around */ 231 232 switch (IFM_SUBTYPE(ife->ifm_media)) { 233 case IFM_AUTO: 234 #ifdef foo 235 /* If we're already in auto mode, just return. */ 236 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 237 return (0); 238 #endif 239 (void)brgphy_mii_phy_auto(sc); 240 break; 241 case IFM_1000_T: 242 case IFM_100_TX: 243 case IFM_10_T: 244 brgphy_setmedia(sc, ife->ifm_media, 245 mii->mii_ifp->if_flags & IFF_LINK0); 246 break; 247 #ifdef foo 248 case IFM_NONE: 249 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 250 break; 251 #endif 252 case IFM_100_T4: 253 default: 254 return (EINVAL); 255 } 256 break; 257 case MII_TICK: 258 /* If we're not currently selected, just return. */ 259 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 260 return (0); 261 262 /* Is the interface even up? */ 263 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 264 return (0); 265 266 /* Only used for autonegotiation. */ 267 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 268 sc->mii_ticks = 0; /* Reset autoneg timer. */ 269 break; 270 } 271 272 /* 273 * Check to see if we have link. If we do, we don't 274 * need to restart the autonegotiation process. 275 */ 276 if (PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK) { 277 sc->mii_ticks = 0; /* Reset autoneg timer. */ 278 break; 279 } 280 281 /* Announce link loss right after it happens. */ 282 if (sc->mii_ticks++ == 0) 283 break; 284 285 /* Only retry autonegotiation every mii_anegticks seconds. */ 286 if (sc->mii_ticks <= sc->mii_anegticks) 287 return (0); 288 289 sc->mii_ticks = 0; 290 (void)brgphy_mii_phy_auto(sc); 291 break; 292 } 293 294 /* Update the media status. */ 295 brgphy_status(sc); 296 297 /* 298 * Callback if something changed. Note that we need to poke 299 * the DSP on the Broadcom PHYs if the media changes. 300 */ 301 if (sc->mii_media_active != mii->mii_media_active || 302 sc->mii_media_status != mii->mii_media_status || 303 cmd == MII_MEDIACHG) { 304 switch (brgphy_mii_model) { 305 case MII_MODEL_xxBROADCOM_BCM5400: 306 case MII_MODEL_xxBROADCOM_BCM5401: 307 bcm5401_load_dspcode(sc); 308 break; 309 case MII_MODEL_xxBROADCOM_BCM5411: 310 bcm5411_load_dspcode(sc); 311 break; 312 } 313 } 314 mii_phy_update(sc, cmd); 315 return (0); 316 } 317 318 static void 319 brgphy_setmedia(struct mii_softc *sc, int media, int master) 320 { 321 int bmcr, gig; 322 323 switch (IFM_SUBTYPE(media)) { 324 case IFM_1000_T: 325 bmcr = BRGPHY_S1000; 326 break; 327 case IFM_100_TX: 328 bmcr = BRGPHY_S100; 329 break; 330 case IFM_10_T: 331 default: 332 bmcr = BRGPHY_S10; 333 break; 334 } 335 if ((media & IFM_GMASK) == IFM_FDX) { 336 bmcr |= BRGPHY_BMCR_FDX; 337 gig = BRGPHY_1000CTL_AFD; 338 } else { 339 gig = BRGPHY_1000CTL_AHD; 340 } 341 342 brgphy_loop(sc); 343 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 344 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 345 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 346 347 if (IFM_SUBTYPE(media) != IFM_1000_T) 348 return; 349 350 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 351 PHY_WRITE(sc, BRGPHY_MII_BMCR, 352 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 353 354 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 355 return; 356 357 /* 358 * When setting the link manually, one side must be the master and 359 * the other the slave. However ifmedia doesn't give us a good way 360 * to specify this, so we fake it by using one of the LINK flags. 361 * If LINK0 is set, we program the PHY to be a master, otherwise 362 * it's a slave. 363 */ 364 if (master) { 365 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 366 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); 367 } else { 368 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 369 gig | BRGPHY_1000CTL_MSE); 370 } 371 } 372 373 static void 374 brgphy_status(struct mii_softc *sc) 375 { 376 struct mii_data *mii = sc->mii_pdata; 377 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 378 int bmcr, bmsr; 379 380 mii->mii_media_status = IFM_AVALID; 381 mii->mii_media_active = IFM_ETHER; 382 383 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 384 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 385 386 if (bmsr & BRGPHY_BMSR_LINK) 387 mii->mii_media_status |= IFM_ACTIVE; 388 389 if (bmcr & BRGPHY_BMCR_LOOP) 390 mii->mii_media_active |= IFM_LOOP; 391 392 if (bmcr & BRGPHY_BMCR_AUTOEN) { 393 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 394 /* Erg, still trying, I guess... */ 395 mii->mii_media_active |= IFM_NONE; 396 return; 397 } 398 } 399 400 if (bmsr & BRGPHY_BMSR_LINK) { 401 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 402 BRGPHY_AUXSTS_AN_RES) { 403 case BRGPHY_RES_1000FD: 404 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 405 break; 406 case BRGPHY_RES_1000HD: 407 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 408 break; 409 case BRGPHY_RES_100FD: 410 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 411 break; 412 case BRGPHY_RES_100T4: 413 mii->mii_media_active |= IFM_100_T4; 414 break; 415 case BRGPHY_RES_100HD: 416 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 417 break; 418 case BRGPHY_RES_10FD: 419 mii->mii_media_active |= IFM_10_T | IFM_FDX; 420 break; 421 case BRGPHY_RES_10HD: 422 mii->mii_media_active |= IFM_10_T | IFM_HDX; 423 break; 424 default: 425 mii->mii_media_active |= IFM_NONE; 426 break; 427 } 428 } else 429 mii->mii_media_active = ife->ifm_media; 430 } 431 432 static int 433 brgphy_mii_phy_auto(struct mii_softc *sc) 434 { 435 int ktcr = 0; 436 437 brgphy_loop(sc); 438 brgphy_reset(sc); 439 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 440 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 441 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 442 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 443 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 444 DELAY(1000); 445 PHY_WRITE(sc, BRGPHY_MII_ANAR, 446 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); 447 DELAY(1000); 448 PHY_WRITE(sc, BRGPHY_MII_BMCR, 449 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 450 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 451 return (EJUSTRETURN); 452 } 453 454 static void 455 brgphy_loop(struct mii_softc *sc) 456 { 457 int i; 458 459 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 460 for (i = 0; i < 15000; i++) { 461 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) { 462 #if 0 463 device_printf(sc->mii_dev, "looped %d\n", i); 464 #endif 465 break; 466 } 467 DELAY(10); 468 } 469 } 470 471 /* Turn off tap power management on 5401. */ 472 static void 473 bcm5401_load_dspcode(struct mii_softc *sc) 474 { 475 static const struct { 476 int reg; 477 uint16_t val; 478 } dspcode[] = { 479 { BRGPHY_MII_AUXCTL, 0x0c20 }, 480 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 481 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 482 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 483 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 484 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 485 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 486 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 487 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 488 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 489 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 490 { 0, 0 }, 491 }; 492 int i; 493 494 for (i = 0; dspcode[i].reg != 0; i++) 495 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 496 DELAY(40); 497 } 498 499 static void 500 bcm5411_load_dspcode(struct mii_softc *sc) 501 { 502 static const struct { 503 int reg; 504 uint16_t val; 505 } dspcode[] = { 506 { 0x1c, 0x8c23 }, 507 { 0x1c, 0x8ca3 }, 508 { 0x1c, 0x8c23 }, 509 { 0, 0 }, 510 }; 511 int i; 512 513 for (i = 0; dspcode[i].reg != 0; i++) 514 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 515 } 516 517 static void 518 bcm5703_load_dspcode(struct mii_softc *sc) 519 { 520 static const struct { 521 int reg; 522 uint16_t val; 523 } dspcode[] = { 524 { BRGPHY_MII_AUXCTL, 0x0c00 }, 525 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 526 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 527 { 0, 0 }, 528 }; 529 int i; 530 531 for (i = 0; dspcode[i].reg != 0; i++) 532 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 533 } 534 535 static void 536 bcm5704_load_dspcode(struct mii_softc *sc) 537 { 538 static const struct { 539 int reg; 540 u_int16_t val; 541 } dspcode[] = { 542 { 0x1c, 0x8d68 }, 543 { 0x1c, 0x8d68 }, 544 { 0, 0 }, 545 }; 546 int i; 547 548 for (i = 0; dspcode[i].reg != 0; i++) 549 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 550 } 551 552 static void 553 bcm5750_load_dspcode(struct mii_softc *sc) 554 { 555 static const struct { 556 int reg; 557 u_int16_t val; 558 } dspcode[] = { 559 { 0x18, 0x0c00 }, 560 { 0x17, 0x000a }, 561 { 0x15, 0x310b }, 562 { 0x17, 0x201f }, 563 { 0x15, 0x9506 }, 564 { 0x17, 0x401f }, 565 { 0x15, 0x14e2 }, 566 { 0x18, 0x0400 }, 567 { 0, 0 }, 568 }; 569 int i; 570 571 for (i = 0; dspcode[i].reg != 0; i++) 572 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 573 } 574 575 static void 576 brgphy_reset(struct mii_softc *sc) 577 { 578 u_int32_t val; 579 struct ifnet *ifp; 580 struct bge_softc *bge_sc = NULL; 581 struct bce_softc *bce_sc = NULL; 582 583 mii_phy_reset(sc); 584 585 switch (brgphy_mii_model) { 586 case MII_MODEL_xxBROADCOM_BCM5400: 587 case MII_MODEL_xxBROADCOM_BCM5401: 588 bcm5401_load_dspcode(sc); 589 break; 590 case MII_MODEL_xxBROADCOM_BCM5411: 591 bcm5411_load_dspcode(sc); 592 break; 593 case MII_MODEL_xxBROADCOM_BCM5703: 594 bcm5703_load_dspcode(sc); 595 break; 596 case MII_MODEL_xxBROADCOM_BCM5704: 597 bcm5704_load_dspcode(sc); 598 break; 599 case MII_MODEL_xxBROADCOM_BCM5750: 600 case MII_MODEL_xxBROADCOM_BCM5752: 601 case MII_MODEL_xxBROADCOM_BCM5714: 602 case MII_MODEL_xxBROADCOM_BCM5780: 603 case MII_MODEL_xxBROADCOM_BCM5706C: 604 case MII_MODEL_xxBROADCOM_BCM5708C: 605 bcm5750_load_dspcode(sc); 606 break; 607 } 608 609 ifp = sc->mii_pdata->mii_ifp; 610 611 /* Find the driver associated with this PHY. */ 612 if (strcmp(ifp->if_dname, "bge") == 0) { 613 bge_sc = ifp->if_softc; 614 } else if (strcmp(ifp->if_dname, "bce") == 0) { 615 bce_sc = ifp->if_softc; 616 } 617 618 /* Handle any NetXtreme/bge workarounds. */ 619 if (bge_sc) { 620 /* 621 * Don't enable Ethernet@WireSpeed for the 5700 or the 622 * 5705 A1 and A2 chips. Make sure we only do this test 623 * on "bge" NICs, since other drivers may use this same 624 * PHY subdriver. 625 */ 626 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 627 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 628 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2) 629 return; 630 631 /* Enable Ethernet@WireSpeed. */ 632 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 633 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 634 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 635 636 /* Enable Link LED on Dell boxes */ 637 if (bge_sc->bge_flags & BGE_FLAG_NO3LED) { 638 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 639 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 640 ~BRGPHY_PHY_EXTCTL_3_LED); 641 } 642 } else if (bce_sc) { 643 /* Set or clear jumbo frame settings in the PHY. */ 644 if (ifp->if_mtu > ETHER_MAX_LEN) { 645 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 646 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 647 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 648 val | BRGPHY_AUXCTL_LONG_PKT); 649 650 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 651 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 652 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 653 } else { 654 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 655 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 656 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 657 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 658 659 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 660 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 661 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 662 } 663 664 /* Enable Ethernet@Wirespeed */ 665 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 666 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 667 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4))); 668 } 669 } 670