1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/brgphyreg.h> 56 #include <net/if_arp.h> 57 #include <machine/bus.h> 58 #include <dev/bge/if_bgereg.h> 59 #include <dev/bce/if_bcereg.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 #include "miibus_if.h" 65 66 static int brgphy_probe(device_t); 67 static int brgphy_attach(device_t); 68 69 struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int mii_model; 72 int mii_rev; 73 }; 74 75 static device_method_t brgphy_methods[] = { 76 /* device interface */ 77 DEVMETHOD(device_probe, brgphy_probe), 78 DEVMETHOD(device_attach, brgphy_attach), 79 DEVMETHOD(device_detach, mii_phy_detach), 80 DEVMETHOD(device_shutdown, bus_generic_shutdown), 81 { 0, 0 } 82 }; 83 84 static devclass_t brgphy_devclass; 85 86 static driver_t brgphy_driver = { 87 "brgphy", 88 brgphy_methods, 89 sizeof(struct brgphy_softc) 90 }; 91 92 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 93 94 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 95 static void brgphy_setmedia(struct mii_softc *, int, int); 96 static void brgphy_status(struct mii_softc *); 97 static int brgphy_mii_phy_auto(struct mii_softc *); 98 static void brgphy_reset(struct mii_softc *); 99 static void brgphy_loop(struct mii_softc *); 100 static int bcm5706_is_tbi(device_t); 101 static void bcm5401_load_dspcode(struct mii_softc *); 102 static void bcm5411_load_dspcode(struct mii_softc *); 103 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 104 static void brgphy_fixup_adc_bug(struct mii_softc *); 105 static void brgphy_fixup_adjust_trim(struct mii_softc *); 106 static void brgphy_fixup_ber_bug(struct mii_softc *); 107 static void brgphy_fixup_crc_bug(struct mii_softc *); 108 static void brgphy_fixup_jitter_bug(struct mii_softc *); 109 static void brgphy_ethernet_wirespeed(struct mii_softc *); 110 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 111 112 static const struct mii_phydesc brgphys[] = { 113 MII_PHY_DESC(xxBROADCOM, BCM5400), 114 MII_PHY_DESC(xxBROADCOM, BCM5401), 115 MII_PHY_DESC(xxBROADCOM, BCM5411), 116 MII_PHY_DESC(xxBROADCOM, BCM5701), 117 MII_PHY_DESC(xxBROADCOM, BCM5703), 118 MII_PHY_DESC(xxBROADCOM, BCM5704), 119 MII_PHY_DESC(xxBROADCOM, BCM5705), 120 MII_PHY_DESC(xxBROADCOM, BCM5706C), 121 MII_PHY_DESC(xxBROADCOM, BCM5714), 122 MII_PHY_DESC(xxBROADCOM, BCM5750), 123 MII_PHY_DESC(xxBROADCOM, BCM5752), 124 MII_PHY_DESC(xxBROADCOM, BCM5754), 125 MII_PHY_DESC(xxBROADCOM, BCM5780), 126 MII_PHY_DESC(xxBROADCOM, BCM5708C), 127 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 128 MII_PHY_END 129 }; 130 131 static int 132 brgphy_probe(device_t dev) 133 { 134 struct mii_attach_args *ma; 135 int error; 136 137 error = mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT); 138 if (error != BUS_PROBE_DEFAULT) 139 return (error); 140 141 ma = device_get_ivars(dev); 142 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 143 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5706C) { 144 /* 145 * Broadcom uses the same MII model ID on two 146 * different types of phys. The first is found on the 147 * BCM 5706 and is supported by this driver. The 148 * other is found on the BCM 5706S and 5708S and is 149 * supported by the gentbi(4) driver, so we check to 150 * see if this phy is supported by gentbi(4) and fail 151 * the probe if so. 152 */ 153 if (bcm5706_is_tbi(dev)) 154 return (ENXIO); 155 } 156 return (error); 157 } 158 159 static int 160 brgphy_attach(device_t dev) 161 { 162 struct brgphy_softc *bsc; 163 struct mii_softc *sc; 164 struct mii_attach_args *ma; 165 struct mii_data *mii; 166 const char *sep = ""; 167 struct bge_softc *bge_sc = NULL; 168 struct bce_softc *bce_sc = NULL; 169 int fast_ether_only = FALSE; 170 171 bsc = device_get_softc(dev); 172 sc = &bsc->mii_sc; 173 ma = device_get_ivars(dev); 174 sc->mii_dev = device_get_parent(dev); 175 mii = device_get_softc(sc->mii_dev); 176 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 177 178 sc->mii_inst = mii->mii_instance; 179 sc->mii_phy = ma->mii_phyno; 180 sc->mii_service = brgphy_service; 181 sc->mii_pdata = mii; 182 183 sc->mii_flags |= MIIF_NOISOLATE; 184 mii->mii_instance++; 185 186 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 187 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 188 189 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 190 BMCR_ISO); 191 #if 0 192 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 193 BMCR_LOOP | BMCR_S100); 194 #endif 195 196 bsc->mii_model = MII_MODEL(ma->mii_id2); 197 bsc->mii_rev = MII_REV(ma->mii_id2); 198 brgphy_reset(sc); 199 200 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 201 sc->mii_capabilities &= ~BMSR_ANEG; 202 device_printf(dev, " "); 203 mii_add_media(sc); 204 205 /* Find the driver associated with this PHY. */ 206 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) { 207 bge_sc = mii->mii_ifp->if_softc; 208 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) { 209 bce_sc = mii->mii_ifp->if_softc; 210 } 211 212 /* The 590x chips are 10/100 only. */ 213 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 214 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 215 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 216 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 217 fast_ether_only = TRUE; 218 219 if (fast_ether_only == FALSE) { 220 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 221 sc->mii_inst), BRGPHY_BMCR_FDX); 222 PRINT(", 1000baseTX"); 223 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 224 IFM_FDX, sc->mii_inst), 0); 225 PRINT("1000baseTX-FDX"); 226 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 227 } else 228 sc->mii_anegticks = MII_ANEGTICKS; 229 230 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 231 PRINT("auto"); 232 233 printf("\n"); 234 #undef ADD 235 #undef PRINT 236 237 MIIBUS_MEDIAINIT(sc->mii_dev); 238 return (0); 239 } 240 241 static int 242 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 243 { 244 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 245 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 246 247 switch (cmd) { 248 case MII_POLLSTAT: 249 /* If we're not polling our PHY instance, just return. */ 250 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 251 return (0); 252 break; 253 case MII_MEDIACHG: 254 /* 255 * If the media indicates a different PHY instance, 256 * isolate ourselves. 257 */ 258 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 259 PHY_WRITE(sc, MII_BMCR, 260 PHY_READ(sc, MII_BMCR) | BMCR_ISO); 261 return (0); 262 } 263 264 /* If the interface is not up, don't do anything. */ 265 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 266 break; 267 268 brgphy_reset(sc); /* XXX hardware bug work-around */ 269 270 switch (IFM_SUBTYPE(ife->ifm_media)) { 271 case IFM_AUTO: 272 #ifdef foo 273 /* If we're already in auto mode, just return. */ 274 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 275 return (0); 276 #endif 277 (void)brgphy_mii_phy_auto(sc); 278 break; 279 case IFM_1000_T: 280 case IFM_100_TX: 281 case IFM_10_T: 282 brgphy_setmedia(sc, ife->ifm_media, 283 mii->mii_ifp->if_flags & IFF_LINK0); 284 break; 285 #ifdef foo 286 case IFM_NONE: 287 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 288 break; 289 #endif 290 case IFM_100_T4: 291 default: 292 return (EINVAL); 293 } 294 break; 295 case MII_TICK: 296 /* If we're not currently selected, just return. */ 297 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 298 return (0); 299 300 /* Is the interface even up? */ 301 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 302 return (0); 303 304 /* Only used for autonegotiation. */ 305 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 306 sc->mii_ticks = 0; /* Reset autoneg timer. */ 307 break; 308 } 309 310 /* 311 * Check to see if we have link. If we do, we don't 312 * need to restart the autonegotiation process. 313 */ 314 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) { 315 sc->mii_ticks = 0; /* Reset autoneg timer. */ 316 break; 317 } 318 319 /* Announce link loss right after it happens. */ 320 if (sc->mii_ticks++ == 0) 321 break; 322 323 /* Only retry autonegotiation every mii_anegticks seconds. */ 324 if (sc->mii_ticks <= sc->mii_anegticks) 325 return (0); 326 327 sc->mii_ticks = 0; 328 (void)brgphy_mii_phy_auto(sc); 329 break; 330 } 331 332 /* Update the media status. */ 333 brgphy_status(sc); 334 335 /* 336 * Callback if something changed. Note that we need to poke 337 * the DSP on the Broadcom PHYs if the media changes. 338 */ 339 if (sc->mii_media_active != mii->mii_media_active || 340 sc->mii_media_status != mii->mii_media_status || 341 cmd == MII_MEDIACHG) { 342 switch (bsc->mii_model) { 343 case MII_MODEL_xxBROADCOM_BCM5400: 344 bcm5401_load_dspcode(sc); 345 break; 346 case MII_MODEL_xxBROADCOM_BCM5401: 347 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 348 bcm5401_load_dspcode(sc); 349 break; 350 case MII_MODEL_xxBROADCOM_BCM5411: 351 bcm5411_load_dspcode(sc); 352 break; 353 } 354 } 355 mii_phy_update(sc, cmd); 356 return (0); 357 } 358 359 static void 360 brgphy_setmedia(struct mii_softc *sc, int media, int master) 361 { 362 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 363 int bmcr, gig; 364 365 switch (IFM_SUBTYPE(media)) { 366 case IFM_1000_T: 367 bmcr = BRGPHY_S1000; 368 break; 369 case IFM_100_TX: 370 bmcr = BRGPHY_S100; 371 break; 372 case IFM_10_T: 373 default: 374 bmcr = BRGPHY_S10; 375 break; 376 } 377 if ((media & IFM_GMASK) == IFM_FDX) { 378 bmcr |= BRGPHY_BMCR_FDX; 379 gig = BRGPHY_1000CTL_AFD; 380 } else { 381 gig = BRGPHY_1000CTL_AHD; 382 } 383 384 brgphy_loop(sc); 385 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 386 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 387 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 388 389 if (IFM_SUBTYPE(media) != IFM_1000_T) 390 return; 391 392 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 393 PHY_WRITE(sc, BRGPHY_MII_BMCR, 394 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 395 396 if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 397 return; 398 399 /* 400 * When setting the link manually, one side must be the master and 401 * the other the slave. However ifmedia doesn't give us a good way 402 * to specify this, so we fake it by using one of the LINK flags. 403 * If LINK0 is set, we program the PHY to be a master, otherwise 404 * it's a slave. 405 */ 406 if (master) { 407 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 408 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); 409 } else { 410 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 411 gig | BRGPHY_1000CTL_MSE); 412 } 413 } 414 415 static void 416 brgphy_status(struct mii_softc *sc) 417 { 418 struct mii_data *mii = sc->mii_pdata; 419 int aux, bmcr, bmsr; 420 421 mii->mii_media_status = IFM_AVALID; 422 mii->mii_media_active = IFM_ETHER; 423 424 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 425 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 426 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 427 428 if (aux & BRGPHY_AUXSTS_LINK) 429 mii->mii_media_status |= IFM_ACTIVE; 430 431 if (bmcr & BRGPHY_BMCR_LOOP) 432 mii->mii_media_active |= IFM_LOOP; 433 434 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 435 (bmsr & BRGPHY_BMSR_ACOMP) == 0) { 436 /* Erg, still trying, I guess... */ 437 mii->mii_media_active |= IFM_NONE; 438 return; 439 } 440 441 if (aux & BRGPHY_AUXSTS_LINK) { 442 switch (aux & BRGPHY_AUXSTS_AN_RES) { 443 case BRGPHY_RES_1000FD: 444 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 445 break; 446 case BRGPHY_RES_1000HD: 447 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 448 break; 449 case BRGPHY_RES_100FD: 450 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 451 break; 452 case BRGPHY_RES_100T4: 453 mii->mii_media_active |= IFM_100_T4; 454 break; 455 case BRGPHY_RES_100HD: 456 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 457 break; 458 case BRGPHY_RES_10FD: 459 mii->mii_media_active |= IFM_10_T | IFM_FDX; 460 break; 461 case BRGPHY_RES_10HD: 462 mii->mii_media_active |= IFM_10_T | IFM_HDX; 463 break; 464 default: 465 mii->mii_media_active |= IFM_NONE; 466 break; 467 } 468 } else 469 mii->mii_media_active |= IFM_NONE; 470 } 471 472 static int 473 brgphy_mii_phy_auto(struct mii_softc *sc) 474 { 475 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 476 int ktcr = 0; 477 478 brgphy_loop(sc); 479 brgphy_reset(sc); 480 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 481 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 482 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 483 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 484 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 485 DELAY(1000); 486 PHY_WRITE(sc, BRGPHY_MII_ANAR, 487 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); 488 DELAY(1000); 489 PHY_WRITE(sc, BRGPHY_MII_BMCR, 490 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 491 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 492 return (EJUSTRETURN); 493 } 494 495 static void 496 brgphy_loop(struct mii_softc *sc) 497 { 498 int i; 499 500 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 501 for (i = 0; i < 15000; i++) { 502 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) { 503 #if 0 504 device_printf(sc->mii_dev, "looped %d\n", i); 505 #endif 506 break; 507 } 508 DELAY(10); 509 } 510 } 511 512 /* 513 * Check to see if a 5706 phy is really a SerDes phy. Copied from 514 * gentbi_probe(). 515 */ 516 static int 517 bcm5706_is_tbi(device_t dev) 518 { 519 device_t parent; 520 struct mii_attach_args *ma; 521 int bmsr, extsr; 522 523 parent = device_get_parent(dev); 524 ma = device_get_ivars(dev); 525 526 bmsr = MIIBUS_READREG(parent, ma->mii_phyno, MII_BMSR); 527 if ((bmsr & BMSR_EXTSTAT) == 0 || (bmsr & BMSR_MEDIAMASK) != 0) 528 return (0); 529 530 extsr = MIIBUS_READREG(parent, ma->mii_phyno, MII_EXTSR); 531 if (extsr & (EXTSR_1000TFDX|EXTSR_1000THDX)) 532 return (0); 533 534 if (extsr & (EXTSR_1000XFDX|EXTSR_1000XHDX)) 535 return (1); 536 537 return (0); 538 } 539 540 /* Turn off tap power management on 5401. */ 541 static void 542 bcm5401_load_dspcode(struct mii_softc *sc) 543 { 544 static const struct { 545 int reg; 546 uint16_t val; 547 } dspcode[] = { 548 { BRGPHY_MII_AUXCTL, 0x0c20 }, 549 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 550 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 551 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 552 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 553 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 554 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 555 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 556 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 557 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 558 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 559 { 0, 0 }, 560 }; 561 int i; 562 563 for (i = 0; dspcode[i].reg != 0; i++) 564 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 565 DELAY(40); 566 } 567 568 static void 569 bcm5411_load_dspcode(struct mii_softc *sc) 570 { 571 static const struct { 572 int reg; 573 uint16_t val; 574 } dspcode[] = { 575 { 0x1c, 0x8c23 }, 576 { 0x1c, 0x8ca3 }, 577 { 0x1c, 0x8c23 }, 578 { 0, 0 }, 579 }; 580 int i; 581 582 for (i = 0; dspcode[i].reg != 0; i++) 583 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 584 } 585 586 static void 587 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 588 { 589 static const struct { 590 int reg; 591 uint16_t val; 592 } dspcode[] = { 593 { 0x1c, 0x8d68 }, 594 { 0x1c, 0x8d68 }, 595 { 0, 0 }, 596 }; 597 int i; 598 599 for (i = 0; dspcode[i].reg != 0; i++) 600 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 601 } 602 603 static void 604 brgphy_fixup_adc_bug(struct mii_softc *sc) 605 { 606 static const struct { 607 int reg; 608 uint16_t val; 609 } dspcode[] = { 610 { BRGPHY_MII_AUXCTL, 0x0c00 }, 611 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 612 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 613 { 0, 0 }, 614 }; 615 int i; 616 617 for (i = 0; dspcode[i].reg != 0; i++) 618 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 619 } 620 621 static void 622 brgphy_fixup_adjust_trim(struct mii_softc *sc) 623 { 624 static const struct { 625 int reg; 626 uint16_t val; 627 } dspcode[] = { 628 { BRGPHY_MII_AUXCTL, 0x0c00 }, 629 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 630 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 631 { BRGPHY_MII_TEST1, 0x0014 }, 632 { BRGPHY_MII_AUXCTL, 0x0400 }, 633 { 0, 0 }, 634 }; 635 int i; 636 637 for (i = 0; dspcode[i].reg != 0; i++) 638 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 639 } 640 641 static void 642 brgphy_fixup_ber_bug(struct mii_softc *sc) 643 { 644 static const struct { 645 int reg; 646 uint16_t val; 647 } dspcode[] = { 648 { BRGPHY_MII_AUXCTL, 0x0c00 }, 649 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 650 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 651 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 652 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 653 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 654 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 655 { BRGPHY_MII_AUXCTL, 0x0400 }, 656 { 0, 0 }, 657 }; 658 int i; 659 660 for (i = 0; dspcode[i].reg != 0; i++) 661 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 662 } 663 664 static void 665 brgphy_fixup_crc_bug(struct mii_softc *sc) 666 { 667 static const struct { 668 int reg; 669 uint16_t val; 670 } dspcode[] = { 671 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 672 { 0x1c, 0x8c68 }, 673 { 0x1c, 0x8d68 }, 674 { 0x1c, 0x8c68 }, 675 { 0, 0 }, 676 }; 677 int i; 678 679 for (i = 0; dspcode[i].reg != 0; i++) 680 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 681 } 682 683 static void 684 brgphy_fixup_jitter_bug(struct mii_softc *sc) 685 { 686 static const struct { 687 int reg; 688 uint16_t val; 689 } dspcode[] = { 690 { BRGPHY_MII_AUXCTL, 0x0c00 }, 691 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 692 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 693 { BRGPHY_MII_AUXCTL, 0x0400 }, 694 { 0, 0 }, 695 }; 696 int i; 697 698 for (i = 0; dspcode[i].reg != 0; i++) 699 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 700 } 701 702 static void 703 brgphy_ethernet_wirespeed(struct mii_softc *sc) 704 { 705 uint32_t val; 706 707 /* Enable Ethernet@WireSpeed. */ 708 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 709 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 710 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 711 } 712 713 static void 714 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 715 { 716 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 717 uint32_t val; 718 719 /* Set or clear jumbo frame settings in the PHY. */ 720 if (mtu > ETHER_MAX_LEN) { 721 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 722 /* BCM5401 PHY cannot read-modify-write. */ 723 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 724 } else { 725 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 726 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 727 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 728 val | BRGPHY_AUXCTL_LONG_PKT); 729 } 730 731 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 732 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 733 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 734 } else { 735 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 736 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 737 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 738 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 739 740 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 741 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 742 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 743 } 744 } 745 746 static void 747 brgphy_reset(struct mii_softc *sc) 748 { 749 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 750 struct bge_softc *bge_sc = NULL; 751 struct bce_softc *bce_sc = NULL; 752 struct ifnet *ifp; 753 754 mii_phy_reset(sc); 755 756 switch (bsc->mii_model) { 757 case MII_MODEL_xxBROADCOM_BCM5400: 758 bcm5401_load_dspcode(sc); 759 break; 760 case MII_MODEL_xxBROADCOM_BCM5401: 761 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 762 bcm5401_load_dspcode(sc); 763 break; 764 case MII_MODEL_xxBROADCOM_BCM5411: 765 bcm5411_load_dspcode(sc); 766 break; 767 } 768 769 ifp = sc->mii_pdata->mii_ifp; 770 771 /* Find the driver associated with this PHY. */ 772 if (strcmp(ifp->if_dname, "bge") == 0) { 773 bge_sc = ifp->if_softc; 774 } else if (strcmp(ifp->if_dname, "bce") == 0) { 775 bce_sc = ifp->if_softc; 776 } 777 778 /* Handle any NetXtreme/bge workarounds. */ 779 if (bge_sc) { 780 /* Fix up various bugs */ 781 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) 782 brgphy_fixup_5704_a0_bug(sc); 783 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) 784 brgphy_fixup_adc_bug(sc); 785 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) 786 brgphy_fixup_adjust_trim(sc); 787 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) 788 brgphy_fixup_ber_bug(sc); 789 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) 790 brgphy_fixup_crc_bug(sc); 791 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) 792 brgphy_fixup_jitter_bug(sc); 793 794 brgphy_jumbo_settings(sc, ifp->if_mtu); 795 796 /* 797 * Don't enable Ethernet@WireSpeed for the 5700 or the 798 * 5705 A1 and A2 chips. 799 */ 800 if (bge_sc->bge_asicrev != BGE_ASICREV_BCM5700 && 801 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A1 && 802 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A2) 803 brgphy_ethernet_wirespeed(sc); 804 805 /* Enable Link LED on Dell boxes */ 806 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { 807 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 808 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 809 ~BRGPHY_PHY_EXTCTL_3_LED); 810 } 811 } else if (bce_sc) { 812 brgphy_fixup_ber_bug(sc); 813 brgphy_jumbo_settings(sc, ifp->if_mtu); 814 brgphy_ethernet_wirespeed(sc); 815 } 816 } 817