1 /* 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 35 * 1000mbps; all we need to negotiate here is full or half duplex. 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <machine/clock.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include "miidevs.h" 55 56 #include <dev/mii/brgphyreg.h> 57 #include <net/if_arp.h> 58 #include <machine/bus.h> 59 #include <dev/bge/if_bgereg.h> 60 61 #include "miibus_if.h" 62 63 static int brgphy_probe(device_t); 64 static int brgphy_attach(device_t); 65 66 static device_method_t brgphy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, brgphy_probe), 69 DEVMETHOD(device_attach, brgphy_attach), 70 DEVMETHOD(device_detach, mii_phy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 { 0, 0 } 73 }; 74 75 static devclass_t brgphy_devclass; 76 77 static driver_t brgphy_driver = { 78 "brgphy", 79 brgphy_methods, 80 sizeof(struct mii_softc) 81 }; 82 83 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 84 85 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 86 static void brgphy_status(struct mii_softc *); 87 static int brgphy_mii_phy_auto(struct mii_softc *); 88 static void brgphy_reset(struct mii_softc *); 89 static void brgphy_loop(struct mii_softc *); 90 static void bcm5401_load_dspcode(struct mii_softc *); 91 static void bcm5411_load_dspcode(struct mii_softc *); 92 static void bcm5703_load_dspcode(struct mii_softc *); 93 static int brgphy_mii_model; 94 95 static int 96 brgphy_probe(dev) 97 device_t dev; 98 { 99 struct mii_attach_args *ma; 100 101 ma = device_get_ivars(dev); 102 103 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 104 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 105 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 106 return(0); 107 } 108 109 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 110 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 111 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 112 return(0); 113 } 114 115 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 116 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 117 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 118 return(0); 119 } 120 121 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 122 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 123 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 124 return(0); 125 } 126 127 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 128 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 129 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 130 return(0); 131 } 132 133 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 134 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 135 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 136 return(0); 137 } 138 139 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 140 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 141 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 142 return(0); 143 } 144 145 return(ENXIO); 146 } 147 148 static int 149 brgphy_attach(dev) 150 device_t dev; 151 { 152 struct mii_softc *sc; 153 struct mii_attach_args *ma; 154 struct mii_data *mii; 155 const char *sep = ""; 156 157 sc = device_get_softc(dev); 158 ma = device_get_ivars(dev); 159 sc->mii_dev = device_get_parent(dev); 160 mii = device_get_softc(sc->mii_dev); 161 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 162 163 sc->mii_inst = mii->mii_instance; 164 sc->mii_phy = ma->mii_phyno; 165 sc->mii_service = brgphy_service; 166 sc->mii_pdata = mii; 167 168 sc->mii_flags |= MIIF_NOISOLATE; 169 mii->mii_instance++; 170 171 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 172 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 173 174 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 175 BMCR_ISO); 176 #if 0 177 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 178 BMCR_LOOP|BMCR_S100); 179 #endif 180 181 brgphy_mii_model = MII_MODEL(ma->mii_id2); 182 brgphy_reset(sc); 183 184 185 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 186 sc->mii_capabilities &= ~BMSR_ANEG; 187 device_printf(dev, " "); 188 mii_add_media(sc); 189 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 190 BRGPHY_BMCR_FDX); 191 PRINT(", 1000baseTX"); 192 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 193 PRINT("1000baseTX-FDX"); 194 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 195 PRINT("auto"); 196 197 printf("\n"); 198 #undef ADD 199 #undef PRINT 200 201 MIIBUS_MEDIAINIT(sc->mii_dev); 202 return(0); 203 } 204 205 static int 206 brgphy_service(sc, mii, cmd) 207 struct mii_softc *sc; 208 struct mii_data *mii; 209 int cmd; 210 { 211 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 212 int reg, speed, gig; 213 214 switch (cmd) { 215 case MII_POLLSTAT: 216 /* 217 * If we're not polling our PHY instance, just return. 218 */ 219 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 220 return (0); 221 break; 222 223 case MII_MEDIACHG: 224 /* 225 * If the media indicates a different PHY instance, 226 * isolate ourselves. 227 */ 228 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 229 reg = PHY_READ(sc, MII_BMCR); 230 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 231 return (0); 232 } 233 234 /* 235 * If the interface is not up, don't do anything. 236 */ 237 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 238 break; 239 240 brgphy_reset(sc); /* XXX hardware bug work-around */ 241 242 switch (IFM_SUBTYPE(ife->ifm_media)) { 243 case IFM_AUTO: 244 #ifdef foo 245 /* 246 * If we're already in auto mode, just return. 247 */ 248 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 249 return (0); 250 #endif 251 (void) brgphy_mii_phy_auto(sc); 252 break; 253 case IFM_1000_T: 254 speed = BRGPHY_S1000; 255 goto setit; 256 case IFM_100_TX: 257 speed = BRGPHY_S100; 258 goto setit; 259 case IFM_10_T: 260 speed = BRGPHY_S10; 261 setit: 262 brgphy_loop(sc); 263 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 264 speed |= BRGPHY_BMCR_FDX; 265 gig = BRGPHY_1000CTL_AFD; 266 } else { 267 gig = BRGPHY_1000CTL_AHD; 268 } 269 270 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 271 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 272 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 273 274 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 275 break; 276 277 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 278 PHY_WRITE(sc, BRGPHY_MII_BMCR, 279 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 280 281 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 282 break; 283 284 /* 285 * When settning the link manually, one side must 286 * be the master and the other the slave. However 287 * ifmedia doesn't give us a good way to specify 288 * this, so we fake it by using one of the LINK 289 * flags. If LINK0 is set, we program the PHY to 290 * be a master, otherwise it's a slave. 291 */ 292 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 293 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 294 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 295 } else { 296 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 297 gig|BRGPHY_1000CTL_MSE); 298 } 299 break; 300 #ifdef foo 301 case IFM_NONE: 302 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 303 break; 304 #endif 305 case IFM_100_T4: 306 default: 307 return (EINVAL); 308 } 309 break; 310 311 case MII_TICK: 312 /* 313 * If we're not currently selected, just return. 314 */ 315 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 316 return (0); 317 318 /* 319 * Is the interface even up? 320 */ 321 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 322 return (0); 323 324 /* 325 * Only used for autonegotiation. 326 */ 327 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 328 break; 329 330 /* 331 * Check to see if we have link. If we do, we don't 332 * need to restart the autonegotiation process. Read 333 * the BMSR twice in case it's latched. 334 */ 335 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 336 if (reg & BRGPHY_AUXSTS_LINK) 337 break; 338 339 /* 340 * Only retry autonegotiation every 5 seconds. 341 */ 342 if (++sc->mii_ticks != 5) 343 return (0); 344 345 sc->mii_ticks = 0; 346 brgphy_mii_phy_auto(sc); 347 return (0); 348 } 349 350 /* Update the media status. */ 351 brgphy_status(sc); 352 353 /* 354 * Callback if something changed. Note that we need to poke 355 * the DSP on the Broadcom PHYs if the media changes. 356 * 357 */ 358 if (sc->mii_media_active != mii->mii_media_active || 359 sc->mii_media_status != mii->mii_media_status || 360 cmd == MII_MEDIACHG) { 361 mii_phy_update(sc, cmd); 362 switch (brgphy_mii_model) { 363 case MII_MODEL_xxBROADCOM_BCM5401: 364 bcm5401_load_dspcode(sc); 365 break; 366 case MII_MODEL_xxBROADCOM_BCM5411: 367 bcm5411_load_dspcode(sc); 368 break; 369 } 370 } 371 return (0); 372 } 373 374 static void 375 brgphy_status(sc) 376 struct mii_softc *sc; 377 { 378 struct mii_data *mii = sc->mii_pdata; 379 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 380 int bmsr, bmcr; 381 382 mii->mii_media_status = IFM_AVALID; 383 mii->mii_media_active = IFM_ETHER; 384 385 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 386 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 387 mii->mii_media_status |= IFM_ACTIVE; 388 389 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 390 391 if (bmcr & BRGPHY_BMCR_LOOP) 392 mii->mii_media_active |= IFM_LOOP; 393 394 if (bmcr & BRGPHY_BMCR_AUTOEN) { 395 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 396 /* Erg, still trying, I guess... */ 397 mii->mii_media_active |= IFM_NONE; 398 return; 399 } 400 401 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 402 BRGPHY_AUXSTS_AN_RES) { 403 case BRGPHY_RES_1000FD: 404 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 405 break; 406 case BRGPHY_RES_1000HD: 407 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 408 break; 409 case BRGPHY_RES_100FD: 410 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 411 break; 412 case BRGPHY_RES_100T4: 413 mii->mii_media_active |= IFM_100_T4; 414 break; 415 case BRGPHY_RES_100HD: 416 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 417 break; 418 case BRGPHY_RES_10FD: 419 mii->mii_media_active |= IFM_10_T | IFM_FDX; 420 break; 421 case BRGPHY_RES_10HD: 422 mii->mii_media_active |= IFM_10_T | IFM_HDX; 423 break; 424 default: 425 mii->mii_media_active |= IFM_NONE; 426 break; 427 } 428 return; 429 } 430 431 mii->mii_media_active = ife->ifm_media; 432 433 return; 434 } 435 436 437 static int 438 brgphy_mii_phy_auto(mii) 439 struct mii_softc *mii; 440 { 441 int ktcr = 0; 442 443 brgphy_loop(mii); 444 brgphy_reset(mii); 445 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 446 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 447 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 448 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 449 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 450 DELAY(1000); 451 PHY_WRITE(mii, BRGPHY_MII_ANAR, 452 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 453 DELAY(1000); 454 PHY_WRITE(mii, BRGPHY_MII_BMCR, 455 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 456 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 457 return (EJUSTRETURN); 458 } 459 460 static void 461 brgphy_loop(struct mii_softc *sc) 462 { 463 u_int32_t bmsr; 464 int i; 465 466 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 467 for (i = 0; i < 15000; i++) { 468 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 469 if (!(bmsr & BRGPHY_BMSR_LINK)) { 470 #if 0 471 device_printf(sc->mii_dev, "looped %d\n", i); 472 #endif 473 break; 474 } 475 DELAY(10); 476 } 477 } 478 479 /* Turn off tap power management on 5401. */ 480 static void 481 bcm5401_load_dspcode(struct mii_softc *sc) 482 { 483 static const struct { 484 int reg; 485 uint16_t val; 486 } dspcode[] = { 487 { BRGPHY_MII_AUXCTL, 0x0c20 }, 488 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 489 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 490 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 491 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 492 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 493 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 494 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 495 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 496 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 497 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 498 { 0, 0 }, 499 }; 500 int i; 501 502 for (i = 0; dspcode[i].reg != 0; i++) 503 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 504 DELAY(40); 505 } 506 507 static void 508 bcm5411_load_dspcode(struct mii_softc *sc) 509 { 510 static const struct { 511 int reg; 512 uint16_t val; 513 } dspcode[] = { 514 { 0x1c, 0x8c23 }, 515 { 0x1c, 0x8ca3 }, 516 { 0x1c, 0x8c23 }, 517 { 0, 0 }, 518 }; 519 int i; 520 521 for (i = 0; dspcode[i].reg != 0; i++) 522 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 523 } 524 525 static void 526 bcm5703_load_dspcode(struct mii_softc *sc) 527 { 528 static const struct { 529 int reg; 530 uint16_t val; 531 } dspcode[] = { 532 { BRGPHY_MII_AUXCTL, 0x0c00 }, 533 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 534 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 535 { 0, 0 }, 536 }; 537 int i; 538 539 for (i = 0; dspcode[i].reg != 0; i++) 540 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 541 } 542 543 static void 544 bcm5704_load_dspcode(struct mii_softc *sc) 545 { 546 static const struct { 547 int reg; 548 u_int16_t val; 549 } dspcode[] = { 550 { 0x1c, 0x8d68 }, 551 { 0x1c, 0x8d68 }, 552 { 0, 0 }, 553 }; 554 int i; 555 556 for (i = 0; dspcode[i].reg != 0; i++) 557 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 558 } 559 560 static void 561 brgphy_reset(struct mii_softc *sc) 562 { 563 u_int32_t val; 564 struct ifnet *ifp; 565 struct bge_softc *bge_sc; 566 567 mii_phy_reset(sc); 568 569 switch (brgphy_mii_model) { 570 case MII_MODEL_xxBROADCOM_BCM5401: 571 bcm5401_load_dspcode(sc); 572 break; 573 case MII_MODEL_xxBROADCOM_BCM5411: 574 bcm5411_load_dspcode(sc); 575 break; 576 case MII_MODEL_xxBROADCOM_BCM5703: 577 bcm5703_load_dspcode(sc); 578 break; 579 case MII_MODEL_xxBROADCOM_BCM5704: 580 bcm5704_load_dspcode(sc); 581 break; 582 } 583 584 ifp = sc->mii_pdata->mii_ifp; 585 bge_sc = ifp->if_softc; 586 587 /* 588 * Don't enable Ethernet@WireSpeed for the 5700 or the 589 * 5705 A1 and A2 chips. Make sure we only do this test 590 * on "bge" NICs, since other drivers may use this same 591 * PHY subdriver. 592 */ 593 if (strcmp(ifp->if_name, "bge") == 0 && 594 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 595 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 596 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)) 597 return; 598 599 /* Enable Ethernet@WireSpeed. */ 600 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 601 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 602 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) || (1 << 4)); 603 } 604