1 /* 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/bus.h> 49 50 #include <machine/clock.h> 51 52 #include <net/if.h> 53 #include <net/if_media.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include "miidevs.h" 58 59 #include <dev/mii/brgphyreg.h> 60 #include <net/if_arp.h> 61 #include <machine/bus.h> 62 #include <dev/bge/if_bgereg.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 #include "miibus_if.h" 68 69 static int brgphy_probe(device_t); 70 static int brgphy_attach(device_t); 71 72 static device_method_t brgphy_methods[] = { 73 /* device interface */ 74 DEVMETHOD(device_probe, brgphy_probe), 75 DEVMETHOD(device_attach, brgphy_attach), 76 DEVMETHOD(device_detach, mii_phy_detach), 77 DEVMETHOD(device_shutdown, bus_generic_shutdown), 78 { 0, 0 } 79 }; 80 81 static devclass_t brgphy_devclass; 82 83 static driver_t brgphy_driver = { 84 "brgphy", 85 brgphy_methods, 86 sizeof(struct mii_softc) 87 }; 88 89 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 90 91 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 92 static void brgphy_status(struct mii_softc *); 93 static int brgphy_mii_phy_auto(struct mii_softc *); 94 static void brgphy_reset(struct mii_softc *); 95 static void brgphy_loop(struct mii_softc *); 96 static void bcm5401_load_dspcode(struct mii_softc *); 97 static void bcm5411_load_dspcode(struct mii_softc *); 98 static void bcm5703_load_dspcode(struct mii_softc *); 99 static int brgphy_mii_model; 100 101 static int 102 brgphy_probe(dev) 103 device_t dev; 104 { 105 struct mii_attach_args *ma; 106 107 ma = device_get_ivars(dev); 108 109 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 110 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 111 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 112 return(0); 113 } 114 115 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 116 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 117 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 118 return(0); 119 } 120 121 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 122 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 123 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 124 return(0); 125 } 126 127 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 128 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 129 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 130 return(0); 131 } 132 133 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 134 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 135 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 136 return(0); 137 } 138 139 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 140 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 141 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 142 return(0); 143 } 144 145 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 146 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 147 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 148 return(0); 149 } 150 151 return(ENXIO); 152 } 153 154 static int 155 brgphy_attach(dev) 156 device_t dev; 157 { 158 struct mii_softc *sc; 159 struct mii_attach_args *ma; 160 struct mii_data *mii; 161 const char *sep = ""; 162 struct bge_softc *bge_sc; 163 int fast_ether_only = FALSE; 164 165 sc = device_get_softc(dev); 166 ma = device_get_ivars(dev); 167 sc->mii_dev = device_get_parent(dev); 168 mii = device_get_softc(sc->mii_dev); 169 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 170 171 sc->mii_inst = mii->mii_instance; 172 sc->mii_phy = ma->mii_phyno; 173 sc->mii_service = brgphy_service; 174 sc->mii_pdata = mii; 175 176 sc->mii_flags |= MIIF_NOISOLATE; 177 mii->mii_instance++; 178 179 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 180 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 181 182 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 183 BMCR_ISO); 184 #if 0 185 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 186 BMCR_LOOP|BMCR_S100); 187 #endif 188 189 brgphy_mii_model = MII_MODEL(ma->mii_id2); 190 brgphy_reset(sc); 191 192 193 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 194 sc->mii_capabilities &= ~BMSR_ANEG; 195 device_printf(dev, " "); 196 mii_add_media(sc); 197 198 /* The 590x chips are 10/100 only. */ 199 200 bge_sc = mii->mii_ifp->if_softc; 201 202 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 203 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 204 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 205 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 206 fast_ether_only = TRUE; 207 208 if (fast_ether_only == FALSE) { 209 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 210 sc->mii_inst), BRGPHY_BMCR_FDX); 211 PRINT(", 1000baseTX"); 212 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 213 IFM_FDX, sc->mii_inst), 0); 214 PRINT("1000baseTX-FDX"); 215 } 216 217 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 218 PRINT("auto"); 219 220 printf("\n"); 221 #undef ADD 222 #undef PRINT 223 224 MIIBUS_MEDIAINIT(sc->mii_dev); 225 return(0); 226 } 227 228 static int 229 brgphy_service(sc, mii, cmd) 230 struct mii_softc *sc; 231 struct mii_data *mii; 232 int cmd; 233 { 234 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 235 int reg, speed, gig; 236 237 switch (cmd) { 238 case MII_POLLSTAT: 239 /* 240 * If we're not polling our PHY instance, just return. 241 */ 242 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 243 return (0); 244 break; 245 246 case MII_MEDIACHG: 247 /* 248 * If the media indicates a different PHY instance, 249 * isolate ourselves. 250 */ 251 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 252 reg = PHY_READ(sc, MII_BMCR); 253 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 254 return (0); 255 } 256 257 /* 258 * If the interface is not up, don't do anything. 259 */ 260 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 261 break; 262 263 brgphy_reset(sc); /* XXX hardware bug work-around */ 264 265 switch (IFM_SUBTYPE(ife->ifm_media)) { 266 case IFM_AUTO: 267 #ifdef foo 268 /* 269 * If we're already in auto mode, just return. 270 */ 271 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 272 return (0); 273 #endif 274 (void) brgphy_mii_phy_auto(sc); 275 break; 276 case IFM_1000_T: 277 speed = BRGPHY_S1000; 278 goto setit; 279 case IFM_100_TX: 280 speed = BRGPHY_S100; 281 goto setit; 282 case IFM_10_T: 283 speed = BRGPHY_S10; 284 setit: 285 brgphy_loop(sc); 286 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 287 speed |= BRGPHY_BMCR_FDX; 288 gig = BRGPHY_1000CTL_AFD; 289 } else { 290 gig = BRGPHY_1000CTL_AHD; 291 } 292 293 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 294 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 295 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 296 297 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 298 break; 299 300 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 301 PHY_WRITE(sc, BRGPHY_MII_BMCR, 302 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 303 304 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 305 break; 306 307 /* 308 * When settning the link manually, one side must 309 * be the master and the other the slave. However 310 * ifmedia doesn't give us a good way to specify 311 * this, so we fake it by using one of the LINK 312 * flags. If LINK0 is set, we program the PHY to 313 * be a master, otherwise it's a slave. 314 */ 315 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 316 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 317 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 318 } else { 319 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 320 gig|BRGPHY_1000CTL_MSE); 321 } 322 break; 323 #ifdef foo 324 case IFM_NONE: 325 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 326 break; 327 #endif 328 case IFM_100_T4: 329 default: 330 return (EINVAL); 331 } 332 break; 333 334 case MII_TICK: 335 /* 336 * If we're not currently selected, just return. 337 */ 338 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 339 return (0); 340 341 /* 342 * Is the interface even up? 343 */ 344 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 345 return (0); 346 347 /* 348 * Only used for autonegotiation. 349 */ 350 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 351 break; 352 353 /* 354 * Check to see if we have link. If we do, we don't 355 * need to restart the autonegotiation process. Read 356 * the BMSR twice in case it's latched. 357 */ 358 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 359 if (reg & BRGPHY_AUXSTS_LINK) 360 break; 361 362 /* 363 * Only retry autonegotiation every 5 seconds. 364 */ 365 if (++sc->mii_ticks <= 5) 366 break; 367 368 sc->mii_ticks = 0; 369 brgphy_mii_phy_auto(sc); 370 return (0); 371 } 372 373 /* Update the media status. */ 374 brgphy_status(sc); 375 376 /* 377 * Callback if something changed. Note that we need to poke 378 * the DSP on the Broadcom PHYs if the media changes. 379 * 380 */ 381 if (sc->mii_media_active != mii->mii_media_active || 382 sc->mii_media_status != mii->mii_media_status || 383 cmd == MII_MEDIACHG) { 384 switch (brgphy_mii_model) { 385 case MII_MODEL_xxBROADCOM_BCM5401: 386 bcm5401_load_dspcode(sc); 387 break; 388 case MII_MODEL_xxBROADCOM_BCM5411: 389 bcm5411_load_dspcode(sc); 390 break; 391 } 392 } 393 mii_phy_update(sc, cmd); 394 return (0); 395 } 396 397 static void 398 brgphy_status(sc) 399 struct mii_softc *sc; 400 { 401 struct mii_data *mii = sc->mii_pdata; 402 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 403 int bmsr, bmcr; 404 405 mii->mii_media_status = IFM_AVALID; 406 mii->mii_media_active = IFM_ETHER; 407 408 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 409 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 410 mii->mii_media_status |= IFM_ACTIVE; 411 412 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 413 414 if (bmcr & BRGPHY_BMCR_LOOP) 415 mii->mii_media_active |= IFM_LOOP; 416 417 if (bmcr & BRGPHY_BMCR_AUTOEN) { 418 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 419 /* Erg, still trying, I guess... */ 420 mii->mii_media_active |= IFM_NONE; 421 return; 422 } 423 424 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 425 BRGPHY_AUXSTS_AN_RES) { 426 case BRGPHY_RES_1000FD: 427 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 428 break; 429 case BRGPHY_RES_1000HD: 430 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 431 break; 432 case BRGPHY_RES_100FD: 433 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 434 break; 435 case BRGPHY_RES_100T4: 436 mii->mii_media_active |= IFM_100_T4; 437 break; 438 case BRGPHY_RES_100HD: 439 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 440 break; 441 case BRGPHY_RES_10FD: 442 mii->mii_media_active |= IFM_10_T | IFM_FDX; 443 break; 444 case BRGPHY_RES_10HD: 445 mii->mii_media_active |= IFM_10_T | IFM_HDX; 446 break; 447 default: 448 mii->mii_media_active |= IFM_NONE; 449 break; 450 } 451 return; 452 } 453 454 mii->mii_media_active = ife->ifm_media; 455 456 return; 457 } 458 459 460 static int 461 brgphy_mii_phy_auto(mii) 462 struct mii_softc *mii; 463 { 464 int ktcr = 0; 465 466 brgphy_loop(mii); 467 brgphy_reset(mii); 468 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 469 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 470 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 471 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 472 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 473 DELAY(1000); 474 PHY_WRITE(mii, BRGPHY_MII_ANAR, 475 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 476 DELAY(1000); 477 PHY_WRITE(mii, BRGPHY_MII_BMCR, 478 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 479 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 480 return (EJUSTRETURN); 481 } 482 483 static void 484 brgphy_loop(struct mii_softc *sc) 485 { 486 u_int32_t bmsr; 487 int i; 488 489 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 490 for (i = 0; i < 15000; i++) { 491 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 492 if (!(bmsr & BRGPHY_BMSR_LINK)) { 493 #if 0 494 device_printf(sc->mii_dev, "looped %d\n", i); 495 #endif 496 break; 497 } 498 DELAY(10); 499 } 500 } 501 502 /* Turn off tap power management on 5401. */ 503 static void 504 bcm5401_load_dspcode(struct mii_softc *sc) 505 { 506 static const struct { 507 int reg; 508 uint16_t val; 509 } dspcode[] = { 510 { BRGPHY_MII_AUXCTL, 0x0c20 }, 511 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 512 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 513 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 514 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 515 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 516 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 517 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 518 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 519 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 520 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 521 { 0, 0 }, 522 }; 523 int i; 524 525 for (i = 0; dspcode[i].reg != 0; i++) 526 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 527 DELAY(40); 528 } 529 530 static void 531 bcm5411_load_dspcode(struct mii_softc *sc) 532 { 533 static const struct { 534 int reg; 535 uint16_t val; 536 } dspcode[] = { 537 { 0x1c, 0x8c23 }, 538 { 0x1c, 0x8ca3 }, 539 { 0x1c, 0x8c23 }, 540 { 0, 0 }, 541 }; 542 int i; 543 544 for (i = 0; dspcode[i].reg != 0; i++) 545 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 546 } 547 548 static void 549 bcm5703_load_dspcode(struct mii_softc *sc) 550 { 551 static const struct { 552 int reg; 553 uint16_t val; 554 } dspcode[] = { 555 { BRGPHY_MII_AUXCTL, 0x0c00 }, 556 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 557 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 558 { 0, 0 }, 559 }; 560 int i; 561 562 for (i = 0; dspcode[i].reg != 0; i++) 563 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 564 } 565 566 static void 567 bcm5704_load_dspcode(struct mii_softc *sc) 568 { 569 static const struct { 570 int reg; 571 u_int16_t val; 572 } dspcode[] = { 573 { 0x1c, 0x8d68 }, 574 { 0x1c, 0x8d68 }, 575 { 0, 0 }, 576 }; 577 int i; 578 579 for (i = 0; dspcode[i].reg != 0; i++) 580 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 581 } 582 583 static void 584 brgphy_reset(struct mii_softc *sc) 585 { 586 u_int32_t val; 587 struct ifnet *ifp; 588 struct bge_softc *bge_sc; 589 590 mii_phy_reset(sc); 591 592 switch (brgphy_mii_model) { 593 case MII_MODEL_xxBROADCOM_BCM5401: 594 bcm5401_load_dspcode(sc); 595 break; 596 case MII_MODEL_xxBROADCOM_BCM5411: 597 bcm5411_load_dspcode(sc); 598 break; 599 case MII_MODEL_xxBROADCOM_BCM5703: 600 bcm5703_load_dspcode(sc); 601 break; 602 case MII_MODEL_xxBROADCOM_BCM5704: 603 bcm5704_load_dspcode(sc); 604 break; 605 } 606 607 ifp = sc->mii_pdata->mii_ifp; 608 bge_sc = ifp->if_softc; 609 610 /* 611 * Don't enable Ethernet@WireSpeed for the 5700 or the 612 * 5705 A1 and A2 chips. Make sure we only do this test 613 * on "bge" NICs, since other drivers may use this same 614 * PHY subdriver. 615 */ 616 if (strcmp(ifp->if_dname, "bge") == 0 && 617 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 618 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 619 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)) 620 return; 621 622 /* Enable Ethernet@WireSpeed. */ 623 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 624 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 625 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 626 627 /* Enable Link LED on Dell boxes */ 628 if (bge_sc->bge_no_3_led) { 629 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 630 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 631 & ~BRGPHY_PHY_EXTCTL_3_LED); 632 } 633 } 634