1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/brgphyreg.h> 56 #include <net/if_arp.h> 57 #include <machine/bus.h> 58 #include <dev/bge/if_bgereg.h> 59 #include <dev/bce/if_bcereg.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 #include "miibus_if.h" 65 66 static int brgphy_probe(device_t); 67 static int brgphy_attach(device_t); 68 69 struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int mii_oui; 72 int mii_model; 73 int mii_rev; 74 int serdes_flags; /* Keeps track of the serdes type used */ 75 #define BRGPHY_5706S 0x0001 76 #define BRGPHY_5708S 0x0002 77 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 78 }; 79 80 static device_method_t brgphy_methods[] = { 81 /* device interface */ 82 DEVMETHOD(device_probe, brgphy_probe), 83 DEVMETHOD(device_attach, brgphy_attach), 84 DEVMETHOD(device_detach, mii_phy_detach), 85 DEVMETHOD(device_shutdown, bus_generic_shutdown), 86 { 0, 0 } 87 }; 88 89 static devclass_t brgphy_devclass; 90 91 static driver_t brgphy_driver = { 92 "brgphy", 93 brgphy_methods, 94 sizeof(struct brgphy_softc) 95 }; 96 97 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 98 99 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 100 static void brgphy_setmedia(struct mii_softc *, int, int); 101 static void brgphy_status(struct mii_softc *); 102 static void brgphy_mii_phy_auto(struct mii_softc *); 103 static void brgphy_reset(struct mii_softc *); 104 static void brgphy_enable_loopback(struct mii_softc *); 105 static void bcm5401_load_dspcode(struct mii_softc *); 106 static void bcm5411_load_dspcode(struct mii_softc *); 107 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 108 static void brgphy_fixup_adc_bug(struct mii_softc *); 109 static void brgphy_fixup_adjust_trim(struct mii_softc *); 110 static void brgphy_fixup_ber_bug(struct mii_softc *); 111 static void brgphy_fixup_crc_bug(struct mii_softc *); 112 static void brgphy_fixup_jitter_bug(struct mii_softc *); 113 static void brgphy_ethernet_wirespeed(struct mii_softc *); 114 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 115 116 static const struct mii_phydesc brgphys[] = { 117 MII_PHY_DESC(xxBROADCOM, BCM5400), 118 MII_PHY_DESC(xxBROADCOM, BCM5401), 119 MII_PHY_DESC(xxBROADCOM, BCM5411), 120 MII_PHY_DESC(xxBROADCOM, BCM5701), 121 MII_PHY_DESC(xxBROADCOM, BCM5703), 122 MII_PHY_DESC(xxBROADCOM, BCM5704), 123 MII_PHY_DESC(xxBROADCOM, BCM5705), 124 MII_PHY_DESC(xxBROADCOM, BCM5706), 125 MII_PHY_DESC(xxBROADCOM, BCM5714), 126 MII_PHY_DESC(xxBROADCOM, BCM5750), 127 MII_PHY_DESC(xxBROADCOM, BCM5752), 128 MII_PHY_DESC(xxBROADCOM, BCM5754), 129 MII_PHY_DESC(xxBROADCOM, BCM5780), 130 MII_PHY_DESC(xxBROADCOM, BCM5708C), 131 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 132 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 133 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), 134 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), 135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), 136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), 137 MII_PHY_END 138 }; 139 140 141 /* Search for our PHY in the list of known PHYs */ 142 static int 143 brgphy_probe(device_t dev) 144 { 145 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 146 } 147 148 /* Attach the PHY to the MII bus */ 149 static int 150 brgphy_attach(device_t dev) 151 { 152 struct brgphy_softc *bsc; 153 struct bge_softc *bge_sc = NULL; 154 struct bce_softc *bce_sc = NULL; 155 struct mii_softc *sc; 156 struct mii_attach_args *ma; 157 struct mii_data *mii; 158 struct ifnet *ifp; 159 int fast_ether; 160 161 bsc = device_get_softc(dev); 162 sc = &bsc->mii_sc; 163 ma = device_get_ivars(dev); 164 sc->mii_dev = device_get_parent(dev); 165 mii = device_get_softc(sc->mii_dev); 166 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 167 168 /* Initialize mii_softc structure */ 169 sc->mii_inst = mii->mii_instance; 170 sc->mii_phy = ma->mii_phyno; 171 sc->mii_service = brgphy_service; 172 sc->mii_pdata = mii; 173 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 174 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 175 mii->mii_instance++; 176 177 /* Initialize brgphy_softc structure */ 178 bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 179 bsc->mii_model = MII_MODEL(ma->mii_id2); 180 bsc->mii_rev = MII_REV(ma->mii_id2); 181 bsc->serdes_flags = 0; 182 183 fast_ether = 0; 184 185 if (bootverbose) 186 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", 187 bsc->mii_oui, bsc->mii_model, bsc->mii_rev); 188 189 /* Handle any special cases based on the PHY ID */ 190 switch (bsc->mii_oui) { 191 case MII_OUI_BROADCOM: 192 break; 193 case MII_OUI_xxBROADCOM: 194 switch (bsc->mii_model) { 195 case MII_MODEL_xxBROADCOM_BCM5706: 196 /* 197 * The 5464 PHY used in the 5706 supports both copper 198 * and fiber interfaces over GMII. Need to check the 199 * shadow registers to see which mode is actually 200 * in effect, and therefore whether we have 5706C or 201 * 5706S. 202 */ 203 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 204 BRGPHY_SHADOW_1C_MODE_CTRL); 205 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 206 BRGPHY_SHADOW_1C_ENA_1000X) { 207 bsc->serdes_flags |= BRGPHY_5706S; 208 sc->mii_flags |= MIIF_HAVEFIBER; 209 } 210 break; 211 } break; 212 case MII_OUI_xxBROADCOM_ALT1: 213 switch (bsc->mii_model) { 214 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: 215 bsc->serdes_flags |= BRGPHY_5708S; 216 sc->mii_flags |= MIIF_HAVEFIBER; 217 break; 218 } break; 219 default: 220 device_printf(dev, "Unrecognized OUI for PHY!\n"); 221 } 222 223 ifp = sc->mii_pdata->mii_ifp; 224 225 /* Find the MAC driver associated with this PHY. */ 226 if (strcmp(ifp->if_dname, "bge") == 0) { 227 bge_sc = ifp->if_softc; 228 } else if (strcmp(ifp->if_dname, "bce") == 0) { 229 bce_sc = ifp->if_softc; 230 } 231 232 /* Todo: Need to add additional controllers such as 5906 & 5787F */ 233 /* The 590x chips are 10/100 only. */ 234 if (bge_sc && 235 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 236 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 237 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) { 238 fast_ether = 1; 239 sc->mii_anegticks = MII_ANEGTICKS; 240 } 241 242 brgphy_reset(sc); 243 244 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 245 if (sc->mii_capabilities & BMSR_EXTSTAT) 246 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 247 device_printf(dev, " "); 248 249 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 250 251 /* Create an instance of Ethernet media. */ 252 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO); 253 254 /* Add the supported media types */ 255 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 256 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), 257 BRGPHY_S10); 258 printf("10baseT, "); 259 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst), 260 BRGPHY_S10 | BRGPHY_BMCR_FDX); 261 printf("10baseT-FDX, "); 262 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), 263 BRGPHY_S100); 264 printf("100baseTX, "); 265 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst), 266 BRGPHY_S100 | BRGPHY_BMCR_FDX); 267 printf("100baseTX-FDX, "); 268 if (fast_ether == 0) { 269 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 270 BRGPHY_S1000); 271 printf("1000baseT, "); 272 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 273 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 274 printf("1000baseT-FDX, "); 275 } 276 } else { 277 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 278 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 279 printf("1000baseSX-FDX, "); 280 /* 2.5G support is a software enabled feature on the 5708S */ 281 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 282 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 283 printf("2500baseSX-FDX, "); 284 } 285 } 286 287 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 288 printf("auto\n"); 289 290 #undef ADD 291 MIIBUS_MEDIAINIT(sc->mii_dev); 292 return (0); 293 } 294 295 static int 296 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 297 { 298 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 299 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 300 int error = 0; 301 int val; 302 303 switch (cmd) { 304 case MII_POLLSTAT: 305 /* If we're not polling our PHY instance, just return. */ 306 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 307 goto brgphy_service_exit; 308 break; 309 case MII_MEDIACHG: 310 /* 311 * If the media indicates a different PHY instance, 312 * isolate ourselves. 313 */ 314 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 315 PHY_WRITE(sc, MII_BMCR, 316 PHY_READ(sc, MII_BMCR) | BMCR_ISO); 317 goto brgphy_service_exit; 318 } 319 320 /* If the interface is not up, don't do anything. */ 321 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 322 break; 323 324 /* Todo: Why is this here? Is it really needed? */ 325 brgphy_reset(sc); /* XXX hardware bug work-around */ 326 327 switch (IFM_SUBTYPE(ife->ifm_media)) { 328 case IFM_AUTO: 329 brgphy_mii_phy_auto(sc); 330 break; 331 case IFM_2500_SX: 332 case IFM_1000_SX: 333 case IFM_1000_T: 334 case IFM_100_TX: 335 case IFM_10_T: 336 brgphy_setmedia(sc, ife->ifm_media, 337 mii->mii_ifp->if_flags & IFF_LINK0); 338 break; 339 default: 340 error = EINVAL; 341 goto brgphy_service_exit; 342 } 343 break; 344 case MII_TICK: 345 /* Bail if we're not currently selected. */ 346 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 347 goto brgphy_service_exit; 348 349 /* Bail if the interface isn't up. */ 350 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 351 goto brgphy_service_exit; 352 353 354 /* Bail if autoneg isn't in process. */ 355 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 356 sc->mii_ticks = 0; 357 break; 358 } 359 360 /* 361 * Check to see if we have link. If we do, we don't 362 * need to restart the autonegotiation process. 363 */ 364 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 365 if (val & BMSR_LINK) { 366 sc->mii_ticks = 0; /* Reset autoneg timer. */ 367 break; 368 } 369 370 #if 0 371 /* Todo: Is this correct? */ 372 /* Announce link loss right after it happens. */ 373 if (sc->mii_ticks++ == 0) 374 break; 375 #endif 376 377 /* Only retry autonegotiation every mii_anegticks seconds. */ 378 if (sc->mii_ticks <= sc->mii_anegticks) 379 goto brgphy_service_exit; 380 381 382 /* Retry autonegotiation */ 383 sc->mii_ticks = 0; 384 brgphy_mii_phy_auto(sc); 385 break; 386 } 387 388 /* Update the media status. */ 389 brgphy_status(sc); 390 391 /* 392 * Callback if something changed. Note that we need to poke 393 * the DSP on the Broadcom PHYs if the media changes. 394 */ 395 if (sc->mii_media_active != mii->mii_media_active || 396 sc->mii_media_status != mii->mii_media_status || 397 cmd == MII_MEDIACHG) { 398 switch (bsc->mii_oui) { 399 case MII_OUI_BROADCOM: 400 break; 401 case MII_OUI_xxBROADCOM: 402 switch (bsc->mii_model) { 403 case MII_MODEL_xxBROADCOM_BCM5400: 404 bcm5401_load_dspcode(sc); 405 break; 406 case MII_MODEL_xxBROADCOM_BCM5401: 407 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 408 bcm5401_load_dspcode(sc); 409 break; 410 case MII_MODEL_xxBROADCOM_BCM5411: 411 bcm5411_load_dspcode(sc); 412 break; 413 } 414 break; 415 case MII_OUI_xxBROADCOM_ALT1: 416 break; 417 } 418 } 419 mii_phy_update(sc, cmd); 420 brgphy_service_exit: 421 return (error); 422 } 423 424 static void 425 brgphy_setmedia(struct mii_softc *sc, int media, int master) 426 { 427 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 428 int bmcr = 0, gig; 429 430 switch (IFM_SUBTYPE(media)) { 431 case IFM_2500_SX: 432 break; 433 case IFM_1000_SX: 434 case IFM_1000_T: 435 bmcr = BRGPHY_S1000; 436 break; 437 case IFM_100_TX: 438 bmcr = BRGPHY_S100; 439 break; 440 case IFM_10_T: 441 default: 442 bmcr = BRGPHY_S10; 443 break; 444 } 445 if ((media & IFM_GMASK) == IFM_FDX) { 446 bmcr |= BRGPHY_BMCR_FDX; 447 gig = BRGPHY_1000CTL_AFD; 448 } else { 449 gig = BRGPHY_1000CTL_AHD; 450 } 451 452 brgphy_enable_loopback(sc); 453 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 454 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 455 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 456 457 if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX)) 458 goto brgphy_setmedia_exit; 459 460 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 461 PHY_WRITE(sc, BRGPHY_MII_BMCR, 462 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 463 464 if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 465 goto brgphy_setmedia_exit; 466 467 /* 468 * When setting the link manually, one side must be the master and 469 * the other the slave. However ifmedia doesn't give us a good way 470 * to specify this, so we fake it by using one of the LINK flags. 471 * If LINK0 is set, we program the PHY to be a master, otherwise 472 * it's a slave. 473 */ 474 if (master) { 475 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 476 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); 477 } else { 478 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 479 gig | BRGPHY_1000CTL_MSE); 480 } 481 brgphy_setmedia_exit: 482 return; 483 } 484 485 /* Set the media status based on the PHY settings. */ 486 /* IFM_FLAG0 = 0 (RX flow control disabled | 1 (enabled) */ 487 /* IFM_FLAG1 = 0 (TX flow control disabled | 1 (enabled) */ 488 static void 489 brgphy_status(struct mii_softc *sc) 490 { 491 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 492 struct mii_data *mii = sc->mii_pdata; 493 int aux, bmcr, bmsr, anar, anlpar, xstat, val; 494 495 496 mii->mii_media_status = IFM_AVALID; 497 mii->mii_media_active = IFM_ETHER; 498 499 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 500 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 501 anar = PHY_READ(sc, BRGPHY_MII_ANAR); 502 anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR); 503 504 /* Loopback is enabled. */ 505 if (bmcr & BRGPHY_BMCR_LOOP) { 506 507 mii->mii_media_active |= IFM_LOOP; 508 } 509 510 /* Autoneg is still in progress. */ 511 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 512 (bmsr & BRGPHY_BMSR_ACOMP) == 0) { 513 /* Erg, still trying, I guess... */ 514 mii->mii_media_active |= IFM_NONE; 515 goto brgphy_status_exit; 516 } 517 518 /* Autoneg is enabled and complete, link should be up. */ 519 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 520 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 521 522 /* If copper link is up, get the negotiated speed/duplex. */ 523 if (aux & BRGPHY_AUXSTS_LINK) { 524 mii->mii_media_status |= IFM_ACTIVE; 525 switch (aux & BRGPHY_AUXSTS_AN_RES) { 526 case BRGPHY_RES_1000FD: 527 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 528 case BRGPHY_RES_1000HD: 529 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 530 case BRGPHY_RES_100FD: 531 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 532 case BRGPHY_RES_100T4: 533 mii->mii_media_active |= IFM_100_T4; break; 534 case BRGPHY_RES_100HD: 535 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 536 case BRGPHY_RES_10FD: 537 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 538 case BRGPHY_RES_10HD: 539 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 540 default: 541 mii->mii_media_active |= IFM_NONE; break; 542 } 543 } 544 } else { 545 /* If serdes link is up, get the negotiated speed/duplex. */ 546 if (bmsr & BRGPHY_BMSR_LINK) { 547 mii->mii_media_status |= IFM_ACTIVE; 548 } 549 550 /* Check the link speed/duplex based on the PHY type. */ 551 if (bsc->serdes_flags & BRGPHY_5706S) { 552 mii->mii_media_active |= IFM_1000_SX; 553 554 /* If autoneg enabled, read negotiated duplex settings */ 555 if (bmcr & BRGPHY_BMCR_AUTOEN) { 556 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 557 if (val & BRGPHY_SERDES_ANAR_FDX) 558 mii->mii_media_active |= IFM_FDX; 559 else 560 mii->mii_media_active |= IFM_HDX; 561 } 562 563 } else if (bsc->serdes_flags & BRGPHY_5708S) { 564 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 565 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 566 567 /* Todo: Create #defines for hard coded values */ 568 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 569 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 570 mii->mii_media_active |= IFM_10_FL; break; 571 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 572 mii->mii_media_active |= IFM_100_FX; break; 573 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 574 mii->mii_media_active |= IFM_1000_SX; break; 575 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 576 mii->mii_media_active |= IFM_2500_SX; break; 577 } 578 579 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 580 mii->mii_media_active |= IFM_FDX; 581 else 582 mii->mii_media_active |= IFM_HDX; 583 } 584 } 585 586 #if 0 587 /* Todo: Change bge/bce to use these settings. */ 588 589 /* Fetch flow control settings from the PHY */ 590 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 591 /* Set FLAG0 is RX is enabled and FLAG1 if TX is enabled */ 592 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) { 593 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; 594 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) && 595 (anlpar & BRPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 596 mii->mii_media_active |= IFM_FLAG1; 597 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) && 598 !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 599 mii->mii_media_active |= IFM_FLAG0; 600 } 601 } 602 /* Todo: Add support for fiber settings too. */ 603 #endif 604 605 606 brgphy_status_exit: 607 return; 608 } 609 610 static void 611 brgphy_mii_phy_auto(struct mii_softc *sc) 612 { 613 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 614 int ktcr = 0; 615 616 brgphy_reset(sc); 617 618 /* Enable flow control in the advertisement register. */ 619 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 620 /* Pause capability advertisement (pause capable & asymmetric) */ 621 PHY_WRITE(sc, BRGPHY_MII_ANAR, 622 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA | 623 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC); 624 } else { 625 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX | 626 BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE); 627 } 628 629 /* Enable speed in the 1000baseT control register */ 630 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 631 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 632 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 633 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 634 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 635 636 /* Start autonegotiation */ 637 PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 638 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 639 640 } 641 642 /* Enable loopback to force the link down. */ 643 static void 644 brgphy_enable_loopback(struct mii_softc *sc) 645 { 646 int i; 647 648 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 649 for (i = 0; i < 15000; i++) { 650 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 651 break; 652 DELAY(10); 653 } 654 } 655 656 /* Turn off tap power management on 5401. */ 657 static void 658 bcm5401_load_dspcode(struct mii_softc *sc) 659 { 660 static const struct { 661 int reg; 662 uint16_t val; 663 } dspcode[] = { 664 { BRGPHY_MII_AUXCTL, 0x0c20 }, 665 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 666 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 667 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 668 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 669 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 670 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 671 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 672 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 673 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 674 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 675 { 0, 0 }, 676 }; 677 int i; 678 679 for (i = 0; dspcode[i].reg != 0; i++) 680 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 681 DELAY(40); 682 } 683 684 static void 685 bcm5411_load_dspcode(struct mii_softc *sc) 686 { 687 static const struct { 688 int reg; 689 uint16_t val; 690 } dspcode[] = { 691 { 0x1c, 0x8c23 }, 692 { 0x1c, 0x8ca3 }, 693 { 0x1c, 0x8c23 }, 694 { 0, 0 }, 695 }; 696 int i; 697 698 for (i = 0; dspcode[i].reg != 0; i++) 699 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 700 } 701 702 static void 703 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 704 { 705 static const struct { 706 int reg; 707 uint16_t val; 708 } dspcode[] = { 709 { 0x1c, 0x8d68 }, 710 { 0x1c, 0x8d68 }, 711 { 0, 0 }, 712 }; 713 int i; 714 715 for (i = 0; dspcode[i].reg != 0; i++) 716 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 717 } 718 719 static void 720 brgphy_fixup_adc_bug(struct mii_softc *sc) 721 { 722 static const struct { 723 int reg; 724 uint16_t val; 725 } dspcode[] = { 726 { BRGPHY_MII_AUXCTL, 0x0c00 }, 727 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 728 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 729 { 0, 0 }, 730 }; 731 int i; 732 733 for (i = 0; dspcode[i].reg != 0; i++) 734 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 735 } 736 737 static void 738 brgphy_fixup_adjust_trim(struct mii_softc *sc) 739 { 740 static const struct { 741 int reg; 742 uint16_t val; 743 } dspcode[] = { 744 { BRGPHY_MII_AUXCTL, 0x0c00 }, 745 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 746 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 747 { BRGPHY_MII_TEST1, 0x0014 }, 748 { BRGPHY_MII_AUXCTL, 0x0400 }, 749 { 0, 0 }, 750 }; 751 int i; 752 753 for (i = 0; dspcode[i].reg != 0; i++) 754 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 755 } 756 757 static void 758 brgphy_fixup_ber_bug(struct mii_softc *sc) 759 { 760 static const struct { 761 int reg; 762 uint16_t val; 763 } dspcode[] = { 764 { BRGPHY_MII_AUXCTL, 0x0c00 }, 765 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 766 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 767 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 768 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 769 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 770 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 771 { BRGPHY_MII_AUXCTL, 0x0400 }, 772 { 0, 0 }, 773 }; 774 int i; 775 776 for (i = 0; dspcode[i].reg != 0; i++) 777 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 778 } 779 780 static void 781 brgphy_fixup_crc_bug(struct mii_softc *sc) 782 { 783 static const struct { 784 int reg; 785 uint16_t val; 786 } dspcode[] = { 787 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 788 { 0x1c, 0x8c68 }, 789 { 0x1c, 0x8d68 }, 790 { 0x1c, 0x8c68 }, 791 { 0, 0 }, 792 }; 793 int i; 794 795 for (i = 0; dspcode[i].reg != 0; i++) 796 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 797 } 798 799 static void 800 brgphy_fixup_jitter_bug(struct mii_softc *sc) 801 { 802 static const struct { 803 int reg; 804 uint16_t val; 805 } dspcode[] = { 806 { BRGPHY_MII_AUXCTL, 0x0c00 }, 807 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 808 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 809 { BRGPHY_MII_AUXCTL, 0x0400 }, 810 { 0, 0 }, 811 }; 812 int i; 813 814 for (i = 0; dspcode[i].reg != 0; i++) 815 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 816 } 817 818 static void 819 brgphy_ethernet_wirespeed(struct mii_softc *sc) 820 { 821 uint32_t val; 822 823 /* Enable Ethernet@WireSpeed. */ 824 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 825 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 826 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 827 } 828 829 static void 830 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 831 { 832 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 833 uint32_t val; 834 835 /* Set or clear jumbo frame settings in the PHY. */ 836 if (mtu > ETHER_MAX_LEN) { 837 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 838 /* BCM5401 PHY cannot read-modify-write. */ 839 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 840 } else { 841 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 842 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 843 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 844 val | BRGPHY_AUXCTL_LONG_PKT); 845 } 846 847 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 848 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 849 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 850 } else { 851 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 852 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 853 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 854 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 855 856 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 857 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 858 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 859 } 860 } 861 862 static void 863 brgphy_reset(struct mii_softc *sc) 864 { 865 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 866 struct bge_softc *bge_sc = NULL; 867 struct bce_softc *bce_sc = NULL; 868 struct ifnet *ifp; 869 870 mii_phy_reset(sc); 871 872 /* Handle any PHY specific procedures to finish the reset. */ 873 switch (bsc->mii_oui) { 874 case MII_OUI_BROADCOM: 875 break; 876 case MII_OUI_xxBROADCOM: 877 switch (bsc->mii_model) { 878 case MII_MODEL_xxBROADCOM_BCM5400: 879 bcm5401_load_dspcode(sc); 880 break; 881 case MII_MODEL_xxBROADCOM_BCM5401: 882 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 883 bcm5401_load_dspcode(sc); 884 break; 885 case MII_MODEL_xxBROADCOM_BCM5411: 886 bcm5411_load_dspcode(sc); 887 break; 888 } 889 break; 890 case MII_OUI_xxBROADCOM_ALT1: 891 break; 892 } 893 894 ifp = sc->mii_pdata->mii_ifp; 895 896 /* Find the driver associated with this PHY. */ 897 if (strcmp(ifp->if_dname, "bge") == 0) { 898 bge_sc = ifp->if_softc; 899 } else if (strcmp(ifp->if_dname, "bce") == 0) { 900 bce_sc = ifp->if_softc; 901 } 902 903 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 904 if (bge_sc) { 905 /* Fix up various bugs */ 906 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) 907 brgphy_fixup_5704_a0_bug(sc); 908 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) 909 brgphy_fixup_adc_bug(sc); 910 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) 911 brgphy_fixup_adjust_trim(sc); 912 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) 913 brgphy_fixup_ber_bug(sc); 914 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) 915 brgphy_fixup_crc_bug(sc); 916 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) 917 brgphy_fixup_jitter_bug(sc); 918 919 brgphy_jumbo_settings(sc, ifp->if_mtu); 920 921 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED) 922 brgphy_ethernet_wirespeed(sc); 923 924 /* Enable Link LED on Dell boxes */ 925 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { 926 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 927 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 928 ~BRGPHY_PHY_EXTCTL_3_LED); 929 } 930 /* Handle any bce (NetXtreme II) workarounds. */ 931 } else if (bce_sc) { 932 933 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 934 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 935 936 /* Store autoneg capabilities/results in digital block (Page 0) */ 937 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 938 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 939 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 940 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 941 942 /* Enable fiber mode and autodetection */ 943 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 944 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 945 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 946 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 947 948 /* Enable parallel detection */ 949 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 950 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 951 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 952 953 /* Advertise 2.5G support through next page during autoneg */ 954 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 955 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 956 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 957 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 958 959 /* Increase TX signal amplitude */ 960 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 961 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 962 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 963 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 964 BRGPHY_5708S_TX_MISC_PG5); 965 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 966 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 967 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 968 BRGPHY_5708S_DIG_PG0); 969 } 970 971 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 972 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 973 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 974 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 975 BRGPHY_5708S_TX_MISC_PG5); 976 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 977 bce_sc->bce_port_hw_cfg & 978 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 979 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 980 BRGPHY_5708S_DIG_PG0); 981 } 982 } else { 983 brgphy_fixup_ber_bug(sc); 984 brgphy_jumbo_settings(sc, ifp->if_mtu); 985 brgphy_ethernet_wirespeed(sc); 986 } 987 988 } 989 } 990 991