1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2000 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/bus.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/ethernet.h> 53 #include <net/if_media.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include "miidevs.h" 58 59 #include <dev/mii/brgphyreg.h> 60 #include <net/if_arp.h> 61 #include <machine/bus.h> 62 #include <dev/bge/if_bgereg.h> 63 #include <dev/bce/if_bcereg.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include "miibus_if.h" 69 70 static int brgphy_probe(device_t); 71 static int brgphy_attach(device_t); 72 73 struct brgphy_softc { 74 struct mii_softc mii_sc; 75 int serdes_flags; /* Keeps track of the serdes type used */ 76 #define BRGPHY_5706S 0x0001 77 #define BRGPHY_5708S 0x0002 78 #define BRGPHY_NOANWAIT 0x0004 79 #define BRGPHY_5709S 0x0008 80 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 81 }; 82 83 static device_method_t brgphy_methods[] = { 84 /* device interface */ 85 DEVMETHOD(device_probe, brgphy_probe), 86 DEVMETHOD(device_attach, brgphy_attach), 87 DEVMETHOD(device_detach, mii_phy_detach), 88 DEVMETHOD(device_shutdown, bus_generic_shutdown), 89 DEVMETHOD_END 90 }; 91 92 static devclass_t brgphy_devclass; 93 94 static driver_t brgphy_driver = { 95 "brgphy", 96 brgphy_methods, 97 sizeof(struct brgphy_softc) 98 }; 99 100 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 101 102 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 103 static void brgphy_setmedia(struct mii_softc *, int); 104 static void brgphy_status(struct mii_softc *); 105 static void brgphy_mii_phy_auto(struct mii_softc *, int); 106 static void brgphy_reset(struct mii_softc *); 107 static void brgphy_enable_loopback(struct mii_softc *); 108 static void bcm5401_load_dspcode(struct mii_softc *); 109 static void bcm5411_load_dspcode(struct mii_softc *); 110 static void bcm54k2_load_dspcode(struct mii_softc *); 111 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 112 static void brgphy_fixup_adc_bug(struct mii_softc *); 113 static void brgphy_fixup_adjust_trim(struct mii_softc *); 114 static void brgphy_fixup_ber_bug(struct mii_softc *); 115 static void brgphy_fixup_crc_bug(struct mii_softc *); 116 static void brgphy_fixup_jitter_bug(struct mii_softc *); 117 static void brgphy_ethernet_wirespeed(struct mii_softc *); 118 static void brgphy_bcm54xx_clock_delay(struct mii_softc *); 119 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 120 121 static const struct mii_phydesc brgphys[] = { 122 MII_PHY_DESC(BROADCOM, BCM5400), 123 MII_PHY_DESC(BROADCOM, BCM5401), 124 MII_PHY_DESC(BROADCOM, BCM5402), 125 MII_PHY_DESC(BROADCOM, BCM5411), 126 MII_PHY_DESC(BROADCOM, BCM5404), 127 MII_PHY_DESC(BROADCOM, BCM5424), 128 MII_PHY_DESC(BROADCOM, BCM54K2), 129 MII_PHY_DESC(BROADCOM, BCM5701), 130 MII_PHY_DESC(BROADCOM, BCM5703), 131 MII_PHY_DESC(BROADCOM, BCM5704), 132 MII_PHY_DESC(BROADCOM, BCM5705), 133 MII_PHY_DESC(BROADCOM, BCM5706), 134 MII_PHY_DESC(BROADCOM, BCM5714), 135 MII_PHY_DESC(BROADCOM, BCM5421), 136 MII_PHY_DESC(BROADCOM, BCM5750), 137 MII_PHY_DESC(BROADCOM, BCM5752), 138 MII_PHY_DESC(BROADCOM, BCM5780), 139 MII_PHY_DESC(BROADCOM, BCM5708C), 140 MII_PHY_DESC(BROADCOM, BCM5466), 141 MII_PHY_DESC(BROADCOM2, BCM5478), 142 MII_PHY_DESC(BROADCOM2, BCM5488), 143 MII_PHY_DESC(BROADCOM2, BCM5482), 144 MII_PHY_DESC(BROADCOM2, BCM5708S), 145 MII_PHY_DESC(BROADCOM2, BCM5709C), 146 MII_PHY_DESC(BROADCOM2, BCM5709S), 147 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 148 MII_PHY_DESC(BROADCOM2, BCM5722), 149 MII_PHY_DESC(BROADCOM2, BCM5755), 150 MII_PHY_DESC(BROADCOM2, BCM5754), 151 MII_PHY_DESC(BROADCOM2, BCM5761), 152 MII_PHY_DESC(BROADCOM2, BCM5784), 153 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 154 MII_PHY_DESC(BROADCOM2, BCM5785), 155 #endif 156 MII_PHY_DESC(BROADCOM3, BCM54618SE), 157 MII_PHY_DESC(BROADCOM3, BCM5717C), 158 MII_PHY_DESC(BROADCOM3, BCM5719C), 159 MII_PHY_DESC(BROADCOM3, BCM5720C), 160 MII_PHY_DESC(BROADCOM3, BCM57765), 161 MII_PHY_DESC(BROADCOM3, BCM57780), 162 MII_PHY_DESC(BROADCOM4, BCM54213PE), 163 MII_PHY_DESC(BROADCOM4, BCM5725C), 164 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 165 MII_PHY_END 166 }; 167 168 static const struct mii_phy_funcs brgphy_funcs = { 169 brgphy_service, 170 brgphy_status, 171 brgphy_reset 172 }; 173 174 static const struct hs21_type { 175 const uint32_t id; 176 const char *prod; 177 } hs21_type_lists[] = { 178 { 0x57081021, "IBM eServer BladeCenter HS21" }, 179 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" }, 180 }; 181 182 static int 183 detect_hs21(struct bce_softc *bce_sc) 184 { 185 char *sysenv; 186 int found, i; 187 188 found = 0; 189 sysenv = kern_getenv("smbios.system.product"); 190 if (sysenv == NULL) 191 return (found); 192 for (i = 0; i < nitems(hs21_type_lists); i++) { 193 if (bce_sc->bce_chipid == hs21_type_lists[i].id && 194 strncmp(sysenv, hs21_type_lists[i].prod, 195 strlen(hs21_type_lists[i].prod)) == 0) { 196 found++; 197 break; 198 } 199 } 200 freeenv(sysenv); 201 return (found); 202 } 203 204 /* Search for our PHY in the list of known PHYs */ 205 static int 206 brgphy_probe(device_t dev) 207 { 208 209 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 210 } 211 212 /* Attach the PHY to the MII bus */ 213 static int 214 brgphy_attach(device_t dev) 215 { 216 struct brgphy_softc *bsc; 217 struct bge_softc *bge_sc = NULL; 218 struct bce_softc *bce_sc = NULL; 219 struct mii_softc *sc; 220 221 bsc = device_get_softc(dev); 222 sc = &bsc->mii_sc; 223 224 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 225 &brgphy_funcs, 0); 226 227 bsc->serdes_flags = 0; 228 229 /* Find the MAC driver associated with this PHY. */ 230 if (mii_dev_mac_match(dev, "bge")) 231 bge_sc = mii_dev_mac_softc(dev); 232 else if (mii_dev_mac_match(dev, "bce")) 233 bce_sc = mii_dev_mac_softc(dev); 234 235 /* Handle any special cases based on the PHY ID */ 236 switch (sc->mii_mpd_oui) { 237 case MII_OUI_BROADCOM: 238 switch (sc->mii_mpd_model) { 239 case MII_MODEL_BROADCOM_BCM5706: 240 case MII_MODEL_BROADCOM_BCM5714: 241 /* 242 * The 5464 PHY used in the 5706 supports both copper 243 * and fiber interfaces over GMII. Need to check the 244 * shadow registers to see which mode is actually 245 * in effect, and therefore whether we have 5706C or 246 * 5706S. 247 */ 248 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 249 BRGPHY_SHADOW_1C_MODE_CTRL); 250 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 251 BRGPHY_SHADOW_1C_ENA_1000X) { 252 bsc->serdes_flags |= BRGPHY_5706S; 253 sc->mii_flags |= MIIF_HAVEFIBER; 254 } 255 break; 256 } 257 break; 258 case MII_OUI_BROADCOM2: 259 switch (sc->mii_mpd_model) { 260 case MII_MODEL_BROADCOM2_BCM5708S: 261 bsc->serdes_flags |= BRGPHY_5708S; 262 sc->mii_flags |= MIIF_HAVEFIBER; 263 break; 264 case MII_MODEL_BROADCOM2_BCM5709S: 265 /* 266 * XXX 267 * 5720S and 5709S shares the same PHY id. 268 * Assume 5720S PHY if parent device is bge(4). 269 */ 270 if (bge_sc != NULL) 271 bsc->serdes_flags |= BRGPHY_5708S; 272 else 273 bsc->serdes_flags |= BRGPHY_5709S; 274 sc->mii_flags |= MIIF_HAVEFIBER; 275 break; 276 } 277 break; 278 } 279 280 PHY_RESET(sc); 281 282 /* Read the PHY's capabilities. */ 283 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 284 if (sc->mii_capabilities & BMSR_EXTSTAT) 285 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 286 device_printf(dev, " "); 287 288 /* Add the supported media types */ 289 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 290 mii_phy_add_media(sc); 291 printf("\n"); 292 } else { 293 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 294 ifmedia_add(&sc->mii_pdata->mii_media, 295 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 296 0, NULL); 297 printf("1000baseSX-FDX, "); 298 /* 299 * 2.5G support is a software enabled feature 300 * on the 5708S and 5709S. 301 */ 302 if (bce_sc && (bce_sc->bce_phy_flags & 303 BCE_PHY_2_5G_CAPABLE_FLAG)) { 304 ifmedia_add(&sc->mii_pdata->mii_media, 305 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, 306 sc->mii_inst), 0, NULL); 307 printf("2500baseSX-FDX, "); 308 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 309 (detect_hs21(bce_sc) != 0)) { 310 /* 311 * There appears to be certain silicon revision 312 * in IBM HS21 blades that is having issues with 313 * this driver wating for the auto-negotiation to 314 * complete. This happens with a specific chip id 315 * only and when the 1000baseSX-FDX is the only 316 * mode. Workaround this issue since it's unlikely 317 * to be ever addressed. 318 */ 319 printf("auto-neg workaround, "); 320 bsc->serdes_flags |= BRGPHY_NOANWAIT; 321 } 322 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER, 323 IFM_AUTO, 0, sc->mii_inst), 0, NULL); 324 printf("auto\n"); 325 } 326 327 MIIBUS_MEDIAINIT(sc->mii_dev); 328 return (0); 329 } 330 331 static int 332 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 333 { 334 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 335 int val; 336 337 switch (cmd) { 338 case MII_POLLSTAT: 339 break; 340 case MII_MEDIACHG: 341 /* Todo: Why is this here? Is it really needed? */ 342 PHY_RESET(sc); /* XXX hardware bug work-around */ 343 344 switch (IFM_SUBTYPE(ife->ifm_media)) { 345 case IFM_AUTO: 346 brgphy_mii_phy_auto(sc, ife->ifm_media); 347 break; 348 case IFM_2500_SX: 349 case IFM_1000_SX: 350 case IFM_1000_T: 351 case IFM_100_TX: 352 case IFM_10_T: 353 brgphy_setmedia(sc, ife->ifm_media); 354 break; 355 default: 356 return (EINVAL); 357 } 358 break; 359 case MII_TICK: 360 /* Bail if autoneg isn't in process. */ 361 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 362 sc->mii_ticks = 0; 363 break; 364 } 365 366 /* 367 * Check to see if we have link. If we do, we don't 368 * need to restart the autonegotiation process. 369 */ 370 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 371 if (val & BMSR_LINK) { 372 sc->mii_ticks = 0; /* Reset autoneg timer. */ 373 break; 374 } 375 376 /* Announce link loss right after it happens. */ 377 if (sc->mii_ticks++ == 0) 378 break; 379 380 /* Only retry autonegotiation every mii_anegticks seconds. */ 381 if (sc->mii_ticks <= sc->mii_anegticks) 382 break; 383 384 /* Retry autonegotiation */ 385 sc->mii_ticks = 0; 386 brgphy_mii_phy_auto(sc, ife->ifm_media); 387 break; 388 } 389 390 /* Update the media status. */ 391 PHY_STATUS(sc); 392 393 /* 394 * Callback if something changed. Note that we need to poke 395 * the DSP on the Broadcom PHYs if the media changes. 396 */ 397 if (sc->mii_media_active != mii->mii_media_active || 398 sc->mii_media_status != mii->mii_media_status || 399 cmd == MII_MEDIACHG) { 400 switch (sc->mii_mpd_oui) { 401 case MII_OUI_BROADCOM: 402 switch (sc->mii_mpd_model) { 403 case MII_MODEL_BROADCOM_BCM5400: 404 bcm5401_load_dspcode(sc); 405 break; 406 case MII_MODEL_BROADCOM_BCM5401: 407 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 408 bcm5401_load_dspcode(sc); 409 break; 410 case MII_MODEL_BROADCOM_BCM5411: 411 bcm5411_load_dspcode(sc); 412 break; 413 case MII_MODEL_BROADCOM_BCM54K2: 414 bcm54k2_load_dspcode(sc); 415 break; 416 } 417 break; 418 case MII_OUI_BROADCOM4: 419 switch (sc->mii_mpd_model) { 420 case MII_MODEL_BROADCOM4_BCM54213PE: 421 brgphy_bcm54xx_clock_delay(sc); 422 break; 423 } 424 } 425 } 426 mii_phy_update(sc, cmd); 427 return (0); 428 } 429 430 /****************************************************************************/ 431 /* Sets the PHY link speed. */ 432 /* */ 433 /* Returns: */ 434 /* None */ 435 /****************************************************************************/ 436 static void 437 brgphy_setmedia(struct mii_softc *sc, int media) 438 { 439 int bmcr = 0, gig; 440 441 switch (IFM_SUBTYPE(media)) { 442 case IFM_2500_SX: 443 break; 444 case IFM_1000_SX: 445 case IFM_1000_T: 446 bmcr = BRGPHY_S1000; 447 break; 448 case IFM_100_TX: 449 bmcr = BRGPHY_S100; 450 break; 451 case IFM_10_T: 452 default: 453 bmcr = BRGPHY_S10; 454 break; 455 } 456 457 if ((media & IFM_FDX) != 0) { 458 bmcr |= BRGPHY_BMCR_FDX; 459 gig = BRGPHY_1000CTL_AFD; 460 } else { 461 gig = BRGPHY_1000CTL_AHD; 462 } 463 464 /* Force loopback to disconnect PHY from Ethernet medium. */ 465 brgphy_enable_loopback(sc); 466 467 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 468 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 469 470 if (IFM_SUBTYPE(media) != IFM_1000_T && 471 IFM_SUBTYPE(media) != IFM_1000_SX) { 472 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 473 return; 474 } 475 476 if (IFM_SUBTYPE(media) == IFM_1000_T) { 477 gig |= BRGPHY_1000CTL_MSE; 478 if ((media & IFM_ETH_MASTER) != 0) 479 gig |= BRGPHY_1000CTL_MSC; 480 } 481 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 482 PHY_WRITE(sc, BRGPHY_MII_BMCR, 483 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 484 } 485 486 /****************************************************************************/ 487 /* Set the media status based on the PHY settings. */ 488 /* */ 489 /* Returns: */ 490 /* None */ 491 /****************************************************************************/ 492 static void 493 brgphy_status(struct mii_softc *sc) 494 { 495 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 496 struct mii_data *mii = sc->mii_pdata; 497 int aux, bmcr, bmsr, val, xstat; 498 u_int flowstat; 499 500 mii->mii_media_status = IFM_AVALID; 501 mii->mii_media_active = IFM_ETHER; 502 503 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 504 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 505 506 if (bmcr & BRGPHY_BMCR_LOOP) { 507 mii->mii_media_active |= IFM_LOOP; 508 } 509 510 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 511 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 512 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 513 /* Erg, still trying, I guess... */ 514 mii->mii_media_active |= IFM_NONE; 515 return; 516 } 517 518 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 519 /* 520 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 521 * wedges at least the PHY of BCM5704 (but not others). 522 */ 523 flowstat = mii_phy_flowstatus(sc); 524 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 525 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 526 527 /* If copper link is up, get the negotiated speed/duplex. */ 528 if (aux & BRGPHY_AUXSTS_LINK) { 529 mii->mii_media_status |= IFM_ACTIVE; 530 switch (aux & BRGPHY_AUXSTS_AN_RES) { 531 case BRGPHY_RES_1000FD: 532 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 533 case BRGPHY_RES_1000HD: 534 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 535 case BRGPHY_RES_100FD: 536 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 537 case BRGPHY_RES_100T4: 538 mii->mii_media_active |= IFM_100_T4; break; 539 case BRGPHY_RES_100HD: 540 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 541 case BRGPHY_RES_10FD: 542 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 543 case BRGPHY_RES_10HD: 544 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 545 default: 546 mii->mii_media_active |= IFM_NONE; break; 547 } 548 549 if ((mii->mii_media_active & IFM_FDX) != 0) 550 mii->mii_media_active |= flowstat; 551 552 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 553 (xstat & BRGPHY_1000STS_MSR) != 0) 554 mii->mii_media_active |= IFM_ETH_MASTER; 555 } 556 } else { 557 /* Todo: Add support for flow control. */ 558 /* If serdes link is up, get the negotiated speed/duplex. */ 559 if (bmsr & BRGPHY_BMSR_LINK) { 560 mii->mii_media_status |= IFM_ACTIVE; 561 } 562 563 /* Check the link speed/duplex based on the PHY type. */ 564 if (bsc->serdes_flags & BRGPHY_5706S) { 565 mii->mii_media_active |= IFM_1000_SX; 566 567 /* If autoneg enabled, read negotiated duplex settings */ 568 if (bmcr & BRGPHY_BMCR_AUTOEN) { 569 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 570 if (val & BRGPHY_SERDES_ANAR_FDX) 571 mii->mii_media_active |= IFM_FDX; 572 else 573 mii->mii_media_active |= IFM_HDX; 574 } 575 } else if (bsc->serdes_flags & BRGPHY_5708S) { 576 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 577 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 578 579 /* Check for MRBE auto-negotiated speed results. */ 580 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 581 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 582 mii->mii_media_active |= IFM_10_FL; break; 583 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 584 mii->mii_media_active |= IFM_100_FX; break; 585 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 586 mii->mii_media_active |= IFM_1000_SX; break; 587 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 588 mii->mii_media_active |= IFM_2500_SX; break; 589 } 590 591 /* Check for MRBE auto-negotiated duplex results. */ 592 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 593 mii->mii_media_active |= IFM_FDX; 594 else 595 mii->mii_media_active |= IFM_HDX; 596 } else if (bsc->serdes_flags & BRGPHY_5709S) { 597 /* Select GP Status Block of the AN MMD, get autoneg results. */ 598 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 599 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 600 601 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 602 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 603 604 /* Check for MRBE auto-negotiated speed results. */ 605 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 606 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 607 mii->mii_media_active |= IFM_10_FL; break; 608 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 609 mii->mii_media_active |= IFM_100_FX; break; 610 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 611 mii->mii_media_active |= IFM_1000_SX; break; 612 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 613 mii->mii_media_active |= IFM_2500_SX; break; 614 } 615 616 /* Check for MRBE auto-negotiated duplex results. */ 617 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 618 mii->mii_media_active |= IFM_FDX; 619 else 620 mii->mii_media_active |= IFM_HDX; 621 } 622 } 623 } 624 625 static void 626 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 627 { 628 int anar, ktcr = 0; 629 630 PHY_RESET(sc); 631 632 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 633 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 634 if ((media & IFM_FLOW) != 0 || 635 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 636 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 637 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 638 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 639 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 640 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 641 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 642 PHY_READ(sc, BRGPHY_MII_1000CTL); 643 } else { 644 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 645 if ((media & IFM_FLOW) != 0 || 646 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 647 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 648 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 649 } 650 651 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 652 BRGPHY_BMCR_STARTNEG); 653 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 654 } 655 656 /* Enable loopback to force the link down. */ 657 static void 658 brgphy_enable_loopback(struct mii_softc *sc) 659 { 660 int i; 661 662 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 663 for (i = 0; i < 15000; i++) { 664 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 665 break; 666 DELAY(10); 667 } 668 } 669 670 /* Turn off tap power management on 5401. */ 671 static void 672 bcm5401_load_dspcode(struct mii_softc *sc) 673 { 674 static const struct { 675 int reg; 676 uint16_t val; 677 } dspcode[] = { 678 { BRGPHY_MII_AUXCTL, 0x0c20 }, 679 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 680 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 681 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 682 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 683 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 684 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 685 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 686 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 687 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 688 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 689 { 0, 0 }, 690 }; 691 int i; 692 693 for (i = 0; dspcode[i].reg != 0; i++) 694 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 695 DELAY(40); 696 } 697 698 static void 699 bcm5411_load_dspcode(struct mii_softc *sc) 700 { 701 static const struct { 702 int reg; 703 uint16_t val; 704 } dspcode[] = { 705 { 0x1c, 0x8c23 }, 706 { 0x1c, 0x8ca3 }, 707 { 0x1c, 0x8c23 }, 708 { 0, 0 }, 709 }; 710 int i; 711 712 for (i = 0; dspcode[i].reg != 0; i++) 713 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 714 } 715 716 void 717 bcm54k2_load_dspcode(struct mii_softc *sc) 718 { 719 static const struct { 720 int reg; 721 uint16_t val; 722 } dspcode[] = { 723 { 4, 0x01e1 }, 724 { 9, 0x0300 }, 725 { 0, 0 }, 726 }; 727 int i; 728 729 for (i = 0; dspcode[i].reg != 0; i++) 730 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 731 732 } 733 734 static void 735 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 736 { 737 static const struct { 738 int reg; 739 uint16_t val; 740 } dspcode[] = { 741 { 0x1c, 0x8d68 }, 742 { 0x1c, 0x8d68 }, 743 { 0, 0 }, 744 }; 745 int i; 746 747 for (i = 0; dspcode[i].reg != 0; i++) 748 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 749 } 750 751 static void 752 brgphy_fixup_adc_bug(struct mii_softc *sc) 753 { 754 static const struct { 755 int reg; 756 uint16_t val; 757 } dspcode[] = { 758 { BRGPHY_MII_AUXCTL, 0x0c00 }, 759 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 760 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 761 { 0, 0 }, 762 }; 763 int i; 764 765 for (i = 0; dspcode[i].reg != 0; i++) 766 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 767 } 768 769 static void 770 brgphy_fixup_adjust_trim(struct mii_softc *sc) 771 { 772 static const struct { 773 int reg; 774 uint16_t val; 775 } dspcode[] = { 776 { BRGPHY_MII_AUXCTL, 0x0c00 }, 777 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 778 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 779 { BRGPHY_MII_TEST1, 0x0014 }, 780 { BRGPHY_MII_AUXCTL, 0x0400 }, 781 { 0, 0 }, 782 }; 783 int i; 784 785 for (i = 0; dspcode[i].reg != 0; i++) 786 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 787 } 788 789 static void 790 brgphy_fixup_ber_bug(struct mii_softc *sc) 791 { 792 static const struct { 793 int reg; 794 uint16_t val; 795 } dspcode[] = { 796 { BRGPHY_MII_AUXCTL, 0x0c00 }, 797 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 798 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 799 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 800 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 801 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 802 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 803 { BRGPHY_MII_AUXCTL, 0x0400 }, 804 { 0, 0 }, 805 }; 806 int i; 807 808 for (i = 0; dspcode[i].reg != 0; i++) 809 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 810 } 811 812 static void 813 brgphy_fixup_crc_bug(struct mii_softc *sc) 814 { 815 static const struct { 816 int reg; 817 uint16_t val; 818 } dspcode[] = { 819 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 820 { 0x1c, 0x8c68 }, 821 { 0x1c, 0x8d68 }, 822 { 0x1c, 0x8c68 }, 823 { 0, 0 }, 824 }; 825 int i; 826 827 for (i = 0; dspcode[i].reg != 0; i++) 828 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 829 } 830 831 static void 832 brgphy_fixup_jitter_bug(struct mii_softc *sc) 833 { 834 static const struct { 835 int reg; 836 uint16_t val; 837 } dspcode[] = { 838 { BRGPHY_MII_AUXCTL, 0x0c00 }, 839 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 840 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 841 { BRGPHY_MII_AUXCTL, 0x0400 }, 842 { 0, 0 }, 843 }; 844 int i; 845 846 for (i = 0; dspcode[i].reg != 0; i++) 847 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 848 } 849 850 static void 851 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 852 { 853 uint32_t val; 854 855 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 856 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 857 val &= ~(1 << 8); 858 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 859 860 } 861 862 static void 863 brgphy_ethernet_wirespeed(struct mii_softc *sc) 864 { 865 uint32_t val; 866 867 /* Enable Ethernet@WireSpeed. */ 868 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 869 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 870 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 871 } 872 873 static void 874 brgphy_bcm54xx_clock_delay(struct mii_softc *sc) 875 { 876 uint16_t val; 877 878 if (!(sc->mii_flags & (MIIF_RX_DELAY | MIIF_TX_DELAY))) 879 /* Adjusting the clocks in rgmii mode causes packet losses. */ 880 return; 881 882 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC | 883 BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT); 884 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 885 val &= BRGPHY_AUXCTL_MISC_DATA_MASK; 886 if (sc->mii_flags & MIIF_RX_DELAY) 887 val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; 888 else 889 val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; 890 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN | 891 BRGPHY_AUXCTL_SHADOW_MISC | val); 892 893 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_CLK_CTRL); 894 val = PHY_READ(sc, BRGPHY_MII_SHADOW_1C); 895 val &= BRGPHY_SHADOW_1C_DATA_MASK; 896 if (sc->mii_flags & MIIF_TX_DELAY) 897 val |= BRGPHY_SHADOW_1C_GTXCLK_EN; 898 else 899 val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN; 900 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_WRITE_EN | 901 BRGPHY_SHADOW_1C_CLK_CTRL | val); 902 } 903 904 static void 905 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 906 { 907 uint32_t val; 908 909 /* Set or clear jumbo frame settings in the PHY. */ 910 if (mtu > ETHER_MAX_LEN) { 911 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 912 /* BCM5401 PHY cannot read-modify-write. */ 913 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 914 } else { 915 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 916 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 917 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 918 val | BRGPHY_AUXCTL_LONG_PKT); 919 } 920 921 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 922 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 923 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 924 } else { 925 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 926 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 927 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 928 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 929 930 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 931 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 932 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 933 } 934 } 935 936 static void 937 brgphy_reset(struct mii_softc *sc) 938 { 939 struct bge_softc *bge_sc = NULL; 940 struct bce_softc *bce_sc = NULL; 941 if_t ifp; 942 int i, val; 943 944 /* 945 * Perform a reset. Note that at least some Broadcom PHYs default to 946 * being powered down as well as isolated after a reset but don't work 947 * if one or both of these bits are cleared. However, they just work 948 * fine if both bits remain set, so we don't use mii_phy_reset() here. 949 */ 950 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 951 952 /* Wait 100ms for it to complete. */ 953 for (i = 0; i < 100; i++) { 954 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 955 break; 956 DELAY(1000); 957 } 958 959 /* Handle any PHY specific procedures following the reset. */ 960 switch (sc->mii_mpd_oui) { 961 case MII_OUI_BROADCOM: 962 switch (sc->mii_mpd_model) { 963 case MII_MODEL_BROADCOM_BCM5400: 964 bcm5401_load_dspcode(sc); 965 break; 966 case MII_MODEL_BROADCOM_BCM5401: 967 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 968 bcm5401_load_dspcode(sc); 969 break; 970 case MII_MODEL_BROADCOM_BCM5411: 971 bcm5411_load_dspcode(sc); 972 break; 973 case MII_MODEL_BROADCOM_BCM54K2: 974 bcm54k2_load_dspcode(sc); 975 break; 976 } 977 break; 978 case MII_OUI_BROADCOM3: 979 switch (sc->mii_mpd_model) { 980 case MII_MODEL_BROADCOM3_BCM5717C: 981 case MII_MODEL_BROADCOM3_BCM5719C: 982 case MII_MODEL_BROADCOM3_BCM5720C: 983 case MII_MODEL_BROADCOM3_BCM57765: 984 return; 985 } 986 break; 987 case MII_OUI_BROADCOM4: 988 return; 989 } 990 991 ifp = sc->mii_pdata->mii_ifp; 992 993 /* Find the driver associated with this PHY. */ 994 if (mii_phy_mac_match(sc, "bge")) 995 bge_sc = mii_phy_mac_softc(sc); 996 else if (mii_phy_mac_match(sc, "bce")) 997 bce_sc = mii_phy_mac_softc(sc); 998 999 if (bge_sc) { 1000 /* Fix up various bugs */ 1001 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 1002 brgphy_fixup_5704_a0_bug(sc); 1003 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 1004 brgphy_fixup_adc_bug(sc); 1005 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 1006 brgphy_fixup_adjust_trim(sc); 1007 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 1008 brgphy_fixup_ber_bug(sc); 1009 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 1010 brgphy_fixup_crc_bug(sc); 1011 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 1012 brgphy_fixup_jitter_bug(sc); 1013 1014 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 1015 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1016 1017 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 1018 brgphy_ethernet_wirespeed(sc); 1019 1020 /* Enable Link LED on Dell boxes */ 1021 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 1022 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1023 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 1024 ~BRGPHY_PHY_EXTCTL_3_LED); 1025 } 1026 1027 /* Adjust output voltage (From Linux driver) */ 1028 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 1029 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 1030 } else if (bce_sc) { 1031 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 1032 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1033 /* Store autoneg capabilities/results in digital block (Page 0) */ 1034 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 1035 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 1036 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 1037 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 1038 1039 /* Enable fiber mode and autodetection */ 1040 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 1041 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 1042 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 1043 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 1044 1045 /* Enable parallel detection */ 1046 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1047 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1048 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1049 1050 /* Advertise 2.5G support through next page during autoneg */ 1051 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1052 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1053 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1054 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1055 1056 /* Increase TX signal amplitude */ 1057 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1058 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1059 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1060 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1061 BRGPHY_5708S_TX_MISC_PG5); 1062 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1063 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1064 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1065 BRGPHY_5708S_DIG_PG0); 1066 } 1067 1068 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1069 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1070 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1071 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1072 BRGPHY_5708S_TX_MISC_PG5); 1073 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1074 bce_sc->bce_port_hw_cfg & 1075 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1076 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1077 BRGPHY_5708S_DIG_PG0); 1078 } 1079 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1080 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1081 /* Select the SerDes Digital block of the AN MMD. */ 1082 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1083 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1084 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1085 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1086 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1087 1088 /* Select the Over 1G block of the AN MMD. */ 1089 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1090 1091 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1092 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1093 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1094 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1095 else 1096 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1097 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1098 1099 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1100 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1101 1102 /* Enable MRBE speed autoneg. */ 1103 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1104 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1105 BRGPHY_MRBE_MSG_PG5_NP_T2; 1106 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1107 1108 /* Select the Clause 73 User B0 block of the AN MMD. */ 1109 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1110 1111 /* Enable MRBE speed autoneg. */ 1112 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1113 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1114 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1115 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1116 1117 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1118 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1119 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1120 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1121 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1122 brgphy_fixup_disable_early_dac(sc); 1123 1124 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1125 brgphy_ethernet_wirespeed(sc); 1126 } else { 1127 brgphy_fixup_ber_bug(sc); 1128 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1129 brgphy_ethernet_wirespeed(sc); 1130 } 1131 } 1132 } 1133