1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2000 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/bus.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/ethernet.h> 53 #include <net/if_media.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include "miidevs.h" 58 59 #include <dev/mii/brgphyreg.h> 60 #include <net/if_arp.h> 61 #include <machine/bus.h> 62 #include <dev/bge/if_bgereg.h> 63 #include <dev/bce/if_bcereg.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include "miibus_if.h" 69 70 static int brgphy_probe(device_t); 71 static int brgphy_attach(device_t); 72 73 struct brgphy_softc { 74 struct mii_softc mii_sc; 75 int serdes_flags; /* Keeps track of the serdes type used */ 76 #define BRGPHY_5706S 0x0001 77 #define BRGPHY_5708S 0x0002 78 #define BRGPHY_NOANWAIT 0x0004 79 #define BRGPHY_5709S 0x0008 80 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 81 }; 82 83 static device_method_t brgphy_methods[] = { 84 /* device interface */ 85 DEVMETHOD(device_probe, brgphy_probe), 86 DEVMETHOD(device_attach, brgphy_attach), 87 DEVMETHOD(device_detach, mii_phy_detach), 88 DEVMETHOD(device_shutdown, bus_generic_shutdown), 89 DEVMETHOD_END 90 }; 91 92 static devclass_t brgphy_devclass; 93 94 static driver_t brgphy_driver = { 95 "brgphy", 96 brgphy_methods, 97 sizeof(struct brgphy_softc) 98 }; 99 100 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 101 102 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 103 static void brgphy_setmedia(struct mii_softc *, int); 104 static void brgphy_status(struct mii_softc *); 105 static void brgphy_mii_phy_auto(struct mii_softc *, int); 106 static void brgphy_reset(struct mii_softc *); 107 static void brgphy_enable_loopback(struct mii_softc *); 108 static void bcm5401_load_dspcode(struct mii_softc *); 109 static void bcm5411_load_dspcode(struct mii_softc *); 110 static void bcm54k2_load_dspcode(struct mii_softc *); 111 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 112 static void brgphy_fixup_adc_bug(struct mii_softc *); 113 static void brgphy_fixup_adjust_trim(struct mii_softc *); 114 static void brgphy_fixup_ber_bug(struct mii_softc *); 115 static void brgphy_fixup_crc_bug(struct mii_softc *); 116 static void brgphy_fixup_jitter_bug(struct mii_softc *); 117 static void brgphy_ethernet_wirespeed(struct mii_softc *); 118 static void brgphy_bcm54xx_clock_delay(struct mii_softc *); 119 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 120 121 static const struct mii_phydesc brgphys[] = { 122 MII_PHY_DESC(BROADCOM, BCM5400), 123 MII_PHY_DESC(BROADCOM, BCM5401), 124 MII_PHY_DESC(BROADCOM, BCM5402), 125 MII_PHY_DESC(BROADCOM, BCM5411), 126 MII_PHY_DESC(BROADCOM, BCM5404), 127 MII_PHY_DESC(BROADCOM, BCM5424), 128 MII_PHY_DESC(BROADCOM, BCM54K2), 129 MII_PHY_DESC(BROADCOM, BCM5701), 130 MII_PHY_DESC(BROADCOM, BCM5703), 131 MII_PHY_DESC(BROADCOM, BCM5704), 132 MII_PHY_DESC(BROADCOM, BCM5705), 133 MII_PHY_DESC(BROADCOM, BCM5706), 134 MII_PHY_DESC(BROADCOM, BCM5714), 135 MII_PHY_DESC(BROADCOM, BCM5421), 136 MII_PHY_DESC(BROADCOM, BCM5750), 137 MII_PHY_DESC(BROADCOM, BCM5752), 138 MII_PHY_DESC(BROADCOM, BCM5780), 139 MII_PHY_DESC(BROADCOM, BCM5708C), 140 MII_PHY_DESC(BROADCOM, BCM5466), 141 MII_PHY_DESC(BROADCOM2, BCM5478), 142 MII_PHY_DESC(BROADCOM2, BCM5488), 143 MII_PHY_DESC(BROADCOM2, BCM5482), 144 MII_PHY_DESC(BROADCOM2, BCM5708S), 145 MII_PHY_DESC(BROADCOM2, BCM5709C), 146 MII_PHY_DESC(BROADCOM2, BCM5709S), 147 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 148 MII_PHY_DESC(BROADCOM2, BCM5722), 149 MII_PHY_DESC(BROADCOM2, BCM5755), 150 MII_PHY_DESC(BROADCOM2, BCM5754), 151 MII_PHY_DESC(BROADCOM2, BCM5761), 152 MII_PHY_DESC(BROADCOM2, BCM5784), 153 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 154 MII_PHY_DESC(BROADCOM2, BCM5785), 155 #endif 156 MII_PHY_DESC(BROADCOM3, BCM54618SE), 157 MII_PHY_DESC(BROADCOM3, BCM5717C), 158 MII_PHY_DESC(BROADCOM3, BCM5719C), 159 MII_PHY_DESC(BROADCOM3, BCM5720C), 160 MII_PHY_DESC(BROADCOM3, BCM57765), 161 MII_PHY_DESC(BROADCOM3, BCM57780), 162 MII_PHY_DESC(BROADCOM4, BCM54213PE), 163 MII_PHY_DESC(BROADCOM4, BCM5725C), 164 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 165 MII_PHY_END 166 }; 167 168 static const struct mii_phy_funcs brgphy_funcs = { 169 brgphy_service, 170 brgphy_status, 171 brgphy_reset 172 }; 173 174 static const struct hs21_type { 175 const uint32_t id; 176 const char *prod; 177 } hs21_type_lists[] = { 178 { 0x57081021, "IBM eServer BladeCenter HS21" }, 179 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" }, 180 }; 181 182 static int 183 detect_hs21(struct bce_softc *bce_sc) 184 { 185 char *sysenv; 186 int found, i; 187 188 found = 0; 189 sysenv = kern_getenv("smbios.system.product"); 190 if (sysenv == NULL) 191 return (found); 192 for (i = 0; i < nitems(hs21_type_lists); i++) { 193 if (bce_sc->bce_chipid == hs21_type_lists[i].id && 194 strncmp(sysenv, hs21_type_lists[i].prod, 195 strlen(hs21_type_lists[i].prod)) == 0) { 196 found++; 197 break; 198 } 199 } 200 freeenv(sysenv); 201 return (found); 202 } 203 204 /* Search for our PHY in the list of known PHYs */ 205 static int 206 brgphy_probe(device_t dev) 207 { 208 209 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 210 } 211 212 /* Attach the PHY to the MII bus */ 213 static int 214 brgphy_attach(device_t dev) 215 { 216 struct brgphy_softc *bsc; 217 struct bge_softc *bge_sc = NULL; 218 struct bce_softc *bce_sc = NULL; 219 struct mii_softc *sc; 220 221 bsc = device_get_softc(dev); 222 sc = &bsc->mii_sc; 223 224 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 225 &brgphy_funcs, 0); 226 227 bsc->serdes_flags = 0; 228 229 /* Find the MAC driver associated with this PHY. */ 230 if (mii_dev_mac_match(dev, "bge")) 231 bge_sc = mii_dev_mac_softc(dev); 232 else if (mii_dev_mac_match(dev, "bce")) 233 bce_sc = mii_dev_mac_softc(dev); 234 235 /* Handle any special cases based on the PHY ID */ 236 switch (sc->mii_mpd_oui) { 237 case MII_OUI_BROADCOM: 238 switch (sc->mii_mpd_model) { 239 case MII_MODEL_BROADCOM_BCM5706: 240 case MII_MODEL_BROADCOM_BCM5714: 241 /* 242 * The 5464 PHY used in the 5706 supports both copper 243 * and fiber interfaces over GMII. Need to check the 244 * shadow registers to see which mode is actually 245 * in effect, and therefore whether we have 5706C or 246 * 5706S. 247 */ 248 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 249 BRGPHY_SHADOW_1C_MODE_CTRL); 250 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 251 BRGPHY_SHADOW_1C_ENA_1000X) { 252 bsc->serdes_flags |= BRGPHY_5706S; 253 sc->mii_flags |= MIIF_HAVEFIBER; 254 } 255 break; 256 } 257 break; 258 case MII_OUI_BROADCOM2: 259 switch (sc->mii_mpd_model) { 260 case MII_MODEL_BROADCOM2_BCM5708S: 261 bsc->serdes_flags |= BRGPHY_5708S; 262 sc->mii_flags |= MIIF_HAVEFIBER; 263 break; 264 case MII_MODEL_BROADCOM2_BCM5709S: 265 /* 266 * XXX 267 * 5720S and 5709S shares the same PHY id. 268 * Assume 5720S PHY if parent device is bge(4). 269 */ 270 if (bge_sc != NULL) 271 bsc->serdes_flags |= BRGPHY_5708S; 272 else 273 bsc->serdes_flags |= BRGPHY_5709S; 274 sc->mii_flags |= MIIF_HAVEFIBER; 275 break; 276 } 277 break; 278 } 279 280 PHY_RESET(sc); 281 282 /* Read the PHY's capabilities. */ 283 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 284 if (sc->mii_capabilities & BMSR_EXTSTAT) 285 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 286 device_printf(dev, " "); 287 288 /* Add the supported media types */ 289 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 290 mii_phy_add_media(sc); 291 printf("\n"); 292 } else { 293 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 294 ifmedia_add(&sc->mii_pdata->mii_media, 295 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 296 0, NULL); 297 printf("1000baseSX-FDX, "); 298 /* 299 * 2.5G support is a software enabled feature 300 * on the 5708S and 5709S. 301 */ 302 if (bce_sc && (bce_sc->bce_phy_flags & 303 BCE_PHY_2_5G_CAPABLE_FLAG)) { 304 ifmedia_add(&sc->mii_pdata->mii_media, 305 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, 306 sc->mii_inst), 0, NULL); 307 printf("2500baseSX-FDX, "); 308 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 309 (detect_hs21(bce_sc) != 0)) { 310 /* 311 * There appears to be certain silicon revision 312 * in IBM HS21 blades that is having issues with 313 * this driver wating for the auto-negotiation to 314 * complete. This happens with a specific chip id 315 * only and when the 1000baseSX-FDX is the only 316 * mode. Workaround this issue since it's unlikely 317 * to be ever addressed. 318 */ 319 printf("auto-neg workaround, "); 320 bsc->serdes_flags |= BRGPHY_NOANWAIT; 321 } 322 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER, 323 IFM_AUTO, 0, sc->mii_inst), 0, NULL); 324 printf("auto\n"); 325 } 326 327 MIIBUS_MEDIAINIT(sc->mii_dev); 328 return (0); 329 } 330 331 static int 332 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 333 { 334 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 335 int val; 336 337 switch (cmd) { 338 case MII_POLLSTAT: 339 break; 340 case MII_MEDIACHG: 341 /* Todo: Why is this here? Is it really needed? */ 342 PHY_RESET(sc); /* XXX hardware bug work-around */ 343 344 switch (IFM_SUBTYPE(ife->ifm_media)) { 345 case IFM_AUTO: 346 brgphy_mii_phy_auto(sc, ife->ifm_media); 347 break; 348 case IFM_2500_SX: 349 case IFM_1000_SX: 350 case IFM_1000_T: 351 case IFM_100_TX: 352 case IFM_10_T: 353 brgphy_setmedia(sc, ife->ifm_media); 354 break; 355 default: 356 return (EINVAL); 357 } 358 break; 359 case MII_TICK: 360 /* Bail if autoneg isn't in process. */ 361 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 362 sc->mii_ticks = 0; 363 break; 364 } 365 366 /* 367 * Check to see if we have link. If we do, we don't 368 * need to restart the autonegotiation process. 369 */ 370 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 371 if (val & BMSR_LINK) { 372 sc->mii_ticks = 0; /* Reset autoneg timer. */ 373 break; 374 } 375 376 /* Announce link loss right after it happens. */ 377 if (sc->mii_ticks++ == 0) 378 break; 379 380 /* Only retry autonegotiation every mii_anegticks seconds. */ 381 if (sc->mii_ticks <= sc->mii_anegticks) 382 break; 383 384 385 /* Retry autonegotiation */ 386 sc->mii_ticks = 0; 387 brgphy_mii_phy_auto(sc, ife->ifm_media); 388 break; 389 } 390 391 /* Update the media status. */ 392 PHY_STATUS(sc); 393 394 /* 395 * Callback if something changed. Note that we need to poke 396 * the DSP on the Broadcom PHYs if the media changes. 397 */ 398 if (sc->mii_media_active != mii->mii_media_active || 399 sc->mii_media_status != mii->mii_media_status || 400 cmd == MII_MEDIACHG) { 401 switch (sc->mii_mpd_oui) { 402 case MII_OUI_BROADCOM: 403 switch (sc->mii_mpd_model) { 404 case MII_MODEL_BROADCOM_BCM5400: 405 bcm5401_load_dspcode(sc); 406 break; 407 case MII_MODEL_BROADCOM_BCM5401: 408 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 409 bcm5401_load_dspcode(sc); 410 break; 411 case MII_MODEL_BROADCOM_BCM5411: 412 bcm5411_load_dspcode(sc); 413 break; 414 case MII_MODEL_BROADCOM_BCM54K2: 415 bcm54k2_load_dspcode(sc); 416 break; 417 } 418 break; 419 case MII_OUI_BROADCOM4: 420 switch (sc->mii_mpd_model) { 421 case MII_MODEL_BROADCOM4_BCM54213PE: 422 brgphy_bcm54xx_clock_delay(sc); 423 break; 424 } 425 } 426 } 427 mii_phy_update(sc, cmd); 428 return (0); 429 } 430 431 /****************************************************************************/ 432 /* Sets the PHY link speed. */ 433 /* */ 434 /* Returns: */ 435 /* None */ 436 /****************************************************************************/ 437 static void 438 brgphy_setmedia(struct mii_softc *sc, int media) 439 { 440 int bmcr = 0, gig; 441 442 switch (IFM_SUBTYPE(media)) { 443 case IFM_2500_SX: 444 break; 445 case IFM_1000_SX: 446 case IFM_1000_T: 447 bmcr = BRGPHY_S1000; 448 break; 449 case IFM_100_TX: 450 bmcr = BRGPHY_S100; 451 break; 452 case IFM_10_T: 453 default: 454 bmcr = BRGPHY_S10; 455 break; 456 } 457 458 if ((media & IFM_FDX) != 0) { 459 bmcr |= BRGPHY_BMCR_FDX; 460 gig = BRGPHY_1000CTL_AFD; 461 } else { 462 gig = BRGPHY_1000CTL_AHD; 463 } 464 465 /* Force loopback to disconnect PHY from Ethernet medium. */ 466 brgphy_enable_loopback(sc); 467 468 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 469 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 470 471 if (IFM_SUBTYPE(media) != IFM_1000_T && 472 IFM_SUBTYPE(media) != IFM_1000_SX) { 473 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 474 return; 475 } 476 477 if (IFM_SUBTYPE(media) == IFM_1000_T) { 478 gig |= BRGPHY_1000CTL_MSE; 479 if ((media & IFM_ETH_MASTER) != 0) 480 gig |= BRGPHY_1000CTL_MSC; 481 } 482 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 483 PHY_WRITE(sc, BRGPHY_MII_BMCR, 484 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 485 } 486 487 /****************************************************************************/ 488 /* Set the media status based on the PHY settings. */ 489 /* */ 490 /* Returns: */ 491 /* None */ 492 /****************************************************************************/ 493 static void 494 brgphy_status(struct mii_softc *sc) 495 { 496 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 497 struct mii_data *mii = sc->mii_pdata; 498 int aux, bmcr, bmsr, val, xstat; 499 u_int flowstat; 500 501 mii->mii_media_status = IFM_AVALID; 502 mii->mii_media_active = IFM_ETHER; 503 504 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 505 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 506 507 if (bmcr & BRGPHY_BMCR_LOOP) { 508 mii->mii_media_active |= IFM_LOOP; 509 } 510 511 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 512 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 513 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 514 /* Erg, still trying, I guess... */ 515 mii->mii_media_active |= IFM_NONE; 516 return; 517 } 518 519 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 520 /* 521 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 522 * wedges at least the PHY of BCM5704 (but not others). 523 */ 524 flowstat = mii_phy_flowstatus(sc); 525 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 526 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 527 528 /* If copper link is up, get the negotiated speed/duplex. */ 529 if (aux & BRGPHY_AUXSTS_LINK) { 530 mii->mii_media_status |= IFM_ACTIVE; 531 switch (aux & BRGPHY_AUXSTS_AN_RES) { 532 case BRGPHY_RES_1000FD: 533 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 534 case BRGPHY_RES_1000HD: 535 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 536 case BRGPHY_RES_100FD: 537 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 538 case BRGPHY_RES_100T4: 539 mii->mii_media_active |= IFM_100_T4; break; 540 case BRGPHY_RES_100HD: 541 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 542 case BRGPHY_RES_10FD: 543 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 544 case BRGPHY_RES_10HD: 545 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 546 default: 547 mii->mii_media_active |= IFM_NONE; break; 548 } 549 550 if ((mii->mii_media_active & IFM_FDX) != 0) 551 mii->mii_media_active |= flowstat; 552 553 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 554 (xstat & BRGPHY_1000STS_MSR) != 0) 555 mii->mii_media_active |= IFM_ETH_MASTER; 556 } 557 } else { 558 /* Todo: Add support for flow control. */ 559 /* If serdes link is up, get the negotiated speed/duplex. */ 560 if (bmsr & BRGPHY_BMSR_LINK) { 561 mii->mii_media_status |= IFM_ACTIVE; 562 } 563 564 /* Check the link speed/duplex based on the PHY type. */ 565 if (bsc->serdes_flags & BRGPHY_5706S) { 566 mii->mii_media_active |= IFM_1000_SX; 567 568 /* If autoneg enabled, read negotiated duplex settings */ 569 if (bmcr & BRGPHY_BMCR_AUTOEN) { 570 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 571 if (val & BRGPHY_SERDES_ANAR_FDX) 572 mii->mii_media_active |= IFM_FDX; 573 else 574 mii->mii_media_active |= IFM_HDX; 575 } 576 } else if (bsc->serdes_flags & BRGPHY_5708S) { 577 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 578 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 579 580 /* Check for MRBE auto-negotiated speed results. */ 581 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 582 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 583 mii->mii_media_active |= IFM_10_FL; break; 584 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 585 mii->mii_media_active |= IFM_100_FX; break; 586 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 587 mii->mii_media_active |= IFM_1000_SX; break; 588 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 589 mii->mii_media_active |= IFM_2500_SX; break; 590 } 591 592 /* Check for MRBE auto-negotiated duplex results. */ 593 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 594 mii->mii_media_active |= IFM_FDX; 595 else 596 mii->mii_media_active |= IFM_HDX; 597 } else if (bsc->serdes_flags & BRGPHY_5709S) { 598 /* Select GP Status Block of the AN MMD, get autoneg results. */ 599 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 600 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 601 602 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 603 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 604 605 /* Check for MRBE auto-negotiated speed results. */ 606 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 607 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 608 mii->mii_media_active |= IFM_10_FL; break; 609 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 610 mii->mii_media_active |= IFM_100_FX; break; 611 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 612 mii->mii_media_active |= IFM_1000_SX; break; 613 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 614 mii->mii_media_active |= IFM_2500_SX; break; 615 } 616 617 /* Check for MRBE auto-negotiated duplex results. */ 618 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 619 mii->mii_media_active |= IFM_FDX; 620 else 621 mii->mii_media_active |= IFM_HDX; 622 } 623 } 624 } 625 626 static void 627 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 628 { 629 int anar, ktcr = 0; 630 631 PHY_RESET(sc); 632 633 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 634 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 635 if ((media & IFM_FLOW) != 0 || 636 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 637 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 638 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 639 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 640 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 641 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 642 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 643 PHY_READ(sc, BRGPHY_MII_1000CTL); 644 } else { 645 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 646 if ((media & IFM_FLOW) != 0 || 647 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 648 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 649 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 650 } 651 652 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 653 BRGPHY_BMCR_STARTNEG); 654 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 655 } 656 657 /* Enable loopback to force the link down. */ 658 static void 659 brgphy_enable_loopback(struct mii_softc *sc) 660 { 661 int i; 662 663 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 664 for (i = 0; i < 15000; i++) { 665 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 666 break; 667 DELAY(10); 668 } 669 } 670 671 /* Turn off tap power management on 5401. */ 672 static void 673 bcm5401_load_dspcode(struct mii_softc *sc) 674 { 675 static const struct { 676 int reg; 677 uint16_t val; 678 } dspcode[] = { 679 { BRGPHY_MII_AUXCTL, 0x0c20 }, 680 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 681 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 682 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 683 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 684 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 685 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 686 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 687 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 688 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 689 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 690 { 0, 0 }, 691 }; 692 int i; 693 694 for (i = 0; dspcode[i].reg != 0; i++) 695 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 696 DELAY(40); 697 } 698 699 static void 700 bcm5411_load_dspcode(struct mii_softc *sc) 701 { 702 static const struct { 703 int reg; 704 uint16_t val; 705 } dspcode[] = { 706 { 0x1c, 0x8c23 }, 707 { 0x1c, 0x8ca3 }, 708 { 0x1c, 0x8c23 }, 709 { 0, 0 }, 710 }; 711 int i; 712 713 for (i = 0; dspcode[i].reg != 0; i++) 714 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 715 } 716 717 void 718 bcm54k2_load_dspcode(struct mii_softc *sc) 719 { 720 static const struct { 721 int reg; 722 uint16_t val; 723 } dspcode[] = { 724 { 4, 0x01e1 }, 725 { 9, 0x0300 }, 726 { 0, 0 }, 727 }; 728 int i; 729 730 for (i = 0; dspcode[i].reg != 0; i++) 731 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 732 733 } 734 735 static void 736 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 737 { 738 static const struct { 739 int reg; 740 uint16_t val; 741 } dspcode[] = { 742 { 0x1c, 0x8d68 }, 743 { 0x1c, 0x8d68 }, 744 { 0, 0 }, 745 }; 746 int i; 747 748 for (i = 0; dspcode[i].reg != 0; i++) 749 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 750 } 751 752 static void 753 brgphy_fixup_adc_bug(struct mii_softc *sc) 754 { 755 static const struct { 756 int reg; 757 uint16_t val; 758 } dspcode[] = { 759 { BRGPHY_MII_AUXCTL, 0x0c00 }, 760 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 761 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 762 { 0, 0 }, 763 }; 764 int i; 765 766 for (i = 0; dspcode[i].reg != 0; i++) 767 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 768 } 769 770 static void 771 brgphy_fixup_adjust_trim(struct mii_softc *sc) 772 { 773 static const struct { 774 int reg; 775 uint16_t val; 776 } dspcode[] = { 777 { BRGPHY_MII_AUXCTL, 0x0c00 }, 778 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 779 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 780 { BRGPHY_MII_TEST1, 0x0014 }, 781 { BRGPHY_MII_AUXCTL, 0x0400 }, 782 { 0, 0 }, 783 }; 784 int i; 785 786 for (i = 0; dspcode[i].reg != 0; i++) 787 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 788 } 789 790 static void 791 brgphy_fixup_ber_bug(struct mii_softc *sc) 792 { 793 static const struct { 794 int reg; 795 uint16_t val; 796 } dspcode[] = { 797 { BRGPHY_MII_AUXCTL, 0x0c00 }, 798 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 799 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 800 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 801 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 802 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 803 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 804 { BRGPHY_MII_AUXCTL, 0x0400 }, 805 { 0, 0 }, 806 }; 807 int i; 808 809 for (i = 0; dspcode[i].reg != 0; i++) 810 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 811 } 812 813 static void 814 brgphy_fixup_crc_bug(struct mii_softc *sc) 815 { 816 static const struct { 817 int reg; 818 uint16_t val; 819 } dspcode[] = { 820 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 821 { 0x1c, 0x8c68 }, 822 { 0x1c, 0x8d68 }, 823 { 0x1c, 0x8c68 }, 824 { 0, 0 }, 825 }; 826 int i; 827 828 for (i = 0; dspcode[i].reg != 0; i++) 829 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 830 } 831 832 static void 833 brgphy_fixup_jitter_bug(struct mii_softc *sc) 834 { 835 static const struct { 836 int reg; 837 uint16_t val; 838 } dspcode[] = { 839 { BRGPHY_MII_AUXCTL, 0x0c00 }, 840 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 841 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 842 { BRGPHY_MII_AUXCTL, 0x0400 }, 843 { 0, 0 }, 844 }; 845 int i; 846 847 for (i = 0; dspcode[i].reg != 0; i++) 848 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 849 } 850 851 static void 852 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 853 { 854 uint32_t val; 855 856 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 857 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 858 val &= ~(1 << 8); 859 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 860 861 } 862 863 static void 864 brgphy_ethernet_wirespeed(struct mii_softc *sc) 865 { 866 uint32_t val; 867 868 /* Enable Ethernet@WireSpeed. */ 869 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 870 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 871 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 872 } 873 874 static void 875 brgphy_bcm54xx_clock_delay(struct mii_softc *sc) 876 { 877 uint16_t val; 878 879 if (!(sc->mii_flags & (MIIF_RX_DELAY | MIIF_TX_DELAY))) 880 /* Adjusting the clocks in rgmii mode causes packet losses. */ 881 return; 882 883 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC | 884 BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT); 885 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 886 val &= BRGPHY_AUXCTL_MISC_DATA_MASK; 887 if (sc->mii_flags & MIIF_RX_DELAY) 888 val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; 889 else 890 val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; 891 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN | 892 BRGPHY_AUXCTL_SHADOW_MISC | val); 893 894 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_CLK_CTRL); 895 val = PHY_READ(sc, BRGPHY_MII_SHADOW_1C); 896 val &= BRGPHY_SHADOW_1C_DATA_MASK; 897 if (sc->mii_flags & MIIF_TX_DELAY) 898 val |= BRGPHY_SHADOW_1C_GTXCLK_EN; 899 else 900 val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN; 901 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_WRITE_EN | 902 BRGPHY_SHADOW_1C_CLK_CTRL | val); 903 } 904 905 static void 906 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 907 { 908 uint32_t val; 909 910 /* Set or clear jumbo frame settings in the PHY. */ 911 if (mtu > ETHER_MAX_LEN) { 912 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 913 /* BCM5401 PHY cannot read-modify-write. */ 914 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 915 } else { 916 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 917 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 918 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 919 val | BRGPHY_AUXCTL_LONG_PKT); 920 } 921 922 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 923 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 924 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 925 } else { 926 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 927 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 928 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 929 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 930 931 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 932 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 933 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 934 } 935 } 936 937 static void 938 brgphy_reset(struct mii_softc *sc) 939 { 940 struct bge_softc *bge_sc = NULL; 941 struct bce_softc *bce_sc = NULL; 942 if_t ifp; 943 int i, val; 944 945 /* 946 * Perform a reset. Note that at least some Broadcom PHYs default to 947 * being powered down as well as isolated after a reset but don't work 948 * if one or both of these bits are cleared. However, they just work 949 * fine if both bits remain set, so we don't use mii_phy_reset() here. 950 */ 951 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 952 953 /* Wait 100ms for it to complete. */ 954 for (i = 0; i < 100; i++) { 955 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 956 break; 957 DELAY(1000); 958 } 959 960 /* Handle any PHY specific procedures following the reset. */ 961 switch (sc->mii_mpd_oui) { 962 case MII_OUI_BROADCOM: 963 switch (sc->mii_mpd_model) { 964 case MII_MODEL_BROADCOM_BCM5400: 965 bcm5401_load_dspcode(sc); 966 break; 967 case MII_MODEL_BROADCOM_BCM5401: 968 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 969 bcm5401_load_dspcode(sc); 970 break; 971 case MII_MODEL_BROADCOM_BCM5411: 972 bcm5411_load_dspcode(sc); 973 break; 974 case MII_MODEL_BROADCOM_BCM54K2: 975 bcm54k2_load_dspcode(sc); 976 break; 977 } 978 break; 979 case MII_OUI_BROADCOM3: 980 switch (sc->mii_mpd_model) { 981 case MII_MODEL_BROADCOM3_BCM5717C: 982 case MII_MODEL_BROADCOM3_BCM5719C: 983 case MII_MODEL_BROADCOM3_BCM5720C: 984 case MII_MODEL_BROADCOM3_BCM57765: 985 return; 986 } 987 break; 988 case MII_OUI_BROADCOM4: 989 return; 990 } 991 992 ifp = sc->mii_pdata->mii_ifp; 993 994 /* Find the driver associated with this PHY. */ 995 if (mii_phy_mac_match(sc, "bge")) 996 bge_sc = mii_phy_mac_softc(sc); 997 else if (mii_phy_mac_match(sc, "bce")) 998 bce_sc = mii_phy_mac_softc(sc); 999 1000 if (bge_sc) { 1001 /* Fix up various bugs */ 1002 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 1003 brgphy_fixup_5704_a0_bug(sc); 1004 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 1005 brgphy_fixup_adc_bug(sc); 1006 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 1007 brgphy_fixup_adjust_trim(sc); 1008 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 1009 brgphy_fixup_ber_bug(sc); 1010 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 1011 brgphy_fixup_crc_bug(sc); 1012 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 1013 brgphy_fixup_jitter_bug(sc); 1014 1015 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 1016 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1017 1018 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 1019 brgphy_ethernet_wirespeed(sc); 1020 1021 /* Enable Link LED on Dell boxes */ 1022 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 1023 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1024 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 1025 ~BRGPHY_PHY_EXTCTL_3_LED); 1026 } 1027 1028 /* Adjust output voltage (From Linux driver) */ 1029 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 1030 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 1031 } else if (bce_sc) { 1032 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 1033 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1034 1035 /* Store autoneg capabilities/results in digital block (Page 0) */ 1036 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 1037 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 1038 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 1039 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 1040 1041 /* Enable fiber mode and autodetection */ 1042 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 1043 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 1044 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 1045 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 1046 1047 /* Enable parallel detection */ 1048 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1049 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1050 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1051 1052 /* Advertise 2.5G support through next page during autoneg */ 1053 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1054 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1055 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1056 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1057 1058 /* Increase TX signal amplitude */ 1059 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1060 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1061 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1062 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1063 BRGPHY_5708S_TX_MISC_PG5); 1064 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1065 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1066 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1067 BRGPHY_5708S_DIG_PG0); 1068 } 1069 1070 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1071 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1072 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1073 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1074 BRGPHY_5708S_TX_MISC_PG5); 1075 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1076 bce_sc->bce_port_hw_cfg & 1077 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1078 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1079 BRGPHY_5708S_DIG_PG0); 1080 } 1081 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1082 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1083 1084 /* Select the SerDes Digital block of the AN MMD. */ 1085 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1086 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1087 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1088 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1089 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1090 1091 /* Select the Over 1G block of the AN MMD. */ 1092 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1093 1094 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1095 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1096 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1097 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1098 else 1099 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1100 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1101 1102 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1103 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1104 1105 /* Enable MRBE speed autoneg. */ 1106 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1107 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1108 BRGPHY_MRBE_MSG_PG5_NP_T2; 1109 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1110 1111 /* Select the Clause 73 User B0 block of the AN MMD. */ 1112 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1113 1114 /* Enable MRBE speed autoneg. */ 1115 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1116 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1117 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1118 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1119 1120 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1121 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1122 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1123 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1124 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1125 brgphy_fixup_disable_early_dac(sc); 1126 1127 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1128 brgphy_ethernet_wirespeed(sc); 1129 } else { 1130 brgphy_fixup_ber_bug(sc); 1131 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1132 brgphy_ethernet_wirespeed(sc); 1133 } 1134 } 1135 } 1136