xref: /freebsd/sys/dev/mii/brgphy.c (revision 9268022b74279434ed6300244e3f977e56a8ceb5)
1 /*-
2  * Copyright (c) 2000
3  *	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by Bill Paul.
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 /*
37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
38  */
39 
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/bus.h>
46 #include <sys/taskqueue.h>
47 
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/ethernet.h>
51 #include <net/if_media.h>
52 
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
55 #include "miidevs.h"
56 
57 #include <dev/mii/brgphyreg.h>
58 #include <net/if_arp.h>
59 #include <machine/bus.h>
60 #include <dev/bge/if_bgereg.h>
61 #include <dev/bce/if_bcereg.h>
62 
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65 
66 #include "miibus_if.h"
67 
68 static int brgphy_probe(device_t);
69 static int brgphy_attach(device_t);
70 
71 struct brgphy_softc {
72 	struct mii_softc mii_sc;
73 	int serdes_flags;	/* Keeps track of the serdes type used */
74 #define BRGPHY_5706S		0x0001
75 #define BRGPHY_5708S		0x0002
76 #define BRGPHY_NOANWAIT		0x0004
77 #define BRGPHY_5709S		0x0008
78 	int bce_phy_flags;	/* PHY flags transferred from the MAC driver */
79 };
80 
81 static device_method_t brgphy_methods[] = {
82 	/* device interface */
83 	DEVMETHOD(device_probe,		brgphy_probe),
84 	DEVMETHOD(device_attach,	brgphy_attach),
85 	DEVMETHOD(device_detach,	mii_phy_detach),
86 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
87 	DEVMETHOD_END
88 };
89 
90 static devclass_t brgphy_devclass;
91 
92 static driver_t brgphy_driver = {
93 	"brgphy",
94 	brgphy_methods,
95 	sizeof(struct brgphy_softc)
96 };
97 
98 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
99 
100 static int	brgphy_service(struct mii_softc *, struct mii_data *, int);
101 static void	brgphy_setmedia(struct mii_softc *, int);
102 static void	brgphy_status(struct mii_softc *);
103 static void	brgphy_mii_phy_auto(struct mii_softc *, int);
104 static void	brgphy_reset(struct mii_softc *);
105 static void	brgphy_enable_loopback(struct mii_softc *);
106 static void	bcm5401_load_dspcode(struct mii_softc *);
107 static void	bcm5411_load_dspcode(struct mii_softc *);
108 static void	bcm54k2_load_dspcode(struct mii_softc *);
109 static void	brgphy_fixup_5704_a0_bug(struct mii_softc *);
110 static void	brgphy_fixup_adc_bug(struct mii_softc *);
111 static void	brgphy_fixup_adjust_trim(struct mii_softc *);
112 static void	brgphy_fixup_ber_bug(struct mii_softc *);
113 static void	brgphy_fixup_crc_bug(struct mii_softc *);
114 static void	brgphy_fixup_jitter_bug(struct mii_softc *);
115 static void	brgphy_ethernet_wirespeed(struct mii_softc *);
116 static void	brgphy_jumbo_settings(struct mii_softc *, u_long);
117 
118 static const struct mii_phydesc brgphys[] = {
119 	MII_PHY_DESC(BROADCOM, BCM5400),
120 	MII_PHY_DESC(BROADCOM, BCM5401),
121 	MII_PHY_DESC(BROADCOM, BCM5411),
122 	MII_PHY_DESC(BROADCOM, BCM54K2),
123 	MII_PHY_DESC(BROADCOM, BCM5701),
124 	MII_PHY_DESC(BROADCOM, BCM5703),
125 	MII_PHY_DESC(BROADCOM, BCM5704),
126 	MII_PHY_DESC(BROADCOM, BCM5705),
127 	MII_PHY_DESC(BROADCOM, BCM5706),
128 	MII_PHY_DESC(BROADCOM, BCM5714),
129 	MII_PHY_DESC(BROADCOM, BCM5421),
130 	MII_PHY_DESC(BROADCOM, BCM5750),
131 	MII_PHY_DESC(BROADCOM, BCM5752),
132 	MII_PHY_DESC(BROADCOM, BCM5780),
133 	MII_PHY_DESC(BROADCOM, BCM5708C),
134 	MII_PHY_DESC(BROADCOM2, BCM5482),
135 	MII_PHY_DESC(BROADCOM2, BCM5708S),
136 	MII_PHY_DESC(BROADCOM2, BCM5709C),
137 	MII_PHY_DESC(BROADCOM2, BCM5709S),
138 	MII_PHY_DESC(BROADCOM2, BCM5709CAX),
139 	MII_PHY_DESC(BROADCOM2, BCM5722),
140 	MII_PHY_DESC(BROADCOM2, BCM5755),
141 	MII_PHY_DESC(BROADCOM2, BCM5754),
142 	MII_PHY_DESC(BROADCOM2, BCM5761),
143 	MII_PHY_DESC(BROADCOM2, BCM5784),
144 #ifdef notyet	/* better handled by ukphy(4) until WARs are implemented */
145 	MII_PHY_DESC(BROADCOM2, BCM5785),
146 #endif
147 	MII_PHY_DESC(BROADCOM3, BCM5717C),
148 	MII_PHY_DESC(BROADCOM3, BCM5719C),
149 	MII_PHY_DESC(BROADCOM3, BCM5720C),
150 	MII_PHY_DESC(BROADCOM3, BCM57765),
151 	MII_PHY_DESC(BROADCOM3, BCM57780),
152 	MII_PHY_DESC(BROADCOM4, BCM5725C),
153 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
154 	MII_PHY_END
155 };
156 
157 static const struct mii_phy_funcs brgphy_funcs = {
158 	brgphy_service,
159 	brgphy_status,
160 	brgphy_reset
161 };
162 
163 #define HS21_PRODUCT_ID	"IBM eServer BladeCenter HS21"
164 #define HS21_BCM_CHIPID	0x57081021
165 
166 static int
167 detect_hs21(struct bce_softc *bce_sc)
168 {
169 	char *sysenv;
170 	int found;
171 
172 	found = 0;
173 	if (bce_sc->bce_chipid == HS21_BCM_CHIPID) {
174 		sysenv = kern_getenv("smbios.system.product");
175 		if (sysenv != NULL) {
176 			if (strncmp(sysenv, HS21_PRODUCT_ID,
177 			    strlen(HS21_PRODUCT_ID)) == 0)
178 				found = 1;
179 			freeenv(sysenv);
180 		}
181 	}
182 	return (found);
183 }
184 
185 /* Search for our PHY in the list of known PHYs */
186 static int
187 brgphy_probe(device_t dev)
188 {
189 
190 	return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
191 }
192 
193 /* Attach the PHY to the MII bus */
194 static int
195 brgphy_attach(device_t dev)
196 {
197 	struct brgphy_softc *bsc;
198 	struct bge_softc *bge_sc = NULL;
199 	struct bce_softc *bce_sc = NULL;
200 	struct mii_softc *sc;
201 	if_t ifp;
202 
203 	bsc = device_get_softc(dev);
204 	sc = &bsc->mii_sc;
205 
206 	mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
207 	    &brgphy_funcs, 0);
208 
209 	bsc->serdes_flags = 0;
210 	ifp = sc->mii_pdata->mii_ifp;
211 
212 	/* Find the MAC driver associated with this PHY. */
213 	if (strcmp(if_getdname(ifp), "bge") == 0)
214 		bge_sc = if_getsoftc(ifp);
215 	else if (strcmp(if_getdname(ifp), "bce") == 0)
216 		bce_sc = if_getsoftc(ifp);
217 
218 	/* Handle any special cases based on the PHY ID */
219 	switch (sc->mii_mpd_oui) {
220 	case MII_OUI_BROADCOM:
221 		switch (sc->mii_mpd_model) {
222 		case MII_MODEL_BROADCOM_BCM5706:
223 		case MII_MODEL_BROADCOM_BCM5714:
224 			/*
225 			 * The 5464 PHY used in the 5706 supports both copper
226 			 * and fiber interfaces over GMII.  Need to check the
227 			 * shadow registers to see which mode is actually
228 			 * in effect, and therefore whether we have 5706C or
229 			 * 5706S.
230 			 */
231 			PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
232 				BRGPHY_SHADOW_1C_MODE_CTRL);
233 			if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
234 				BRGPHY_SHADOW_1C_ENA_1000X) {
235 				bsc->serdes_flags |= BRGPHY_5706S;
236 				sc->mii_flags |= MIIF_HAVEFIBER;
237 			}
238 			break;
239 		}
240 		break;
241 	case MII_OUI_BROADCOM2:
242 		switch (sc->mii_mpd_model) {
243 		case MII_MODEL_BROADCOM2_BCM5708S:
244 			bsc->serdes_flags |= BRGPHY_5708S;
245 			sc->mii_flags |= MIIF_HAVEFIBER;
246 			break;
247 		case MII_MODEL_BROADCOM2_BCM5709S:
248 			/*
249 			 * XXX
250 			 * 5720S and 5709S shares the same PHY id.
251 			 * Assume 5720S PHY if parent device is bge(4).
252 			 */
253 			if (bge_sc != NULL)
254 				bsc->serdes_flags |= BRGPHY_5708S;
255 			else
256 				bsc->serdes_flags |= BRGPHY_5709S;
257 			sc->mii_flags |= MIIF_HAVEFIBER;
258 			break;
259 		}
260 		break;
261 	}
262 
263 	PHY_RESET(sc);
264 
265 	/* Read the PHY's capabilities. */
266 	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
267 	if (sc->mii_capabilities & BMSR_EXTSTAT)
268 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
269 	device_printf(dev, " ");
270 
271 #define	ADD(m, c)	ifmedia_add(&sc->mii_pdata->mii_media, (m), (c), NULL)
272 
273 	/* Add the supported media types */
274 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
275 		mii_phy_add_media(sc);
276 		printf("\n");
277 	} else {
278 		sc->mii_anegticks = MII_ANEGTICKS_GIGE;
279 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
280 			BRGPHY_S1000 | BRGPHY_BMCR_FDX);
281 		printf("1000baseSX-FDX, ");
282 		/* 2.5G support is a software enabled feature on the 5708S and 5709S. */
283 		if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
284 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
285 			printf("2500baseSX-FDX, ");
286 		} else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
287 		    (detect_hs21(bce_sc) != 0)) {
288 			/*
289 			 * There appears to be certain silicon revision
290 			 * in IBM HS21 blades that is having issues with
291 			 * this driver wating for the auto-negotiation to
292 			 * complete. This happens with a specific chip id
293 			 * only and when the 1000baseSX-FDX is the only
294 			 * mode. Workaround this issue since it's unlikely
295 			 * to be ever addressed.
296 			 */
297 			printf("auto-neg workaround, ");
298 			bsc->serdes_flags |= BRGPHY_NOANWAIT;
299 		}
300 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
301 		printf("auto\n");
302 	}
303 
304 #undef ADD
305 	MIIBUS_MEDIAINIT(sc->mii_dev);
306 	return (0);
307 }
308 
309 static int
310 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
311 {
312 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
313 	int val;
314 
315 	switch (cmd) {
316 	case MII_POLLSTAT:
317 		break;
318 	case MII_MEDIACHG:
319 		/* Todo: Why is this here?  Is it really needed? */
320 		PHY_RESET(sc);	/* XXX hardware bug work-around */
321 
322 		switch (IFM_SUBTYPE(ife->ifm_media)) {
323 		case IFM_AUTO:
324 			brgphy_mii_phy_auto(sc, ife->ifm_media);
325 			break;
326 		case IFM_2500_SX:
327 		case IFM_1000_SX:
328 		case IFM_1000_T:
329 		case IFM_100_TX:
330 		case IFM_10_T:
331 			brgphy_setmedia(sc, ife->ifm_media);
332 			break;
333 		default:
334 			return (EINVAL);
335 		}
336 		break;
337 	case MII_TICK:
338 		/* Bail if autoneg isn't in process. */
339 		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
340 			sc->mii_ticks = 0;
341 			break;
342 		}
343 
344 		/*
345 		 * Check to see if we have link.  If we do, we don't
346 		 * need to restart the autonegotiation process.
347 		 */
348 		val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
349 		if (val & BMSR_LINK) {
350 			sc->mii_ticks = 0;	/* Reset autoneg timer. */
351 			break;
352 		}
353 
354 		/* Announce link loss right after it happens. */
355 		if (sc->mii_ticks++ == 0)
356 			break;
357 
358 		/* Only retry autonegotiation every mii_anegticks seconds. */
359 		if (sc->mii_ticks <= sc->mii_anegticks)
360 			break;
361 
362 
363 		/* Retry autonegotiation */
364 		sc->mii_ticks = 0;
365 		brgphy_mii_phy_auto(sc, ife->ifm_media);
366 		break;
367 	}
368 
369 	/* Update the media status. */
370 	PHY_STATUS(sc);
371 
372 	/*
373 	 * Callback if something changed. Note that we need to poke
374 	 * the DSP on the Broadcom PHYs if the media changes.
375 	 */
376 	if (sc->mii_media_active != mii->mii_media_active ||
377 	    sc->mii_media_status != mii->mii_media_status ||
378 	    cmd == MII_MEDIACHG) {
379 		switch (sc->mii_mpd_oui) {
380 		case MII_OUI_BROADCOM:
381 			switch (sc->mii_mpd_model) {
382 			case MII_MODEL_BROADCOM_BCM5400:
383 				bcm5401_load_dspcode(sc);
384 				break;
385 			case MII_MODEL_BROADCOM_BCM5401:
386 				if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
387 					bcm5401_load_dspcode(sc);
388 				break;
389 			case MII_MODEL_BROADCOM_BCM5411:
390 				bcm5411_load_dspcode(sc);
391 				break;
392 			case MII_MODEL_BROADCOM_BCM54K2:
393 				bcm54k2_load_dspcode(sc);
394 				break;
395 			}
396 			break;
397 		}
398 	}
399 	mii_phy_update(sc, cmd);
400 	return (0);
401 }
402 
403 /****************************************************************************/
404 /* Sets the PHY link speed.                                                 */
405 /*                                                                          */
406 /* Returns:                                                                 */
407 /*   None                                                                   */
408 /****************************************************************************/
409 static void
410 brgphy_setmedia(struct mii_softc *sc, int media)
411 {
412 	int bmcr = 0, gig;
413 
414 	switch (IFM_SUBTYPE(media)) {
415 	case IFM_2500_SX:
416 		break;
417 	case IFM_1000_SX:
418 	case IFM_1000_T:
419 		bmcr = BRGPHY_S1000;
420 		break;
421 	case IFM_100_TX:
422 		bmcr = BRGPHY_S100;
423 		break;
424 	case IFM_10_T:
425 	default:
426 		bmcr = BRGPHY_S10;
427 		break;
428 	}
429 
430 	if ((media & IFM_FDX) != 0) {
431 		bmcr |= BRGPHY_BMCR_FDX;
432 		gig = BRGPHY_1000CTL_AFD;
433 	} else {
434 		gig = BRGPHY_1000CTL_AHD;
435 	}
436 
437 	/* Force loopback to disconnect PHY from Ethernet medium. */
438 	brgphy_enable_loopback(sc);
439 
440 	PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
441 	PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
442 
443 	if (IFM_SUBTYPE(media) != IFM_1000_T &&
444 	    IFM_SUBTYPE(media) != IFM_1000_SX) {
445 		PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
446 		return;
447 	}
448 
449 	if (IFM_SUBTYPE(media) == IFM_1000_T) {
450 		gig |= BRGPHY_1000CTL_MSE;
451 		if ((media & IFM_ETH_MASTER) != 0)
452 			gig |= BRGPHY_1000CTL_MSC;
453 	}
454 	PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
455 	PHY_WRITE(sc, BRGPHY_MII_BMCR,
456 	    bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
457 }
458 
459 /****************************************************************************/
460 /* Set the media status based on the PHY settings.                          */
461 /*                                                                          */
462 /* Returns:                                                                 */
463 /*   None                                                                   */
464 /****************************************************************************/
465 static void
466 brgphy_status(struct mii_softc *sc)
467 {
468 	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
469 	struct mii_data *mii = sc->mii_pdata;
470 	int aux, bmcr, bmsr, val, xstat;
471 	u_int flowstat;
472 
473 	mii->mii_media_status = IFM_AVALID;
474 	mii->mii_media_active = IFM_ETHER;
475 
476 	bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
477 	bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
478 
479 	if (bmcr & BRGPHY_BMCR_LOOP) {
480 		mii->mii_media_active |= IFM_LOOP;
481 	}
482 
483 	if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
484 	    (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
485 	    (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
486 		/* Erg, still trying, I guess... */
487 		mii->mii_media_active |= IFM_NONE;
488 		return;
489 	}
490 
491 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
492 		/*
493 		 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
494 		 * wedges at least the PHY of BCM5704 (but not others).
495 		 */
496 		flowstat = mii_phy_flowstatus(sc);
497 		xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
498 		aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
499 
500 		/* If copper link is up, get the negotiated speed/duplex. */
501 		if (aux & BRGPHY_AUXSTS_LINK) {
502 			mii->mii_media_status |= IFM_ACTIVE;
503 			switch (aux & BRGPHY_AUXSTS_AN_RES) {
504 			case BRGPHY_RES_1000FD:
505 				mii->mii_media_active |= IFM_1000_T | IFM_FDX; 	break;
506 			case BRGPHY_RES_1000HD:
507 				mii->mii_media_active |= IFM_1000_T | IFM_HDX; 	break;
508 			case BRGPHY_RES_100FD:
509 				mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
510 			case BRGPHY_RES_100T4:
511 				mii->mii_media_active |= IFM_100_T4; break;
512 			case BRGPHY_RES_100HD:
513 				mii->mii_media_active |= IFM_100_TX | IFM_HDX; 	break;
514 			case BRGPHY_RES_10FD:
515 				mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
516 			case BRGPHY_RES_10HD:
517 				mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
518 			default:
519 				mii->mii_media_active |= IFM_NONE; break;
520 			}
521 
522 			if ((mii->mii_media_active & IFM_FDX) != 0)
523 				mii->mii_media_active |= flowstat;
524 
525 			if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
526 			    (xstat & BRGPHY_1000STS_MSR) != 0)
527 				mii->mii_media_active |= IFM_ETH_MASTER;
528 		}
529 	} else {
530 		/* Todo: Add support for flow control. */
531 		/* If serdes link is up, get the negotiated speed/duplex. */
532 		if (bmsr & BRGPHY_BMSR_LINK) {
533 			mii->mii_media_status |= IFM_ACTIVE;
534 		}
535 
536 		/* Check the link speed/duplex based on the PHY type. */
537 		if (bsc->serdes_flags & BRGPHY_5706S) {
538 			mii->mii_media_active |= IFM_1000_SX;
539 
540 			/* If autoneg enabled, read negotiated duplex settings */
541 			if (bmcr & BRGPHY_BMCR_AUTOEN) {
542 				val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
543 				if (val & BRGPHY_SERDES_ANAR_FDX)
544 					mii->mii_media_active |= IFM_FDX;
545 				else
546 					mii->mii_media_active |= IFM_HDX;
547 			}
548 		} else if (bsc->serdes_flags & BRGPHY_5708S) {
549 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
550 			xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
551 
552 			/* Check for MRBE auto-negotiated speed results. */
553 			switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
554 			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
555 				mii->mii_media_active |= IFM_10_FL; break;
556 			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
557 				mii->mii_media_active |= IFM_100_FX; break;
558 			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
559 				mii->mii_media_active |= IFM_1000_SX; break;
560 			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
561 				mii->mii_media_active |= IFM_2500_SX; break;
562 			}
563 
564 			/* Check for MRBE auto-negotiated duplex results. */
565 			if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
566 				mii->mii_media_active |= IFM_FDX;
567 			else
568 				mii->mii_media_active |= IFM_HDX;
569 		} else if (bsc->serdes_flags & BRGPHY_5709S) {
570 			/* Select GP Status Block of the AN MMD, get autoneg results. */
571 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
572 			xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
573 
574 			/* Restore IEEE0 block (assumed in all brgphy(4) code). */
575 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
576 
577 			/* Check for MRBE auto-negotiated speed results. */
578 			switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
579 				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
580 					mii->mii_media_active |= IFM_10_FL; break;
581 				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
582 					mii->mii_media_active |= IFM_100_FX; break;
583 				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
584 					mii->mii_media_active |= IFM_1000_SX; break;
585 				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
586 					mii->mii_media_active |= IFM_2500_SX; break;
587 			}
588 
589 			/* Check for MRBE auto-negotiated duplex results. */
590 			if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
591 				mii->mii_media_active |= IFM_FDX;
592 			else
593 				mii->mii_media_active |= IFM_HDX;
594 		}
595 	}
596 }
597 
598 static void
599 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
600 {
601 	int anar, ktcr = 0;
602 
603 	PHY_RESET(sc);
604 
605 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
606 		anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
607 		if ((media & IFM_FLOW) != 0 ||
608 		    (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
609 			anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
610 		PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
611 		ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
612 		if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
613 			ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
614 		PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
615 		PHY_READ(sc, BRGPHY_MII_1000CTL);
616 	} else {
617 		anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
618 		if ((media & IFM_FLOW) != 0 ||
619 		    (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
620 			anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
621 		PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
622 	}
623 
624 	PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
625 	    BRGPHY_BMCR_STARTNEG);
626 	PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
627 }
628 
629 /* Enable loopback to force the link down. */
630 static void
631 brgphy_enable_loopback(struct mii_softc *sc)
632 {
633 	int i;
634 
635 	PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
636 	for (i = 0; i < 15000; i++) {
637 		if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
638 			break;
639 		DELAY(10);
640 	}
641 }
642 
643 /* Turn off tap power management on 5401. */
644 static void
645 bcm5401_load_dspcode(struct mii_softc *sc)
646 {
647 	static const struct {
648 		int		reg;
649 		uint16_t	val;
650 	} dspcode[] = {
651 		{ BRGPHY_MII_AUXCTL,		0x0c20 },
652 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0012 },
653 		{ BRGPHY_MII_DSP_RW_PORT,	0x1804 },
654 		{ BRGPHY_MII_DSP_ADDR_REG,	0x0013 },
655 		{ BRGPHY_MII_DSP_RW_PORT,	0x1204 },
656 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
657 		{ BRGPHY_MII_DSP_RW_PORT,	0x0132 },
658 		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
659 		{ BRGPHY_MII_DSP_RW_PORT,	0x0232 },
660 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
661 		{ BRGPHY_MII_DSP_RW_PORT,	0x0a20 },
662 		{ 0,				0 },
663 	};
664 	int i;
665 
666 	for (i = 0; dspcode[i].reg != 0; i++)
667 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
668 	DELAY(40);
669 }
670 
671 static void
672 bcm5411_load_dspcode(struct mii_softc *sc)
673 {
674 	static const struct {
675 		int		reg;
676 		uint16_t	val;
677 	} dspcode[] = {
678 		{ 0x1c,				0x8c23 },
679 		{ 0x1c,				0x8ca3 },
680 		{ 0x1c,				0x8c23 },
681 		{ 0,				0 },
682 	};
683 	int i;
684 
685 	for (i = 0; dspcode[i].reg != 0; i++)
686 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
687 }
688 
689 void
690 bcm54k2_load_dspcode(struct mii_softc *sc)
691 {
692 	static const struct {
693 		int		reg;
694 		uint16_t	val;
695 	} dspcode[] = {
696 		{ 4,				0x01e1 },
697 		{ 9,				0x0300 },
698 		{ 0,				0 },
699 	};
700 	int i;
701 
702 	for (i = 0; dspcode[i].reg != 0; i++)
703 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
704 
705 }
706 
707 static void
708 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
709 {
710 	static const struct {
711 		int		reg;
712 		uint16_t	val;
713 	} dspcode[] = {
714 		{ 0x1c,				0x8d68 },
715 		{ 0x1c,				0x8d68 },
716 		{ 0,				0 },
717 	};
718 	int i;
719 
720 	for (i = 0; dspcode[i].reg != 0; i++)
721 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
722 }
723 
724 static void
725 brgphy_fixup_adc_bug(struct mii_softc *sc)
726 {
727 	static const struct {
728 		int		reg;
729 		uint16_t	val;
730 	} dspcode[] = {
731 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
732 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
733 		{ BRGPHY_MII_DSP_RW_PORT,	0x2aaa },
734 		{ 0,				0 },
735 	};
736 	int i;
737 
738 	for (i = 0; dspcode[i].reg != 0; i++)
739 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
740 }
741 
742 static void
743 brgphy_fixup_adjust_trim(struct mii_softc *sc)
744 {
745 	static const struct {
746 		int		reg;
747 		uint16_t	val;
748 	} dspcode[] = {
749 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
750 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
751 		{ BRGPHY_MII_DSP_RW_PORT,	0x110b },
752 		{ BRGPHY_MII_TEST1,			0x0014 },
753 		{ BRGPHY_MII_AUXCTL,		0x0400 },
754 		{ 0,				0 },
755 	};
756 	int i;
757 
758 	for (i = 0; dspcode[i].reg != 0; i++)
759 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
760 }
761 
762 static void
763 brgphy_fixup_ber_bug(struct mii_softc *sc)
764 {
765 	static const struct {
766 		int		reg;
767 		uint16_t	val;
768 	} dspcode[] = {
769 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
770 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
771 		{ BRGPHY_MII_DSP_RW_PORT,	0x310b },
772 		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
773 		{ BRGPHY_MII_DSP_RW_PORT,	0x9506 },
774 		{ BRGPHY_MII_DSP_ADDR_REG,	0x401f },
775 		{ BRGPHY_MII_DSP_RW_PORT,	0x14e2 },
776 		{ BRGPHY_MII_AUXCTL,		0x0400 },
777 		{ 0,				0 },
778 	};
779 	int i;
780 
781 	for (i = 0; dspcode[i].reg != 0; i++)
782 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
783 }
784 
785 static void
786 brgphy_fixup_crc_bug(struct mii_softc *sc)
787 {
788 	static const struct {
789 		int		reg;
790 		uint16_t	val;
791 	} dspcode[] = {
792 		{ BRGPHY_MII_DSP_RW_PORT,	0x0a75 },
793 		{ 0x1c,				0x8c68 },
794 		{ 0x1c,				0x8d68 },
795 		{ 0x1c,				0x8c68 },
796 		{ 0,				0 },
797 	};
798 	int i;
799 
800 	for (i = 0; dspcode[i].reg != 0; i++)
801 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
802 }
803 
804 static void
805 brgphy_fixup_jitter_bug(struct mii_softc *sc)
806 {
807 	static const struct {
808 		int		reg;
809 		uint16_t	val;
810 	} dspcode[] = {
811 		{ BRGPHY_MII_AUXCTL,		0x0c00 },
812 		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
813 		{ BRGPHY_MII_DSP_RW_PORT,	0x010b },
814 		{ BRGPHY_MII_AUXCTL,		0x0400 },
815 		{ 0,				0 },
816 	};
817 	int i;
818 
819 	for (i = 0; dspcode[i].reg != 0; i++)
820 		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
821 }
822 
823 static void
824 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
825 {
826 	uint32_t val;
827 
828 	PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
829 	val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
830 	val &= ~(1 << 8);
831 	PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
832 
833 }
834 
835 static void
836 brgphy_ethernet_wirespeed(struct mii_softc *sc)
837 {
838 	uint32_t	val;
839 
840 	/* Enable Ethernet@WireSpeed. */
841 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
842 	val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
843 	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
844 }
845 
846 static void
847 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
848 {
849 	uint32_t	val;
850 
851 	/* Set or clear jumbo frame settings in the PHY. */
852 	if (mtu > ETHER_MAX_LEN) {
853 		if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
854 			/* BCM5401 PHY cannot read-modify-write. */
855 			PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
856 		} else {
857 			PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
858 			val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
859 			PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
860 			    val | BRGPHY_AUXCTL_LONG_PKT);
861 		}
862 
863 		val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
864 		PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
865 		    val | BRGPHY_PHY_EXTCTL_HIGH_LA);
866 	} else {
867 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
868 		val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
869 		PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
870 		    val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
871 
872 		val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
873 		PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
874 			val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
875 	}
876 }
877 
878 static void
879 brgphy_reset(struct mii_softc *sc)
880 {
881 	struct bge_softc *bge_sc = NULL;
882 	struct bce_softc *bce_sc = NULL;
883 	if_t ifp;
884 	int i, val;
885 
886 	/*
887 	 * Perform a reset.  Note that at least some Broadcom PHYs default to
888 	 * being powered down as well as isolated after a reset but don't work
889 	 * if one or both of these bits are cleared.  However, they just work
890 	 * fine if both bits remain set, so we don't use mii_phy_reset() here.
891 	 */
892 	PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
893 
894 	/* Wait 100ms for it to complete. */
895 	for (i = 0; i < 100; i++) {
896 		if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
897 			break;
898 		DELAY(1000);
899 	}
900 
901 	/* Handle any PHY specific procedures following the reset. */
902 	switch (sc->mii_mpd_oui) {
903 	case MII_OUI_BROADCOM:
904 		switch (sc->mii_mpd_model) {
905 		case MII_MODEL_BROADCOM_BCM5400:
906 			bcm5401_load_dspcode(sc);
907 			break;
908 		case MII_MODEL_BROADCOM_BCM5401:
909 			if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
910 				bcm5401_load_dspcode(sc);
911 			break;
912 		case MII_MODEL_BROADCOM_BCM5411:
913 			bcm5411_load_dspcode(sc);
914 			break;
915 		case MII_MODEL_BROADCOM_BCM54K2:
916 			bcm54k2_load_dspcode(sc);
917 			break;
918 		}
919 		break;
920 	case MII_OUI_BROADCOM3:
921 		switch (sc->mii_mpd_model) {
922 		case MII_MODEL_BROADCOM3_BCM5717C:
923 		case MII_MODEL_BROADCOM3_BCM5719C:
924 		case MII_MODEL_BROADCOM3_BCM5720C:
925 		case MII_MODEL_BROADCOM3_BCM57765:
926 			return;
927 		}
928 		break;
929 	case MII_OUI_BROADCOM4:
930 		return;
931 	}
932 
933 	ifp = sc->mii_pdata->mii_ifp;
934 
935 	/* Find the driver associated with this PHY. */
936 	if (strcmp(if_getdname(ifp), "bge") == 0)	{
937 		bge_sc = if_getsoftc(ifp);
938 	} else if (strcmp(if_getdname(ifp), "bce") == 0) {
939 		bce_sc = if_getsoftc(ifp);
940 	}
941 
942 	if (bge_sc) {
943 		/* Fix up various bugs */
944 		if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
945 			brgphy_fixup_5704_a0_bug(sc);
946 		if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
947 			brgphy_fixup_adc_bug(sc);
948 		if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
949 			brgphy_fixup_adjust_trim(sc);
950 		if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
951 			brgphy_fixup_ber_bug(sc);
952 		if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
953 			brgphy_fixup_crc_bug(sc);
954 		if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
955 			brgphy_fixup_jitter_bug(sc);
956 
957 		if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
958 			brgphy_jumbo_settings(sc, if_getmtu(ifp));
959 
960 		if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
961 			brgphy_ethernet_wirespeed(sc);
962 
963 		/* Enable Link LED on Dell boxes */
964 		if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
965 			PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
966 			    PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
967 			    ~BRGPHY_PHY_EXTCTL_3_LED);
968 		}
969 
970 		/* Adjust output voltage (From Linux driver) */
971 		if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
972 			PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
973 	} else if (bce_sc) {
974 		if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
975 			(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
976 
977 			/* Store autoneg capabilities/results in digital block (Page 0) */
978 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
979 			PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
980 				BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
981 			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
982 
983 			/* Enable fiber mode and autodetection */
984 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
985 				PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
986 				BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
987 				BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
988 
989 			/* Enable parallel detection */
990 			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
991 				PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
992 				BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
993 
994 			/* Advertise 2.5G support through next page during autoneg */
995 			if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
996 				PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
997 					PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
998 					BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
999 
1000 			/* Increase TX signal amplitude */
1001 			if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1002 			    (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1003 			    (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1004 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1005 					BRGPHY_5708S_TX_MISC_PG5);
1006 				PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1007 					PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1008 				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1009 					BRGPHY_5708S_DIG_PG0);
1010 			}
1011 
1012 			/* Backplanes use special driver/pre-driver/pre-emphasis values. */
1013 			if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1014 				(bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1015 					PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1016 						BRGPHY_5708S_TX_MISC_PG5);
1017 					PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1018 						bce_sc->bce_port_hw_cfg &
1019 						BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1020 					PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1021 						BRGPHY_5708S_DIG_PG0);
1022 			}
1023 		} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1024 			(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1025 
1026 			/* Select the SerDes Digital block of the AN MMD. */
1027 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1028 			val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1029 			val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1030 			val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1031 			PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1032 
1033 			/* Select the Over 1G block of the AN MMD. */
1034 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1035 
1036 			/* Enable autoneg "Next Page" to advertise 2.5G support. */
1037 			val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1038 			if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1039 				val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1040 			else
1041 				val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1042 			PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1043 
1044 			/* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1045 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1046 
1047 			/* Enable MRBE speed autoneg. */
1048 			val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1049 			val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1050 			    BRGPHY_MRBE_MSG_PG5_NP_T2;
1051 			PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1052 
1053 			/* Select the Clause 73 User B0 block of the AN MMD. */
1054 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1055 
1056 			/* Enable MRBE speed autoneg. */
1057 			PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1058 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1059 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1060 			    BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1061 
1062 			/* Restore IEEE0 block (assumed in all brgphy(4) code). */
1063 			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1064         } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1065 			if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1066 				(BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1067 				brgphy_fixup_disable_early_dac(sc);
1068 
1069 			brgphy_jumbo_settings(sc, if_getmtu(ifp));
1070 			brgphy_ethernet_wirespeed(sc);
1071 		} else {
1072 			brgphy_fixup_ber_bug(sc);
1073 			brgphy_jumbo_settings(sc, if_getmtu(ifp));
1074 			brgphy_ethernet_wirespeed(sc);
1075 		}
1076 	}
1077 }
1078