1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_var.h> 49 #include <net/ethernet.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include "miidevs.h" 55 56 #include <dev/mii/brgphyreg.h> 57 #include <net/if_arp.h> 58 #include <machine/bus.h> 59 #include <dev/bge/if_bgereg.h> 60 #include <dev/bce/if_bcereg.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 65 #include "miibus_if.h" 66 67 static int brgphy_probe(device_t); 68 static int brgphy_attach(device_t); 69 70 struct brgphy_softc { 71 struct mii_softc mii_sc; 72 int serdes_flags; /* Keeps track of the serdes type used */ 73 #define BRGPHY_5706S 0x0001 74 #define BRGPHY_5708S 0x0002 75 #define BRGPHY_NOANWAIT 0x0004 76 #define BRGPHY_5709S 0x0008 77 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 78 }; 79 80 static device_method_t brgphy_methods[] = { 81 /* device interface */ 82 DEVMETHOD(device_probe, brgphy_probe), 83 DEVMETHOD(device_attach, brgphy_attach), 84 DEVMETHOD(device_detach, mii_phy_detach), 85 DEVMETHOD(device_shutdown, bus_generic_shutdown), 86 DEVMETHOD_END 87 }; 88 89 static devclass_t brgphy_devclass; 90 91 static driver_t brgphy_driver = { 92 "brgphy", 93 brgphy_methods, 94 sizeof(struct brgphy_softc) 95 }; 96 97 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 98 99 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 100 static void brgphy_setmedia(struct mii_softc *, int); 101 static void brgphy_status(struct mii_softc *); 102 static void brgphy_mii_phy_auto(struct mii_softc *, int); 103 static void brgphy_reset(struct mii_softc *); 104 static void brgphy_enable_loopback(struct mii_softc *); 105 static void bcm5401_load_dspcode(struct mii_softc *); 106 static void bcm5411_load_dspcode(struct mii_softc *); 107 static void bcm54k2_load_dspcode(struct mii_softc *); 108 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 109 static void brgphy_fixup_adc_bug(struct mii_softc *); 110 static void brgphy_fixup_adjust_trim(struct mii_softc *); 111 static void brgphy_fixup_ber_bug(struct mii_softc *); 112 static void brgphy_fixup_crc_bug(struct mii_softc *); 113 static void brgphy_fixup_jitter_bug(struct mii_softc *); 114 static void brgphy_ethernet_wirespeed(struct mii_softc *); 115 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 116 117 static const struct mii_phydesc brgphys[] = { 118 MII_PHY_DESC(BROADCOM, BCM5400), 119 MII_PHY_DESC(BROADCOM, BCM5401), 120 MII_PHY_DESC(BROADCOM, BCM5411), 121 MII_PHY_DESC(BROADCOM, BCM54K2), 122 MII_PHY_DESC(BROADCOM, BCM5701), 123 MII_PHY_DESC(BROADCOM, BCM5703), 124 MII_PHY_DESC(BROADCOM, BCM5704), 125 MII_PHY_DESC(BROADCOM, BCM5705), 126 MII_PHY_DESC(BROADCOM, BCM5706), 127 MII_PHY_DESC(BROADCOM, BCM5714), 128 MII_PHY_DESC(BROADCOM, BCM5421), 129 MII_PHY_DESC(BROADCOM, BCM5750), 130 MII_PHY_DESC(BROADCOM, BCM5752), 131 MII_PHY_DESC(BROADCOM, BCM5780), 132 MII_PHY_DESC(BROADCOM, BCM5708C), 133 MII_PHY_DESC(BROADCOM2, BCM5482), 134 MII_PHY_DESC(BROADCOM2, BCM5708S), 135 MII_PHY_DESC(BROADCOM2, BCM5709C), 136 MII_PHY_DESC(BROADCOM2, BCM5709S), 137 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 138 MII_PHY_DESC(BROADCOM2, BCM5722), 139 MII_PHY_DESC(BROADCOM2, BCM5755), 140 MII_PHY_DESC(BROADCOM2, BCM5754), 141 MII_PHY_DESC(BROADCOM2, BCM5761), 142 MII_PHY_DESC(BROADCOM2, BCM5784), 143 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 144 MII_PHY_DESC(BROADCOM2, BCM5785), 145 #endif 146 MII_PHY_DESC(BROADCOM3, BCM5717C), 147 MII_PHY_DESC(BROADCOM3, BCM5719C), 148 MII_PHY_DESC(BROADCOM3, BCM5720C), 149 MII_PHY_DESC(BROADCOM3, BCM57765), 150 MII_PHY_DESC(BROADCOM3, BCM57780), 151 MII_PHY_DESC(BROADCOM4, BCM5725C), 152 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 153 MII_PHY_END 154 }; 155 156 static const struct mii_phy_funcs brgphy_funcs = { 157 brgphy_service, 158 brgphy_status, 159 brgphy_reset 160 }; 161 162 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 163 #define HS21_BCM_CHIPID 0x57081021 164 165 static int 166 detect_hs21(struct bce_softc *bce_sc) 167 { 168 char *sysenv; 169 int found; 170 171 found = 0; 172 if (bce_sc->bce_chipid == HS21_BCM_CHIPID) { 173 sysenv = getenv("smbios.system.product"); 174 if (sysenv != NULL) { 175 if (strncmp(sysenv, HS21_PRODUCT_ID, 176 strlen(HS21_PRODUCT_ID)) == 0) 177 found = 1; 178 freeenv(sysenv); 179 } 180 } 181 return (found); 182 } 183 184 /* Search for our PHY in the list of known PHYs */ 185 static int 186 brgphy_probe(device_t dev) 187 { 188 189 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 190 } 191 192 /* Attach the PHY to the MII bus */ 193 static int 194 brgphy_attach(device_t dev) 195 { 196 struct brgphy_softc *bsc; 197 struct bge_softc *bge_sc = NULL; 198 struct bce_softc *bce_sc = NULL; 199 struct mii_softc *sc; 200 struct ifnet *ifp; 201 202 bsc = device_get_softc(dev); 203 sc = &bsc->mii_sc; 204 205 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 206 &brgphy_funcs, 0); 207 208 bsc->serdes_flags = 0; 209 ifp = sc->mii_pdata->mii_ifp; 210 211 /* Find the MAC driver associated with this PHY. */ 212 if (strcmp(ifp->if_dname, "bge") == 0) 213 bge_sc = ifp->if_softc; 214 else if (strcmp(ifp->if_dname, "bce") == 0) 215 bce_sc = ifp->if_softc; 216 217 /* Handle any special cases based on the PHY ID */ 218 switch (sc->mii_mpd_oui) { 219 case MII_OUI_BROADCOM: 220 switch (sc->mii_mpd_model) { 221 case MII_MODEL_BROADCOM_BCM5706: 222 case MII_MODEL_BROADCOM_BCM5714: 223 /* 224 * The 5464 PHY used in the 5706 supports both copper 225 * and fiber interfaces over GMII. Need to check the 226 * shadow registers to see which mode is actually 227 * in effect, and therefore whether we have 5706C or 228 * 5706S. 229 */ 230 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 231 BRGPHY_SHADOW_1C_MODE_CTRL); 232 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 233 BRGPHY_SHADOW_1C_ENA_1000X) { 234 bsc->serdes_flags |= BRGPHY_5706S; 235 sc->mii_flags |= MIIF_HAVEFIBER; 236 } 237 break; 238 } 239 break; 240 case MII_OUI_BROADCOM2: 241 switch (sc->mii_mpd_model) { 242 case MII_MODEL_BROADCOM2_BCM5708S: 243 bsc->serdes_flags |= BRGPHY_5708S; 244 sc->mii_flags |= MIIF_HAVEFIBER; 245 break; 246 case MII_MODEL_BROADCOM2_BCM5709S: 247 /* 248 * XXX 249 * 5720S and 5709S shares the same PHY id. 250 * Assume 5720S PHY if parent device is bge(4). 251 */ 252 if (bge_sc != NULL) 253 bsc->serdes_flags |= BRGPHY_5708S; 254 else 255 bsc->serdes_flags |= BRGPHY_5709S; 256 sc->mii_flags |= MIIF_HAVEFIBER; 257 break; 258 } 259 break; 260 } 261 262 PHY_RESET(sc); 263 264 /* Read the PHY's capabilities. */ 265 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 266 if (sc->mii_capabilities & BMSR_EXTSTAT) 267 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 268 device_printf(dev, " "); 269 270 #define ADD(m, c) ifmedia_add(&sc->mii_pdata->mii_media, (m), (c), NULL) 271 272 /* Add the supported media types */ 273 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 274 mii_phy_add_media(sc); 275 printf("\n"); 276 } else { 277 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 278 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 279 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 280 printf("1000baseSX-FDX, "); 281 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 282 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 283 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 284 printf("2500baseSX-FDX, "); 285 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 286 (detect_hs21(bce_sc) != 0)) { 287 /* 288 * There appears to be certain silicon revision 289 * in IBM HS21 blades that is having issues with 290 * this driver wating for the auto-negotiation to 291 * complete. This happens with a specific chip id 292 * only and when the 1000baseSX-FDX is the only 293 * mode. Workaround this issue since it's unlikely 294 * to be ever addressed. 295 */ 296 printf("auto-neg workaround, "); 297 bsc->serdes_flags |= BRGPHY_NOANWAIT; 298 } 299 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 300 printf("auto\n"); 301 } 302 303 #undef ADD 304 MIIBUS_MEDIAINIT(sc->mii_dev); 305 return (0); 306 } 307 308 static int 309 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 310 { 311 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 312 int val; 313 314 switch (cmd) { 315 case MII_POLLSTAT: 316 break; 317 case MII_MEDIACHG: 318 /* Todo: Why is this here? Is it really needed? */ 319 PHY_RESET(sc); /* XXX hardware bug work-around */ 320 321 switch (IFM_SUBTYPE(ife->ifm_media)) { 322 case IFM_AUTO: 323 brgphy_mii_phy_auto(sc, ife->ifm_media); 324 break; 325 case IFM_2500_SX: 326 case IFM_1000_SX: 327 case IFM_1000_T: 328 case IFM_100_TX: 329 case IFM_10_T: 330 brgphy_setmedia(sc, ife->ifm_media); 331 break; 332 default: 333 return (EINVAL); 334 } 335 break; 336 case MII_TICK: 337 /* Bail if autoneg isn't in process. */ 338 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 339 sc->mii_ticks = 0; 340 break; 341 } 342 343 /* 344 * Check to see if we have link. If we do, we don't 345 * need to restart the autonegotiation process. 346 */ 347 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 348 if (val & BMSR_LINK) { 349 sc->mii_ticks = 0; /* Reset autoneg timer. */ 350 break; 351 } 352 353 /* Announce link loss right after it happens. */ 354 if (sc->mii_ticks++ == 0) 355 break; 356 357 /* Only retry autonegotiation every mii_anegticks seconds. */ 358 if (sc->mii_ticks <= sc->mii_anegticks) 359 break; 360 361 362 /* Retry autonegotiation */ 363 sc->mii_ticks = 0; 364 brgphy_mii_phy_auto(sc, ife->ifm_media); 365 break; 366 } 367 368 /* Update the media status. */ 369 PHY_STATUS(sc); 370 371 /* 372 * Callback if something changed. Note that we need to poke 373 * the DSP on the Broadcom PHYs if the media changes. 374 */ 375 if (sc->mii_media_active != mii->mii_media_active || 376 sc->mii_media_status != mii->mii_media_status || 377 cmd == MII_MEDIACHG) { 378 switch (sc->mii_mpd_oui) { 379 case MII_OUI_BROADCOM: 380 switch (sc->mii_mpd_model) { 381 case MII_MODEL_BROADCOM_BCM5400: 382 bcm5401_load_dspcode(sc); 383 break; 384 case MII_MODEL_BROADCOM_BCM5401: 385 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 386 bcm5401_load_dspcode(sc); 387 break; 388 case MII_MODEL_BROADCOM_BCM5411: 389 bcm5411_load_dspcode(sc); 390 break; 391 case MII_MODEL_BROADCOM_BCM54K2: 392 bcm54k2_load_dspcode(sc); 393 break; 394 } 395 break; 396 } 397 } 398 mii_phy_update(sc, cmd); 399 return (0); 400 } 401 402 /****************************************************************************/ 403 /* Sets the PHY link speed. */ 404 /* */ 405 /* Returns: */ 406 /* None */ 407 /****************************************************************************/ 408 static void 409 brgphy_setmedia(struct mii_softc *sc, int media) 410 { 411 int bmcr = 0, gig; 412 413 switch (IFM_SUBTYPE(media)) { 414 case IFM_2500_SX: 415 break; 416 case IFM_1000_SX: 417 case IFM_1000_T: 418 bmcr = BRGPHY_S1000; 419 break; 420 case IFM_100_TX: 421 bmcr = BRGPHY_S100; 422 break; 423 case IFM_10_T: 424 default: 425 bmcr = BRGPHY_S10; 426 break; 427 } 428 429 if ((media & IFM_FDX) != 0) { 430 bmcr |= BRGPHY_BMCR_FDX; 431 gig = BRGPHY_1000CTL_AFD; 432 } else { 433 gig = BRGPHY_1000CTL_AHD; 434 } 435 436 /* Force loopback to disconnect PHY from Ethernet medium. */ 437 brgphy_enable_loopback(sc); 438 439 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 440 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 441 442 if (IFM_SUBTYPE(media) != IFM_1000_T && 443 IFM_SUBTYPE(media) != IFM_1000_SX) { 444 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 445 return; 446 } 447 448 if (IFM_SUBTYPE(media) == IFM_1000_T) { 449 gig |= BRGPHY_1000CTL_MSE; 450 if ((media & IFM_ETH_MASTER) != 0) 451 gig |= BRGPHY_1000CTL_MSC; 452 } 453 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 454 PHY_WRITE(sc, BRGPHY_MII_BMCR, 455 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 456 } 457 458 /****************************************************************************/ 459 /* Set the media status based on the PHY settings. */ 460 /* */ 461 /* Returns: */ 462 /* None */ 463 /****************************************************************************/ 464 static void 465 brgphy_status(struct mii_softc *sc) 466 { 467 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 468 struct mii_data *mii = sc->mii_pdata; 469 int aux, bmcr, bmsr, val, xstat; 470 u_int flowstat; 471 472 mii->mii_media_status = IFM_AVALID; 473 mii->mii_media_active = IFM_ETHER; 474 475 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 476 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 477 478 if (bmcr & BRGPHY_BMCR_LOOP) { 479 mii->mii_media_active |= IFM_LOOP; 480 } 481 482 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 483 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 484 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 485 /* Erg, still trying, I guess... */ 486 mii->mii_media_active |= IFM_NONE; 487 return; 488 } 489 490 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 491 /* 492 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 493 * wedges at least the PHY of BCM5704 (but not others). 494 */ 495 flowstat = mii_phy_flowstatus(sc); 496 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 497 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 498 499 /* If copper link is up, get the negotiated speed/duplex. */ 500 if (aux & BRGPHY_AUXSTS_LINK) { 501 mii->mii_media_status |= IFM_ACTIVE; 502 switch (aux & BRGPHY_AUXSTS_AN_RES) { 503 case BRGPHY_RES_1000FD: 504 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 505 case BRGPHY_RES_1000HD: 506 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 507 case BRGPHY_RES_100FD: 508 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 509 case BRGPHY_RES_100T4: 510 mii->mii_media_active |= IFM_100_T4; break; 511 case BRGPHY_RES_100HD: 512 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 513 case BRGPHY_RES_10FD: 514 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 515 case BRGPHY_RES_10HD: 516 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 517 default: 518 mii->mii_media_active |= IFM_NONE; break; 519 } 520 521 if ((mii->mii_media_active & IFM_FDX) != 0) 522 mii->mii_media_active |= flowstat; 523 524 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 525 (xstat & BRGPHY_1000STS_MSR) != 0) 526 mii->mii_media_active |= IFM_ETH_MASTER; 527 } 528 } else { 529 /* Todo: Add support for flow control. */ 530 /* If serdes link is up, get the negotiated speed/duplex. */ 531 if (bmsr & BRGPHY_BMSR_LINK) { 532 mii->mii_media_status |= IFM_ACTIVE; 533 } 534 535 /* Check the link speed/duplex based on the PHY type. */ 536 if (bsc->serdes_flags & BRGPHY_5706S) { 537 mii->mii_media_active |= IFM_1000_SX; 538 539 /* If autoneg enabled, read negotiated duplex settings */ 540 if (bmcr & BRGPHY_BMCR_AUTOEN) { 541 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 542 if (val & BRGPHY_SERDES_ANAR_FDX) 543 mii->mii_media_active |= IFM_FDX; 544 else 545 mii->mii_media_active |= IFM_HDX; 546 } 547 } else if (bsc->serdes_flags & BRGPHY_5708S) { 548 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 549 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 550 551 /* Check for MRBE auto-negotiated speed results. */ 552 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 553 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 554 mii->mii_media_active |= IFM_10_FL; break; 555 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 556 mii->mii_media_active |= IFM_100_FX; break; 557 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 558 mii->mii_media_active |= IFM_1000_SX; break; 559 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 560 mii->mii_media_active |= IFM_2500_SX; break; 561 } 562 563 /* Check for MRBE auto-negotiated duplex results. */ 564 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 565 mii->mii_media_active |= IFM_FDX; 566 else 567 mii->mii_media_active |= IFM_HDX; 568 } else if (bsc->serdes_flags & BRGPHY_5709S) { 569 /* Select GP Status Block of the AN MMD, get autoneg results. */ 570 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 571 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 572 573 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 574 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 575 576 /* Check for MRBE auto-negotiated speed results. */ 577 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 578 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 579 mii->mii_media_active |= IFM_10_FL; break; 580 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 581 mii->mii_media_active |= IFM_100_FX; break; 582 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 583 mii->mii_media_active |= IFM_1000_SX; break; 584 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 585 mii->mii_media_active |= IFM_2500_SX; break; 586 } 587 588 /* Check for MRBE auto-negotiated duplex results. */ 589 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 590 mii->mii_media_active |= IFM_FDX; 591 else 592 mii->mii_media_active |= IFM_HDX; 593 } 594 } 595 } 596 597 static void 598 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 599 { 600 int anar, ktcr = 0; 601 602 PHY_RESET(sc); 603 604 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 605 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 606 if ((media & IFM_FLOW) != 0 || 607 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 608 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 609 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 610 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 611 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 612 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 613 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 614 PHY_READ(sc, BRGPHY_MII_1000CTL); 615 } else { 616 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 617 if ((media & IFM_FLOW) != 0 || 618 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 619 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 620 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 621 } 622 623 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 624 BRGPHY_BMCR_STARTNEG); 625 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 626 } 627 628 /* Enable loopback to force the link down. */ 629 static void 630 brgphy_enable_loopback(struct mii_softc *sc) 631 { 632 int i; 633 634 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 635 for (i = 0; i < 15000; i++) { 636 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 637 break; 638 DELAY(10); 639 } 640 } 641 642 /* Turn off tap power management on 5401. */ 643 static void 644 bcm5401_load_dspcode(struct mii_softc *sc) 645 { 646 static const struct { 647 int reg; 648 uint16_t val; 649 } dspcode[] = { 650 { BRGPHY_MII_AUXCTL, 0x0c20 }, 651 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 652 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 653 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 654 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 655 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 656 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 657 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 658 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 659 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 660 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 661 { 0, 0 }, 662 }; 663 int i; 664 665 for (i = 0; dspcode[i].reg != 0; i++) 666 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 667 DELAY(40); 668 } 669 670 static void 671 bcm5411_load_dspcode(struct mii_softc *sc) 672 { 673 static const struct { 674 int reg; 675 uint16_t val; 676 } dspcode[] = { 677 { 0x1c, 0x8c23 }, 678 { 0x1c, 0x8ca3 }, 679 { 0x1c, 0x8c23 }, 680 { 0, 0 }, 681 }; 682 int i; 683 684 for (i = 0; dspcode[i].reg != 0; i++) 685 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 686 } 687 688 void 689 bcm54k2_load_dspcode(struct mii_softc *sc) 690 { 691 static const struct { 692 int reg; 693 uint16_t val; 694 } dspcode[] = { 695 { 4, 0x01e1 }, 696 { 9, 0x0300 }, 697 { 0, 0 }, 698 }; 699 int i; 700 701 for (i = 0; dspcode[i].reg != 0; i++) 702 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 703 704 } 705 706 static void 707 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 708 { 709 static const struct { 710 int reg; 711 uint16_t val; 712 } dspcode[] = { 713 { 0x1c, 0x8d68 }, 714 { 0x1c, 0x8d68 }, 715 { 0, 0 }, 716 }; 717 int i; 718 719 for (i = 0; dspcode[i].reg != 0; i++) 720 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 721 } 722 723 static void 724 brgphy_fixup_adc_bug(struct mii_softc *sc) 725 { 726 static const struct { 727 int reg; 728 uint16_t val; 729 } dspcode[] = { 730 { BRGPHY_MII_AUXCTL, 0x0c00 }, 731 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 732 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 733 { 0, 0 }, 734 }; 735 int i; 736 737 for (i = 0; dspcode[i].reg != 0; i++) 738 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 739 } 740 741 static void 742 brgphy_fixup_adjust_trim(struct mii_softc *sc) 743 { 744 static const struct { 745 int reg; 746 uint16_t val; 747 } dspcode[] = { 748 { BRGPHY_MII_AUXCTL, 0x0c00 }, 749 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 750 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 751 { BRGPHY_MII_TEST1, 0x0014 }, 752 { BRGPHY_MII_AUXCTL, 0x0400 }, 753 { 0, 0 }, 754 }; 755 int i; 756 757 for (i = 0; dspcode[i].reg != 0; i++) 758 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 759 } 760 761 static void 762 brgphy_fixup_ber_bug(struct mii_softc *sc) 763 { 764 static const struct { 765 int reg; 766 uint16_t val; 767 } dspcode[] = { 768 { BRGPHY_MII_AUXCTL, 0x0c00 }, 769 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 770 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 771 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 772 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 773 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 774 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 775 { BRGPHY_MII_AUXCTL, 0x0400 }, 776 { 0, 0 }, 777 }; 778 int i; 779 780 for (i = 0; dspcode[i].reg != 0; i++) 781 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 782 } 783 784 static void 785 brgphy_fixup_crc_bug(struct mii_softc *sc) 786 { 787 static const struct { 788 int reg; 789 uint16_t val; 790 } dspcode[] = { 791 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 792 { 0x1c, 0x8c68 }, 793 { 0x1c, 0x8d68 }, 794 { 0x1c, 0x8c68 }, 795 { 0, 0 }, 796 }; 797 int i; 798 799 for (i = 0; dspcode[i].reg != 0; i++) 800 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 801 } 802 803 static void 804 brgphy_fixup_jitter_bug(struct mii_softc *sc) 805 { 806 static const struct { 807 int reg; 808 uint16_t val; 809 } dspcode[] = { 810 { BRGPHY_MII_AUXCTL, 0x0c00 }, 811 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 812 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 813 { BRGPHY_MII_AUXCTL, 0x0400 }, 814 { 0, 0 }, 815 }; 816 int i; 817 818 for (i = 0; dspcode[i].reg != 0; i++) 819 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 820 } 821 822 static void 823 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 824 { 825 uint32_t val; 826 827 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 828 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 829 val &= ~(1 << 8); 830 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 831 832 } 833 834 static void 835 brgphy_ethernet_wirespeed(struct mii_softc *sc) 836 { 837 uint32_t val; 838 839 /* Enable Ethernet@WireSpeed. */ 840 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 841 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 842 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 843 } 844 845 static void 846 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 847 { 848 uint32_t val; 849 850 /* Set or clear jumbo frame settings in the PHY. */ 851 if (mtu > ETHER_MAX_LEN) { 852 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 853 /* BCM5401 PHY cannot read-modify-write. */ 854 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 855 } else { 856 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 857 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 858 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 859 val | BRGPHY_AUXCTL_LONG_PKT); 860 } 861 862 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 863 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 864 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 865 } else { 866 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 867 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 868 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 869 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 870 871 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 872 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 873 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 874 } 875 } 876 877 static void 878 brgphy_reset(struct mii_softc *sc) 879 { 880 struct bge_softc *bge_sc = NULL; 881 struct bce_softc *bce_sc = NULL; 882 struct ifnet *ifp; 883 int i, val; 884 885 /* 886 * Perform a reset. Note that at least some Broadcom PHYs default to 887 * being powered down as well as isolated after a reset but don't work 888 * if one or both of these bits are cleared. However, they just work 889 * fine if both bits remain set, so we don't use mii_phy_reset() here. 890 */ 891 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 892 893 /* Wait 100ms for it to complete. */ 894 for (i = 0; i < 100; i++) { 895 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 896 break; 897 DELAY(1000); 898 } 899 900 /* Handle any PHY specific procedures following the reset. */ 901 switch (sc->mii_mpd_oui) { 902 case MII_OUI_BROADCOM: 903 switch (sc->mii_mpd_model) { 904 case MII_MODEL_BROADCOM_BCM5400: 905 bcm5401_load_dspcode(sc); 906 break; 907 case MII_MODEL_BROADCOM_BCM5401: 908 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 909 bcm5401_load_dspcode(sc); 910 break; 911 case MII_MODEL_BROADCOM_BCM5411: 912 bcm5411_load_dspcode(sc); 913 break; 914 case MII_MODEL_BROADCOM_BCM54K2: 915 bcm54k2_load_dspcode(sc); 916 break; 917 } 918 break; 919 case MII_OUI_BROADCOM3: 920 switch (sc->mii_mpd_model) { 921 case MII_MODEL_BROADCOM3_BCM5717C: 922 case MII_MODEL_BROADCOM3_BCM5719C: 923 case MII_MODEL_BROADCOM3_BCM5720C: 924 case MII_MODEL_BROADCOM3_BCM57765: 925 return; 926 } 927 break; 928 case MII_OUI_BROADCOM4: 929 return; 930 } 931 932 ifp = sc->mii_pdata->mii_ifp; 933 934 /* Find the driver associated with this PHY. */ 935 if (strcmp(ifp->if_dname, "bge") == 0) { 936 bge_sc = ifp->if_softc; 937 } else if (strcmp(ifp->if_dname, "bce") == 0) { 938 bce_sc = ifp->if_softc; 939 } 940 941 if (bge_sc) { 942 /* Fix up various bugs */ 943 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 944 brgphy_fixup_5704_a0_bug(sc); 945 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 946 brgphy_fixup_adc_bug(sc); 947 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 948 brgphy_fixup_adjust_trim(sc); 949 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 950 brgphy_fixup_ber_bug(sc); 951 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 952 brgphy_fixup_crc_bug(sc); 953 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 954 brgphy_fixup_jitter_bug(sc); 955 956 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 957 brgphy_jumbo_settings(sc, ifp->if_mtu); 958 959 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 960 brgphy_ethernet_wirespeed(sc); 961 962 /* Enable Link LED on Dell boxes */ 963 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 964 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 965 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 966 ~BRGPHY_PHY_EXTCTL_3_LED); 967 } 968 969 /* Adjust output voltage (From Linux driver) */ 970 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 971 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 972 } else if (bce_sc) { 973 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 974 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 975 976 /* Store autoneg capabilities/results in digital block (Page 0) */ 977 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 978 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 979 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 980 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 981 982 /* Enable fiber mode and autodetection */ 983 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 984 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 985 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 986 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 987 988 /* Enable parallel detection */ 989 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 990 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 991 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 992 993 /* Advertise 2.5G support through next page during autoneg */ 994 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 995 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 996 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 997 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 998 999 /* Increase TX signal amplitude */ 1000 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1001 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1002 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1003 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1004 BRGPHY_5708S_TX_MISC_PG5); 1005 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1006 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1007 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1008 BRGPHY_5708S_DIG_PG0); 1009 } 1010 1011 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1012 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1013 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1014 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1015 BRGPHY_5708S_TX_MISC_PG5); 1016 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1017 bce_sc->bce_port_hw_cfg & 1018 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1019 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1020 BRGPHY_5708S_DIG_PG0); 1021 } 1022 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1023 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1024 1025 /* Select the SerDes Digital block of the AN MMD. */ 1026 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1027 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1028 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1029 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1030 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1031 1032 /* Select the Over 1G block of the AN MMD. */ 1033 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1034 1035 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1036 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1037 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1038 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1039 else 1040 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1041 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1042 1043 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1044 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1045 1046 /* Enable MRBE speed autoneg. */ 1047 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1048 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1049 BRGPHY_MRBE_MSG_PG5_NP_T2; 1050 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1051 1052 /* Select the Clause 73 User B0 block of the AN MMD. */ 1053 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1054 1055 /* Enable MRBE speed autoneg. */ 1056 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1057 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1058 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1059 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1060 1061 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1062 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1063 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1064 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1065 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1066 brgphy_fixup_disable_early_dac(sc); 1067 1068 brgphy_jumbo_settings(sc, ifp->if_mtu); 1069 brgphy_ethernet_wirespeed(sc); 1070 } else { 1071 brgphy_fixup_ber_bug(sc); 1072 brgphy_jumbo_settings(sc, ifp->if_mtu); 1073 brgphy_ethernet_wirespeed(sc); 1074 } 1075 } 1076 } 1077