1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 48 #include <machine/clock.h> 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/brgphyreg.h> 58 #include <net/if_arp.h> 59 #include <machine/bus.h> 60 #include <dev/bge/if_bgereg.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 65 #include "miibus_if.h" 66 67 static int brgphy_probe(device_t); 68 static int brgphy_attach(device_t); 69 70 static device_method_t brgphy_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, brgphy_probe), 73 DEVMETHOD(device_attach, brgphy_attach), 74 DEVMETHOD(device_detach, mii_phy_detach), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 { 0, 0 } 77 }; 78 79 static devclass_t brgphy_devclass; 80 81 static driver_t brgphy_driver = { 82 "brgphy", 83 brgphy_methods, 84 sizeof(struct mii_softc) 85 }; 86 87 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 88 89 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 90 static void brgphy_status(struct mii_softc *); 91 static int brgphy_mii_phy_auto(struct mii_softc *); 92 static void brgphy_reset(struct mii_softc *); 93 static void brgphy_loop(struct mii_softc *); 94 static void bcm5401_load_dspcode(struct mii_softc *); 95 static void bcm5411_load_dspcode(struct mii_softc *); 96 static void bcm5703_load_dspcode(struct mii_softc *); 97 static void bcm5750_load_dspcode(struct mii_softc *); 98 static int brgphy_mii_model; 99 100 static int 101 brgphy_probe(device_t dev) 102 { 103 struct mii_attach_args *ma; 104 105 ma = device_get_ivars(dev); 106 107 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 108 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 109 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 110 return(0); 111 } 112 113 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 114 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 115 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 116 return(0); 117 } 118 119 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 120 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 121 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 122 return(0); 123 } 124 125 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 126 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 127 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 128 return(0); 129 } 130 131 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 132 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 133 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 134 return(0); 135 } 136 137 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 138 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 139 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 140 return(0); 141 } 142 143 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 144 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 145 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 146 return(0); 147 } 148 149 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 150 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750) { 151 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5750); 152 return(0); 153 } 154 155 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 156 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5714) { 157 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5714); 158 return(0); 159 } 160 161 return(ENXIO); 162 } 163 164 static int 165 brgphy_attach(device_t dev) 166 { 167 struct mii_softc *sc; 168 struct mii_attach_args *ma; 169 struct mii_data *mii; 170 const char *sep = ""; 171 struct bge_softc *bge_sc; 172 int fast_ether_only = FALSE; 173 174 sc = device_get_softc(dev); 175 ma = device_get_ivars(dev); 176 sc->mii_dev = device_get_parent(dev); 177 mii = device_get_softc(sc->mii_dev); 178 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 179 180 sc->mii_inst = mii->mii_instance; 181 sc->mii_phy = ma->mii_phyno; 182 sc->mii_service = brgphy_service; 183 sc->mii_pdata = mii; 184 185 sc->mii_flags |= MIIF_NOISOLATE; 186 mii->mii_instance++; 187 188 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 189 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 190 191 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 192 BMCR_ISO); 193 #if 0 194 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 195 BMCR_LOOP|BMCR_S100); 196 #endif 197 198 brgphy_mii_model = MII_MODEL(ma->mii_id2); 199 brgphy_reset(sc); 200 201 202 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 203 sc->mii_capabilities &= ~BMSR_ANEG; 204 device_printf(dev, " "); 205 mii_add_media(sc); 206 207 /* The 590x chips are 10/100 only. */ 208 209 bge_sc = mii->mii_ifp->if_softc; 210 211 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 212 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 213 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 214 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 215 fast_ether_only = TRUE; 216 217 if (fast_ether_only == FALSE) { 218 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 219 sc->mii_inst), BRGPHY_BMCR_FDX); 220 PRINT(", 1000baseTX"); 221 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 222 IFM_FDX, sc->mii_inst), 0); 223 PRINT("1000baseTX-FDX"); 224 } 225 226 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 227 PRINT("auto"); 228 229 printf("\n"); 230 #undef ADD 231 #undef PRINT 232 233 MIIBUS_MEDIAINIT(sc->mii_dev); 234 return(0); 235 } 236 237 static int 238 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 239 { 240 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 241 int reg, speed, gig; 242 243 switch (cmd) { 244 case MII_POLLSTAT: 245 /* 246 * If we're not polling our PHY instance, just return. 247 */ 248 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 249 return (0); 250 break; 251 252 case MII_MEDIACHG: 253 /* 254 * If the media indicates a different PHY instance, 255 * isolate ourselves. 256 */ 257 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 258 reg = PHY_READ(sc, MII_BMCR); 259 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 260 return (0); 261 } 262 263 /* 264 * If the interface is not up, don't do anything. 265 */ 266 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 267 break; 268 269 brgphy_reset(sc); /* XXX hardware bug work-around */ 270 271 switch (IFM_SUBTYPE(ife->ifm_media)) { 272 case IFM_AUTO: 273 #ifdef foo 274 /* 275 * If we're already in auto mode, just return. 276 */ 277 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 278 return (0); 279 #endif 280 (void) brgphy_mii_phy_auto(sc); 281 break; 282 case IFM_1000_T: 283 speed = BRGPHY_S1000; 284 goto setit; 285 case IFM_100_TX: 286 speed = BRGPHY_S100; 287 goto setit; 288 case IFM_10_T: 289 speed = BRGPHY_S10; 290 setit: 291 brgphy_loop(sc); 292 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 293 speed |= BRGPHY_BMCR_FDX; 294 gig = BRGPHY_1000CTL_AFD; 295 } else { 296 gig = BRGPHY_1000CTL_AHD; 297 } 298 299 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 300 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 301 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 302 303 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 304 break; 305 306 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 307 PHY_WRITE(sc, BRGPHY_MII_BMCR, 308 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 309 310 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 311 break; 312 313 /* 314 * When settning the link manually, one side must 315 * be the master and the other the slave. However 316 * ifmedia doesn't give us a good way to specify 317 * this, so we fake it by using one of the LINK 318 * flags. If LINK0 is set, we program the PHY to 319 * be a master, otherwise it's a slave. 320 */ 321 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 322 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 323 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 324 } else { 325 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 326 gig|BRGPHY_1000CTL_MSE); 327 } 328 break; 329 #ifdef foo 330 case IFM_NONE: 331 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 332 break; 333 #endif 334 case IFM_100_T4: 335 default: 336 return (EINVAL); 337 } 338 break; 339 340 case MII_TICK: 341 /* 342 * If we're not currently selected, just return. 343 */ 344 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 345 return (0); 346 347 /* 348 * Is the interface even up? 349 */ 350 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 351 return (0); 352 353 /* 354 * Only used for autonegotiation. 355 */ 356 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 357 break; 358 359 /* 360 * Check to see if we have link. If we do, we don't 361 * need to restart the autonegotiation process. Read 362 * the BMSR twice in case it's latched. 363 */ 364 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 365 if (reg & BRGPHY_AUXSTS_LINK) 366 break; 367 368 /* 369 * Only retry autonegotiation every 5 seconds. 370 */ 371 if (++sc->mii_ticks <= 5) 372 break; 373 374 sc->mii_ticks = 0; 375 brgphy_mii_phy_auto(sc); 376 break; 377 } 378 379 /* Update the media status. */ 380 brgphy_status(sc); 381 382 /* 383 * Callback if something changed. Note that we need to poke 384 * the DSP on the Broadcom PHYs if the media changes. 385 * 386 */ 387 if (sc->mii_media_active != mii->mii_media_active || 388 sc->mii_media_status != mii->mii_media_status || 389 cmd == MII_MEDIACHG) { 390 switch (brgphy_mii_model) { 391 case MII_MODEL_xxBROADCOM_BCM5400: 392 case MII_MODEL_xxBROADCOM_BCM5401: 393 bcm5401_load_dspcode(sc); 394 break; 395 case MII_MODEL_xxBROADCOM_BCM5411: 396 bcm5411_load_dspcode(sc); 397 break; 398 } 399 } 400 mii_phy_update(sc, cmd); 401 return (0); 402 } 403 404 static void 405 brgphy_status(struct mii_softc *sc) 406 { 407 struct mii_data *mii = sc->mii_pdata; 408 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 409 int bmsr, bmcr; 410 411 mii->mii_media_status = IFM_AVALID; 412 mii->mii_media_active = IFM_ETHER; 413 414 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 415 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 416 mii->mii_media_status |= IFM_ACTIVE; 417 418 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 419 420 if (bmcr & BRGPHY_BMCR_LOOP) 421 mii->mii_media_active |= IFM_LOOP; 422 423 if (bmcr & BRGPHY_BMCR_AUTOEN) { 424 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 425 /* Erg, still trying, I guess... */ 426 mii->mii_media_active |= IFM_NONE; 427 return; 428 } 429 430 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 431 BRGPHY_AUXSTS_AN_RES) { 432 case BRGPHY_RES_1000FD: 433 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 434 break; 435 case BRGPHY_RES_1000HD: 436 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 437 break; 438 case BRGPHY_RES_100FD: 439 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 440 break; 441 case BRGPHY_RES_100T4: 442 mii->mii_media_active |= IFM_100_T4; 443 break; 444 case BRGPHY_RES_100HD: 445 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 446 break; 447 case BRGPHY_RES_10FD: 448 mii->mii_media_active |= IFM_10_T | IFM_FDX; 449 break; 450 case BRGPHY_RES_10HD: 451 mii->mii_media_active |= IFM_10_T | IFM_HDX; 452 break; 453 default: 454 mii->mii_media_active |= IFM_NONE; 455 break; 456 } 457 return; 458 } 459 460 mii->mii_media_active = ife->ifm_media; 461 462 return; 463 } 464 465 466 static int 467 brgphy_mii_phy_auto(struct mii_softc *mii) 468 { 469 int ktcr = 0; 470 471 brgphy_loop(mii); 472 brgphy_reset(mii); 473 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 474 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 475 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 476 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 477 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 478 DELAY(1000); 479 PHY_WRITE(mii, BRGPHY_MII_ANAR, 480 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 481 DELAY(1000); 482 PHY_WRITE(mii, BRGPHY_MII_BMCR, 483 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 484 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 485 return (EJUSTRETURN); 486 } 487 488 static void 489 brgphy_loop(struct mii_softc *sc) 490 { 491 u_int32_t bmsr; 492 int i; 493 494 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 495 for (i = 0; i < 15000; i++) { 496 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 497 if (!(bmsr & BRGPHY_BMSR_LINK)) { 498 #if 0 499 device_printf(sc->mii_dev, "looped %d\n", i); 500 #endif 501 break; 502 } 503 DELAY(10); 504 } 505 } 506 507 /* Turn off tap power management on 5401. */ 508 static void 509 bcm5401_load_dspcode(struct mii_softc *sc) 510 { 511 static const struct { 512 int reg; 513 uint16_t val; 514 } dspcode[] = { 515 { BRGPHY_MII_AUXCTL, 0x0c20 }, 516 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 517 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 518 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 519 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 520 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 521 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 522 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 523 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 524 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 525 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 526 { 0, 0 }, 527 }; 528 int i; 529 530 for (i = 0; dspcode[i].reg != 0; i++) 531 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 532 DELAY(40); 533 } 534 535 static void 536 bcm5411_load_dspcode(struct mii_softc *sc) 537 { 538 static const struct { 539 int reg; 540 uint16_t val; 541 } dspcode[] = { 542 { 0x1c, 0x8c23 }, 543 { 0x1c, 0x8ca3 }, 544 { 0x1c, 0x8c23 }, 545 { 0, 0 }, 546 }; 547 int i; 548 549 for (i = 0; dspcode[i].reg != 0; i++) 550 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 551 } 552 553 static void 554 bcm5703_load_dspcode(struct mii_softc *sc) 555 { 556 static const struct { 557 int reg; 558 uint16_t val; 559 } dspcode[] = { 560 { BRGPHY_MII_AUXCTL, 0x0c00 }, 561 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 562 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 563 { 0, 0 }, 564 }; 565 int i; 566 567 for (i = 0; dspcode[i].reg != 0; i++) 568 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 569 } 570 571 static void 572 bcm5704_load_dspcode(struct mii_softc *sc) 573 { 574 static const struct { 575 int reg; 576 u_int16_t val; 577 } dspcode[] = { 578 { 0x1c, 0x8d68 }, 579 { 0x1c, 0x8d68 }, 580 { 0, 0 }, 581 }; 582 int i; 583 584 for (i = 0; dspcode[i].reg != 0; i++) 585 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 586 } 587 588 static void 589 bcm5750_load_dspcode(struct mii_softc *sc) 590 { 591 static const struct { 592 int reg; 593 u_int16_t val; 594 } dspcode[] = { 595 { 0x18, 0x0c00 }, 596 { 0x17, 0x000a }, 597 { 0x15, 0x310b }, 598 { 0x17, 0x201f }, 599 { 0x15, 0x9506 }, 600 { 0x17, 0x401f }, 601 { 0x15, 0x14e2 }, 602 { 0x18, 0x0400 }, 603 { 0, 0 }, 604 }; 605 int i; 606 607 for (i = 0; dspcode[i].reg != 0; i++) 608 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 609 } 610 611 static void 612 brgphy_reset(struct mii_softc *sc) 613 { 614 u_int32_t val; 615 struct ifnet *ifp; 616 struct bge_softc *bge_sc; 617 618 mii_phy_reset(sc); 619 620 switch (brgphy_mii_model) { 621 case MII_MODEL_xxBROADCOM_BCM5400: 622 case MII_MODEL_xxBROADCOM_BCM5401: 623 bcm5401_load_dspcode(sc); 624 break; 625 case MII_MODEL_xxBROADCOM_BCM5411: 626 bcm5411_load_dspcode(sc); 627 break; 628 case MII_MODEL_xxBROADCOM_BCM5703: 629 bcm5703_load_dspcode(sc); 630 break; 631 case MII_MODEL_xxBROADCOM_BCM5704: 632 bcm5704_load_dspcode(sc); 633 break; 634 case MII_MODEL_xxBROADCOM_BCM5750: 635 case MII_MODEL_xxBROADCOM_BCM5714: 636 bcm5750_load_dspcode(sc); 637 break; 638 } 639 640 ifp = sc->mii_pdata->mii_ifp; 641 bge_sc = ifp->if_softc; 642 643 /* 644 * Don't enable Ethernet@WireSpeed for the 5700 or the 645 * 5705 A1 and A2 chips. Make sure we only do this test 646 * on "bge" NICs, since other drivers may use this same 647 * PHY subdriver. 648 */ 649 if (strcmp(ifp->if_dname, "bge") == 0 && 650 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 651 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 652 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)) 653 return; 654 655 /* Enable Ethernet@WireSpeed. */ 656 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 657 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 658 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 659 660 /* Enable Link LED on Dell boxes */ 661 if (bge_sc->bge_no_3_led) { 662 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 663 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 664 & ~BRGPHY_PHY_EXTCTL_3_LED); 665 } 666 } 667