1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 48 49 #include <net/if.h> 50 #include <net/ethernet.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/brgphyreg.h> 58 #include <net/if_arp.h> 59 #include <machine/bus.h> 60 #include <dev/bge/if_bgereg.h> 61 #include <dev/bce/if_bcereg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 66 #include "miibus_if.h" 67 68 static int brgphy_probe(device_t); 69 static int brgphy_attach(device_t); 70 71 static device_method_t brgphy_methods[] = { 72 /* device interface */ 73 DEVMETHOD(device_probe, brgphy_probe), 74 DEVMETHOD(device_attach, brgphy_attach), 75 DEVMETHOD(device_detach, mii_phy_detach), 76 DEVMETHOD(device_shutdown, bus_generic_shutdown), 77 { 0, 0 } 78 }; 79 80 static devclass_t brgphy_devclass; 81 82 static driver_t brgphy_driver = { 83 "brgphy", 84 brgphy_methods, 85 sizeof(struct mii_softc) 86 }; 87 88 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 89 90 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 91 static void brgphy_status(struct mii_softc *); 92 static int brgphy_mii_phy_auto(struct mii_softc *); 93 static void brgphy_reset(struct mii_softc *); 94 static void brgphy_loop(struct mii_softc *); 95 static void bcm5401_load_dspcode(struct mii_softc *); 96 static void bcm5411_load_dspcode(struct mii_softc *); 97 static void bcm5703_load_dspcode(struct mii_softc *); 98 static void bcm5750_load_dspcode(struct mii_softc *); 99 static int brgphy_mii_model; 100 101 static const struct mii_phydesc brgphys[] = { 102 MII_PHY_DESC(xxBROADCOM, BCM5400), 103 MII_PHY_DESC(xxBROADCOM, BCM5401), 104 MII_PHY_DESC(xxBROADCOM, BCM5411), 105 MII_PHY_DESC(xxBROADCOM, BCM5752), 106 MII_PHY_DESC(xxBROADCOM, BCM5701), 107 MII_PHY_DESC(xxBROADCOM, BCM5703), 108 MII_PHY_DESC(xxBROADCOM, BCM5704), 109 MII_PHY_DESC(xxBROADCOM, BCM5705), 110 MII_PHY_DESC(xxBROADCOM, BCM5750), 111 MII_PHY_DESC(xxBROADCOM, BCM5714), 112 MII_PHY_DESC(xxBROADCOM, BCM5780), 113 MII_PHY_DESC(xxBROADCOM, BCM5706C), 114 MII_PHY_DESC(xxBROADCOM, BCM5708C), 115 MII_PHY_END 116 }; 117 118 static int 119 brgphy_probe(device_t dev) 120 { 121 struct mii_attach_args *ma; 122 const struct mii_phydesc *mpd; 123 124 ma = device_get_ivars(dev); 125 mpd = mii_phy_match(ma, brgphys); 126 if (mpd != NULL) { 127 device_set_desc(dev, mpd->mpd_name); 128 return (BUS_PROBE_DEFAULT); 129 } 130 131 return (ENXIO); 132 } 133 134 static int 135 brgphy_attach(device_t dev) 136 { 137 struct mii_softc *sc; 138 struct mii_attach_args *ma; 139 struct mii_data *mii; 140 const char *sep = ""; 141 struct bge_softc *bge_sc = NULL; 142 struct bce_softc *bce_sc = NULL; 143 int fast_ether_only = FALSE; 144 145 sc = device_get_softc(dev); 146 ma = device_get_ivars(dev); 147 sc->mii_dev = device_get_parent(dev); 148 mii = device_get_softc(sc->mii_dev); 149 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 150 151 sc->mii_inst = mii->mii_instance; 152 sc->mii_phy = ma->mii_phyno; 153 sc->mii_service = brgphy_service; 154 sc->mii_pdata = mii; 155 156 sc->mii_flags |= MIIF_NOISOLATE; 157 mii->mii_instance++; 158 159 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 160 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 161 162 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 163 BMCR_ISO); 164 #if 0 165 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 166 BMCR_LOOP|BMCR_S100); 167 #endif 168 169 brgphy_mii_model = MII_MODEL(ma->mii_id2); 170 brgphy_reset(sc); 171 172 173 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 174 sc->mii_capabilities &= ~BMSR_ANEG; 175 device_printf(dev, " "); 176 mii_add_media(sc); 177 178 /* Find the driver associated with this PHY. */ 179 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) { 180 bge_sc = mii->mii_ifp->if_softc; 181 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) { 182 bce_sc = mii->mii_ifp->if_softc; 183 } 184 185 /* The 590x chips are 10/100 only. */ 186 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 187 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 188 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 189 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 190 fast_ether_only = TRUE; 191 192 if (fast_ether_only == FALSE) { 193 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 194 sc->mii_inst), BRGPHY_BMCR_FDX); 195 PRINT(", 1000baseTX"); 196 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 197 IFM_FDX, sc->mii_inst), 0); 198 PRINT("1000baseTX-FDX"); 199 } 200 201 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 202 PRINT("auto"); 203 204 printf("\n"); 205 #undef ADD 206 #undef PRINT 207 208 MIIBUS_MEDIAINIT(sc->mii_dev); 209 return(0); 210 } 211 212 static int 213 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 214 { 215 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 216 int reg, speed, gig; 217 218 switch (cmd) { 219 case MII_POLLSTAT: 220 /* 221 * If we're not polling our PHY instance, just return. 222 */ 223 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 224 return (0); 225 break; 226 227 case MII_MEDIACHG: 228 /* 229 * If the media indicates a different PHY instance, 230 * isolate ourselves. 231 */ 232 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 233 reg = PHY_READ(sc, MII_BMCR); 234 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 235 return (0); 236 } 237 238 /* 239 * If the interface is not up, don't do anything. 240 */ 241 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 242 break; 243 244 brgphy_reset(sc); /* XXX hardware bug work-around */ 245 246 switch (IFM_SUBTYPE(ife->ifm_media)) { 247 case IFM_AUTO: 248 #ifdef foo 249 /* 250 * If we're already in auto mode, just return. 251 */ 252 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 253 return (0); 254 #endif 255 (void) brgphy_mii_phy_auto(sc); 256 break; 257 case IFM_1000_T: 258 speed = BRGPHY_S1000; 259 goto setit; 260 case IFM_100_TX: 261 speed = BRGPHY_S100; 262 goto setit; 263 case IFM_10_T: 264 speed = BRGPHY_S10; 265 setit: 266 brgphy_loop(sc); 267 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 268 speed |= BRGPHY_BMCR_FDX; 269 gig = BRGPHY_1000CTL_AFD; 270 } else { 271 gig = BRGPHY_1000CTL_AHD; 272 } 273 274 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 275 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 276 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 277 278 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 279 break; 280 281 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 282 PHY_WRITE(sc, BRGPHY_MII_BMCR, 283 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 284 285 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 286 break; 287 288 /* 289 * When settning the link manually, one side must 290 * be the master and the other the slave. However 291 * ifmedia doesn't give us a good way to specify 292 * this, so we fake it by using one of the LINK 293 * flags. If LINK0 is set, we program the PHY to 294 * be a master, otherwise it's a slave. 295 */ 296 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 297 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 298 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 299 } else { 300 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 301 gig|BRGPHY_1000CTL_MSE); 302 } 303 break; 304 #ifdef foo 305 case IFM_NONE: 306 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 307 break; 308 #endif 309 case IFM_100_T4: 310 default: 311 return (EINVAL); 312 } 313 break; 314 315 case MII_TICK: 316 /* 317 * If we're not currently selected, just return. 318 */ 319 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 320 return (0); 321 322 /* 323 * Is the interface even up? 324 */ 325 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 326 return (0); 327 328 /* 329 * Only used for autonegotiation. 330 */ 331 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 332 break; 333 334 /* 335 * Check to see if we have link. If we do, we don't 336 * need to restart the autonegotiation process. Read 337 * the BMSR twice in case it's latched. 338 */ 339 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 340 if (reg & BRGPHY_AUXSTS_LINK) 341 break; 342 343 /* 344 * Only retry autonegotiation every 5 seconds. 345 */ 346 if (++sc->mii_ticks <= 5) 347 break; 348 349 sc->mii_ticks = 0; 350 brgphy_mii_phy_auto(sc); 351 break; 352 } 353 354 /* Update the media status. */ 355 brgphy_status(sc); 356 357 /* 358 * Callback if something changed. Note that we need to poke 359 * the DSP on the Broadcom PHYs if the media changes. 360 * 361 */ 362 if (sc->mii_media_active != mii->mii_media_active || 363 sc->mii_media_status != mii->mii_media_status || 364 cmd == MII_MEDIACHG) { 365 switch (brgphy_mii_model) { 366 case MII_MODEL_xxBROADCOM_BCM5400: 367 case MII_MODEL_xxBROADCOM_BCM5401: 368 bcm5401_load_dspcode(sc); 369 break; 370 case MII_MODEL_xxBROADCOM_BCM5411: 371 bcm5411_load_dspcode(sc); 372 break; 373 } 374 } 375 mii_phy_update(sc, cmd); 376 return (0); 377 } 378 379 static void 380 brgphy_status(struct mii_softc *sc) 381 { 382 struct mii_data *mii = sc->mii_pdata; 383 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 384 int bmsr, bmcr; 385 386 mii->mii_media_status = IFM_AVALID; 387 mii->mii_media_active = IFM_ETHER; 388 389 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 390 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 391 mii->mii_media_status |= IFM_ACTIVE; 392 393 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 394 395 if (bmcr & BRGPHY_BMCR_LOOP) 396 mii->mii_media_active |= IFM_LOOP; 397 398 if (bmcr & BRGPHY_BMCR_AUTOEN) { 399 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 400 /* Erg, still trying, I guess... */ 401 mii->mii_media_active |= IFM_NONE; 402 return; 403 } 404 405 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 406 BRGPHY_AUXSTS_AN_RES) { 407 case BRGPHY_RES_1000FD: 408 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 409 break; 410 case BRGPHY_RES_1000HD: 411 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 412 break; 413 case BRGPHY_RES_100FD: 414 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 415 break; 416 case BRGPHY_RES_100T4: 417 mii->mii_media_active |= IFM_100_T4; 418 break; 419 case BRGPHY_RES_100HD: 420 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 421 break; 422 case BRGPHY_RES_10FD: 423 mii->mii_media_active |= IFM_10_T | IFM_FDX; 424 break; 425 case BRGPHY_RES_10HD: 426 mii->mii_media_active |= IFM_10_T | IFM_HDX; 427 break; 428 default: 429 mii->mii_media_active |= IFM_NONE; 430 break; 431 } 432 return; 433 } 434 435 mii->mii_media_active = ife->ifm_media; 436 437 return; 438 } 439 440 441 static int 442 brgphy_mii_phy_auto(struct mii_softc *mii) 443 { 444 int ktcr = 0; 445 446 brgphy_loop(mii); 447 brgphy_reset(mii); 448 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 449 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 450 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 451 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 452 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 453 DELAY(1000); 454 PHY_WRITE(mii, BRGPHY_MII_ANAR, 455 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 456 DELAY(1000); 457 PHY_WRITE(mii, BRGPHY_MII_BMCR, 458 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 459 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 460 return (EJUSTRETURN); 461 } 462 463 static void 464 brgphy_loop(struct mii_softc *sc) 465 { 466 u_int32_t bmsr; 467 int i; 468 469 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 470 for (i = 0; i < 15000; i++) { 471 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 472 if (!(bmsr & BRGPHY_BMSR_LINK)) { 473 #if 0 474 device_printf(sc->mii_dev, "looped %d\n", i); 475 #endif 476 break; 477 } 478 DELAY(10); 479 } 480 } 481 482 /* Turn off tap power management on 5401. */ 483 static void 484 bcm5401_load_dspcode(struct mii_softc *sc) 485 { 486 static const struct { 487 int reg; 488 uint16_t val; 489 } dspcode[] = { 490 { BRGPHY_MII_AUXCTL, 0x0c20 }, 491 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 492 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 493 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 494 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 495 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 496 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 497 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 498 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 499 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 500 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 501 { 0, 0 }, 502 }; 503 int i; 504 505 for (i = 0; dspcode[i].reg != 0; i++) 506 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 507 DELAY(40); 508 } 509 510 static void 511 bcm5411_load_dspcode(struct mii_softc *sc) 512 { 513 static const struct { 514 int reg; 515 uint16_t val; 516 } dspcode[] = { 517 { 0x1c, 0x8c23 }, 518 { 0x1c, 0x8ca3 }, 519 { 0x1c, 0x8c23 }, 520 { 0, 0 }, 521 }; 522 int i; 523 524 for (i = 0; dspcode[i].reg != 0; i++) 525 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 526 } 527 528 static void 529 bcm5703_load_dspcode(struct mii_softc *sc) 530 { 531 static const struct { 532 int reg; 533 uint16_t val; 534 } dspcode[] = { 535 { BRGPHY_MII_AUXCTL, 0x0c00 }, 536 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 537 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 538 { 0, 0 }, 539 }; 540 int i; 541 542 for (i = 0; dspcode[i].reg != 0; i++) 543 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 544 } 545 546 static void 547 bcm5704_load_dspcode(struct mii_softc *sc) 548 { 549 static const struct { 550 int reg; 551 u_int16_t val; 552 } dspcode[] = { 553 { 0x1c, 0x8d68 }, 554 { 0x1c, 0x8d68 }, 555 { 0, 0 }, 556 }; 557 int i; 558 559 for (i = 0; dspcode[i].reg != 0; i++) 560 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 561 } 562 563 static void 564 bcm5750_load_dspcode(struct mii_softc *sc) 565 { 566 static const struct { 567 int reg; 568 u_int16_t val; 569 } dspcode[] = { 570 { 0x18, 0x0c00 }, 571 { 0x17, 0x000a }, 572 { 0x15, 0x310b }, 573 { 0x17, 0x201f }, 574 { 0x15, 0x9506 }, 575 { 0x17, 0x401f }, 576 { 0x15, 0x14e2 }, 577 { 0x18, 0x0400 }, 578 { 0, 0 }, 579 }; 580 int i; 581 582 for (i = 0; dspcode[i].reg != 0; i++) 583 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 584 } 585 586 static void 587 brgphy_reset(struct mii_softc *sc) 588 { 589 u_int32_t val; 590 struct ifnet *ifp; 591 struct bge_softc *bge_sc = NULL; 592 struct bce_softc *bce_sc = NULL; 593 594 mii_phy_reset(sc); 595 596 switch (brgphy_mii_model) { 597 case MII_MODEL_xxBROADCOM_BCM5400: 598 case MII_MODEL_xxBROADCOM_BCM5401: 599 bcm5401_load_dspcode(sc); 600 break; 601 case MII_MODEL_xxBROADCOM_BCM5411: 602 bcm5411_load_dspcode(sc); 603 break; 604 case MII_MODEL_xxBROADCOM_BCM5703: 605 bcm5703_load_dspcode(sc); 606 break; 607 case MII_MODEL_xxBROADCOM_BCM5704: 608 bcm5704_load_dspcode(sc); 609 break; 610 case MII_MODEL_xxBROADCOM_BCM5750: 611 case MII_MODEL_xxBROADCOM_BCM5752: 612 case MII_MODEL_xxBROADCOM_BCM5714: 613 case MII_MODEL_xxBROADCOM_BCM5780: 614 case MII_MODEL_xxBROADCOM_BCM5706C: 615 case MII_MODEL_xxBROADCOM_BCM5708C: 616 bcm5750_load_dspcode(sc); 617 break; 618 } 619 620 ifp = sc->mii_pdata->mii_ifp; 621 622 /* Find the driver associated with this PHY. */ 623 if (strcmp(ifp->if_dname, "bge") == 0) { 624 bge_sc = ifp->if_softc; 625 } else if (strcmp(ifp->if_dname, "bce") == 0) { 626 bce_sc = ifp->if_softc; 627 } 628 629 /* Handle any NetXtreme/bge workarounds. */ 630 if (bge_sc) { 631 /* 632 * Don't enable Ethernet@WireSpeed for the 5700 or the 633 * 5705 A1 and A2 chips. Make sure we only do this test 634 * on "bge" NICs, since other drivers may use this same 635 * PHY subdriver. 636 */ 637 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 638 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 639 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2) 640 return; 641 642 /* Enable Ethernet@WireSpeed. */ 643 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 644 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 645 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 646 647 /* Enable Link LED on Dell boxes */ 648 if (bge_sc->bge_flags & BGE_FLAG_NO3LED) { 649 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 650 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 651 & ~BRGPHY_PHY_EXTCTL_3_LED); 652 } 653 } else if (bce_sc) { 654 655 /* Set or clear jumbo frame settings in the PHY. */ 656 if (ifp->if_mtu > ETHER_MAX_LEN) { 657 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 658 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 659 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 660 val | BRGPHY_AUXCTL_LONG_PKT); 661 662 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 663 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 664 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 665 } else { 666 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 667 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 668 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 669 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 670 671 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 672 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 673 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 674 } 675 676 /* Enable Ethernet@Wirespeed */ 677 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 678 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 679 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4))); 680 } 681 } 682