1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/brgphyreg.h> 56 #include <net/if_arp.h> 57 #include <machine/bus.h> 58 #include <dev/bge/if_bgereg.h> 59 #include <dev/bce/if_bcereg.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 #include "miibus_if.h" 65 66 static int brgphy_probe(device_t); 67 static int brgphy_attach(device_t); 68 69 struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int mii_oui; 72 int mii_model; 73 int mii_rev; 74 int serdes_flags; /* Keeps track of the serdes type used */ 75 #define BRGPHY_5706S 0x0001 76 #define BRGPHY_5708S 0x0002 77 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 78 }; 79 80 static device_method_t brgphy_methods[] = { 81 /* device interface */ 82 DEVMETHOD(device_probe, brgphy_probe), 83 DEVMETHOD(device_attach, brgphy_attach), 84 DEVMETHOD(device_detach, mii_phy_detach), 85 DEVMETHOD(device_shutdown, bus_generic_shutdown), 86 { 0, 0 } 87 }; 88 89 static devclass_t brgphy_devclass; 90 91 static driver_t brgphy_driver = { 92 "brgphy", 93 brgphy_methods, 94 sizeof(struct brgphy_softc) 95 }; 96 97 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 98 99 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 100 static void brgphy_setmedia(struct mii_softc *, int, int); 101 static void brgphy_status(struct mii_softc *); 102 static void brgphy_mii_phy_auto(struct mii_softc *); 103 static void brgphy_reset(struct mii_softc *); 104 static void brgphy_enable_loopback(struct mii_softc *); 105 static void bcm5401_load_dspcode(struct mii_softc *); 106 static void bcm5411_load_dspcode(struct mii_softc *); 107 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 108 static void brgphy_fixup_adc_bug(struct mii_softc *); 109 static void brgphy_fixup_adjust_trim(struct mii_softc *); 110 static void brgphy_fixup_ber_bug(struct mii_softc *); 111 static void brgphy_fixup_crc_bug(struct mii_softc *); 112 static void brgphy_fixup_jitter_bug(struct mii_softc *); 113 static void brgphy_ethernet_wirespeed(struct mii_softc *); 114 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 115 116 static const struct mii_phydesc brgphys[] = { 117 MII_PHY_DESC(xxBROADCOM, BCM5400), 118 MII_PHY_DESC(xxBROADCOM, BCM5401), 119 MII_PHY_DESC(xxBROADCOM, BCM5411), 120 MII_PHY_DESC(xxBROADCOM, BCM5701), 121 MII_PHY_DESC(xxBROADCOM, BCM5703), 122 MII_PHY_DESC(xxBROADCOM, BCM5704), 123 MII_PHY_DESC(xxBROADCOM, BCM5705), 124 MII_PHY_DESC(xxBROADCOM, BCM5706), 125 MII_PHY_DESC(xxBROADCOM, BCM5714), 126 MII_PHY_DESC(xxBROADCOM, BCM5750), 127 MII_PHY_DESC(xxBROADCOM, BCM5752), 128 MII_PHY_DESC(xxBROADCOM, BCM5754), 129 MII_PHY_DESC(xxBROADCOM, BCM5780), 130 MII_PHY_DESC(xxBROADCOM, BCM5708C), 131 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 132 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 133 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), 134 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), 135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), 136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), 137 MII_PHY_DESC(BROADCOM2, BCM5906), 138 MII_PHY_END 139 }; 140 141 142 /* Search for our PHY in the list of known PHYs */ 143 static int 144 brgphy_probe(device_t dev) 145 { 146 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 147 } 148 149 /* Attach the PHY to the MII bus */ 150 static int 151 brgphy_attach(device_t dev) 152 { 153 struct brgphy_softc *bsc; 154 struct bge_softc *bge_sc = NULL; 155 struct bce_softc *bce_sc = NULL; 156 struct mii_softc *sc; 157 struct mii_attach_args *ma; 158 struct mii_data *mii; 159 struct ifnet *ifp; 160 int fast_ether; 161 162 bsc = device_get_softc(dev); 163 sc = &bsc->mii_sc; 164 ma = device_get_ivars(dev); 165 sc->mii_dev = device_get_parent(dev); 166 mii = device_get_softc(sc->mii_dev); 167 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 168 169 /* Initialize mii_softc structure */ 170 sc->mii_inst = mii->mii_instance; 171 sc->mii_phy = ma->mii_phyno; 172 sc->mii_service = brgphy_service; 173 sc->mii_pdata = mii; 174 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 175 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 176 mii->mii_instance++; 177 178 /* Initialize brgphy_softc structure */ 179 bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 180 bsc->mii_model = MII_MODEL(ma->mii_id2); 181 bsc->mii_rev = MII_REV(ma->mii_id2); 182 bsc->serdes_flags = 0; 183 184 fast_ether = 0; 185 186 if (bootverbose) 187 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", 188 bsc->mii_oui, bsc->mii_model, bsc->mii_rev); 189 190 /* Handle any special cases based on the PHY ID */ 191 switch (bsc->mii_oui) { 192 case MII_OUI_BROADCOM: 193 case MII_OUI_BROADCOM2: 194 break; 195 case MII_OUI_xxBROADCOM: 196 switch (bsc->mii_model) { 197 case MII_MODEL_xxBROADCOM_BCM5706: 198 /* 199 * The 5464 PHY used in the 5706 supports both copper 200 * and fiber interfaces over GMII. Need to check the 201 * shadow registers to see which mode is actually 202 * in effect, and therefore whether we have 5706C or 203 * 5706S. 204 */ 205 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 206 BRGPHY_SHADOW_1C_MODE_CTRL); 207 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 208 BRGPHY_SHADOW_1C_ENA_1000X) { 209 bsc->serdes_flags |= BRGPHY_5706S; 210 sc->mii_flags |= MIIF_HAVEFIBER; 211 } 212 break; 213 } break; 214 case MII_OUI_xxBROADCOM_ALT1: 215 switch (bsc->mii_model) { 216 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: 217 bsc->serdes_flags |= BRGPHY_5708S; 218 sc->mii_flags |= MIIF_HAVEFIBER; 219 break; 220 } break; 221 default: 222 device_printf(dev, "Unrecognized OUI for PHY!\n"); 223 } 224 225 ifp = sc->mii_pdata->mii_ifp; 226 227 /* Find the MAC driver associated with this PHY. */ 228 if (strcmp(ifp->if_dname, "bge") == 0) { 229 bge_sc = ifp->if_softc; 230 } else if (strcmp(ifp->if_dname, "bce") == 0) { 231 bce_sc = ifp->if_softc; 232 } 233 234 /* Todo: Need to add additional controllers such as 5906 & 5787F */ 235 /* The 590x chips are 10/100 only. */ 236 if (bge_sc && 237 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 238 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 239 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 || 240 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 || 241 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) { 242 fast_ether = 1; 243 sc->mii_anegticks = MII_ANEGTICKS; 244 } 245 246 brgphy_reset(sc); 247 248 /* Read the PHY's capabilities. */ 249 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 250 if (sc->mii_capabilities & BMSR_EXTSTAT) 251 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 252 device_printf(dev, " "); 253 254 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 255 256 /* Create an instance of Ethernet media. */ 257 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO); 258 259 /* Add the supported media types */ 260 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 261 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), 262 BRGPHY_S10); 263 printf("10baseT, "); 264 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst), 265 BRGPHY_S10 | BRGPHY_BMCR_FDX); 266 printf("10baseT-FDX, "); 267 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), 268 BRGPHY_S100); 269 printf("100baseTX, "); 270 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst), 271 BRGPHY_S100 | BRGPHY_BMCR_FDX); 272 printf("100baseTX-FDX, "); 273 if (fast_ether == 0) { 274 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 275 BRGPHY_S1000); 276 printf("1000baseT, "); 277 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 278 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 279 printf("1000baseT-FDX, "); 280 } 281 } else { 282 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 283 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 284 printf("1000baseSX-FDX, "); 285 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 286 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 287 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 288 printf("2500baseSX-FDX, "); 289 } 290 } 291 292 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 293 printf("auto\n"); 294 295 #undef ADD 296 MIIBUS_MEDIAINIT(sc->mii_dev); 297 return (0); 298 } 299 300 static int 301 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 302 { 303 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 304 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 305 int error = 0; 306 int val; 307 308 switch (cmd) { 309 case MII_POLLSTAT: 310 /* If we're not polling our PHY instance, just return. */ 311 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 312 goto brgphy_service_exit; 313 break; 314 case MII_MEDIACHG: 315 /* 316 * If the media indicates a different PHY instance, 317 * isolate ourselves. 318 */ 319 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 320 PHY_WRITE(sc, MII_BMCR, 321 PHY_READ(sc, MII_BMCR) | BMCR_ISO); 322 goto brgphy_service_exit; 323 } 324 325 /* If the interface is not up, don't do anything. */ 326 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 327 break; 328 329 /* Todo: Why is this here? Is it really needed? */ 330 brgphy_reset(sc); /* XXX hardware bug work-around */ 331 332 switch (IFM_SUBTYPE(ife->ifm_media)) { 333 case IFM_AUTO: 334 brgphy_mii_phy_auto(sc); 335 break; 336 case IFM_2500_SX: 337 case IFM_1000_SX: 338 case IFM_1000_T: 339 case IFM_100_TX: 340 case IFM_10_T: 341 brgphy_setmedia(sc, ife->ifm_media, 342 mii->mii_ifp->if_flags & IFF_LINK0); 343 break; 344 default: 345 error = EINVAL; 346 goto brgphy_service_exit; 347 } 348 break; 349 case MII_TICK: 350 /* Bail if we're not currently selected. */ 351 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 352 goto brgphy_service_exit; 353 354 /* Bail if the interface isn't up. */ 355 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 356 goto brgphy_service_exit; 357 358 359 /* Bail if autoneg isn't in process. */ 360 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 361 sc->mii_ticks = 0; 362 break; 363 } 364 365 /* 366 * Check to see if we have link. If we do, we don't 367 * need to restart the autonegotiation process. 368 */ 369 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 370 if (val & BMSR_LINK) { 371 sc->mii_ticks = 0; /* Reset autoneg timer. */ 372 break; 373 } 374 375 /* Announce link loss right after it happens. */ 376 if (sc->mii_ticks++ == 0) 377 break; 378 379 /* Only retry autonegotiation every mii_anegticks seconds. */ 380 if (sc->mii_ticks <= sc->mii_anegticks) 381 break; 382 383 384 /* Retry autonegotiation */ 385 sc->mii_ticks = 0; 386 brgphy_mii_phy_auto(sc); 387 break; 388 } 389 390 /* Update the media status. */ 391 brgphy_status(sc); 392 393 /* 394 * Callback if something changed. Note that we need to poke 395 * the DSP on the Broadcom PHYs if the media changes. 396 */ 397 if (sc->mii_media_active != mii->mii_media_active || 398 sc->mii_media_status != mii->mii_media_status || 399 cmd == MII_MEDIACHG) { 400 switch (bsc->mii_oui) { 401 case MII_OUI_BROADCOM: 402 break; 403 case MII_OUI_xxBROADCOM: 404 switch (bsc->mii_model) { 405 case MII_MODEL_xxBROADCOM_BCM5400: 406 bcm5401_load_dspcode(sc); 407 break; 408 case MII_MODEL_xxBROADCOM_BCM5401: 409 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 410 bcm5401_load_dspcode(sc); 411 break; 412 case MII_MODEL_xxBROADCOM_BCM5411: 413 bcm5411_load_dspcode(sc); 414 break; 415 } 416 break; 417 case MII_OUI_xxBROADCOM_ALT1: 418 break; 419 } 420 } 421 mii_phy_update(sc, cmd); 422 brgphy_service_exit: 423 return (error); 424 } 425 426 427 /****************************************************************************/ 428 /* Sets the PHY link speed. */ 429 /* */ 430 /* Returns: */ 431 /* None */ 432 /****************************************************************************/ 433 static void 434 brgphy_setmedia(struct mii_softc *sc, int media, int master) 435 { 436 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 437 int bmcr = 0, gig; 438 439 /* Calculate the value for the BMCR register. */ 440 switch (IFM_SUBTYPE(media)) { 441 case IFM_2500_SX: 442 break; 443 case IFM_1000_SX: 444 case IFM_1000_T: 445 bmcr = BRGPHY_S1000; 446 break; 447 case IFM_100_TX: 448 bmcr = BRGPHY_S100; 449 break; 450 case IFM_10_T: 451 default: 452 bmcr = BRGPHY_S10; 453 break; 454 } 455 456 /* Calculate duplex settings for 1000BasetT/1000BaseX. */ 457 if ((media & IFM_GMASK) == IFM_FDX) { 458 bmcr |= BRGPHY_BMCR_FDX; 459 gig = BRGPHY_1000CTL_AFD; 460 } else { 461 gig = BRGPHY_1000CTL_AHD; 462 } 463 464 /* Force loopback to disconnect PHY for Ethernet medium. */ 465 brgphy_enable_loopback(sc); 466 467 /* Disable 1000BaseT advertisements. */ 468 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 469 /* Disable 10/100 advertisements. */ 470 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 471 /* Write forced link speed. */ 472 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 473 474 /* If 10/100 only then configuration is complete. */ 475 if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX)) 476 goto brgphy_setmedia_exit; 477 478 /* Set duplex speed advertisement for 1000BaseT/1000BaseX. */ 479 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 480 /* Restart auto-negotiation for 1000BaseT/1000BaseX. */ 481 PHY_WRITE(sc, BRGPHY_MII_BMCR, 482 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 483 484 /* If not 5701 PHY then configuration is complete. */ 485 if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 486 goto brgphy_setmedia_exit; 487 488 /* 489 * When setting the link manually, one side must be the master and 490 * the other the slave. However ifmedia doesn't give us a good way 491 * to specify this, so we fake it by using one of the LINK flags. 492 * If LINK0 is set, we program the PHY to be a master, otherwise 493 * it's a slave. 494 */ 495 if (master) { 496 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 497 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); 498 } else { 499 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 500 gig | BRGPHY_1000CTL_MSE); 501 } 502 503 brgphy_setmedia_exit: 504 return; 505 } 506 507 /****************************************************************************/ 508 /* Set the media status based on the PHY settings. */ 509 /* IFM_FLAG0 = 0 (RX flow control disabled) | 1 (enabled) */ 510 /* IFM_FLAG1 = 0 (TX flow control disabled) | 1 (enabled) */ 511 /* */ 512 /* Returns: */ 513 /* None */ 514 /****************************************************************************/ 515 static void 516 brgphy_status(struct mii_softc *sc) 517 { 518 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 519 struct mii_data *mii = sc->mii_pdata; 520 int aux, bmcr, bmsr, anar, anlpar, xstat, val; 521 522 523 mii->mii_media_status = IFM_AVALID; 524 mii->mii_media_active = IFM_ETHER; 525 526 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 527 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 528 anar = PHY_READ(sc, BRGPHY_MII_ANAR); 529 anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR); 530 531 /* Loopback is enabled. */ 532 if (bmcr & BRGPHY_BMCR_LOOP) { 533 534 mii->mii_media_active |= IFM_LOOP; 535 } 536 537 /* Autoneg is still in progress. */ 538 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 539 (bmsr & BRGPHY_BMSR_ACOMP) == 0) { 540 /* Erg, still trying, I guess... */ 541 mii->mii_media_active |= IFM_NONE; 542 goto brgphy_status_exit; 543 } 544 545 /* Autoneg is enabled and complete, link should be up. */ 546 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 547 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 548 549 /* If copper link is up, get the negotiated speed/duplex. */ 550 if (aux & BRGPHY_AUXSTS_LINK) { 551 mii->mii_media_status |= IFM_ACTIVE; 552 switch (aux & BRGPHY_AUXSTS_AN_RES) { 553 case BRGPHY_RES_1000FD: 554 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 555 case BRGPHY_RES_1000HD: 556 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 557 case BRGPHY_RES_100FD: 558 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 559 case BRGPHY_RES_100T4: 560 mii->mii_media_active |= IFM_100_T4; break; 561 case BRGPHY_RES_100HD: 562 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 563 case BRGPHY_RES_10FD: 564 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 565 case BRGPHY_RES_10HD: 566 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 567 default: 568 mii->mii_media_active |= IFM_NONE; break; 569 } 570 } 571 } else { 572 /* If serdes link is up, get the negotiated speed/duplex. */ 573 if (bmsr & BRGPHY_BMSR_LINK) { 574 mii->mii_media_status |= IFM_ACTIVE; 575 } 576 577 /* Check the link speed/duplex based on the PHY type. */ 578 if (bsc->serdes_flags & BRGPHY_5706S) { 579 mii->mii_media_active |= IFM_1000_SX; 580 581 /* If autoneg enabled, read negotiated duplex settings */ 582 if (bmcr & BRGPHY_BMCR_AUTOEN) { 583 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 584 if (val & BRGPHY_SERDES_ANAR_FDX) 585 mii->mii_media_active |= IFM_FDX; 586 else 587 mii->mii_media_active |= IFM_HDX; 588 } 589 590 } else if (bsc->serdes_flags & BRGPHY_5708S) { 591 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 592 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 593 594 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 595 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 596 mii->mii_media_active |= IFM_10_FL; break; 597 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 598 mii->mii_media_active |= IFM_100_FX; break; 599 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 600 mii->mii_media_active |= IFM_1000_SX; break; 601 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 602 mii->mii_media_active |= IFM_2500_SX; break; 603 } 604 605 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 606 mii->mii_media_active |= IFM_FDX; 607 else 608 mii->mii_media_active |= IFM_HDX; 609 } 610 } 611 612 #if 0 613 /* Todo: Change bge/bce to use these settings. */ 614 615 /* Fetch flow control settings from the PHY */ 616 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 617 /* Set FLAG0 is RX is enabled and FLAG1 if TX is enabled */ 618 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) { 619 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; 620 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) && 621 (anlpar & BRPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 622 mii->mii_media_active |= IFM_FLAG1; 623 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) && 624 !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 625 mii->mii_media_active |= IFM_FLAG0; 626 } 627 } 628 629 /* Todo: Add support for fiber settings too. */ 630 #endif 631 632 633 brgphy_status_exit: 634 return; 635 } 636 637 static void 638 brgphy_mii_phy_auto(struct mii_softc *sc) 639 { 640 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 641 int ktcr = 0; 642 643 brgphy_reset(sc); 644 645 /* Enable flow control in the advertisement register. */ 646 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 647 /* Pause capability advertisement (pause capable & asymmetric) */ 648 PHY_WRITE(sc, BRGPHY_MII_ANAR, 649 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA | 650 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC); 651 } else { 652 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX | 653 BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE); 654 } 655 656 /* Enable speed in the 1000baseT control register */ 657 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 658 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 659 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 660 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 661 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 662 663 /* Start autonegotiation */ 664 PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 665 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 666 667 } 668 669 670 /* Enable loopback to force the link down. */ 671 static void 672 brgphy_enable_loopback(struct mii_softc *sc) 673 { 674 int i; 675 676 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 677 for (i = 0; i < 15000; i++) { 678 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 679 break; 680 DELAY(10); 681 } 682 } 683 684 /* Turn off tap power management on 5401. */ 685 static void 686 bcm5401_load_dspcode(struct mii_softc *sc) 687 { 688 static const struct { 689 int reg; 690 uint16_t val; 691 } dspcode[] = { 692 { BRGPHY_MII_AUXCTL, 0x0c20 }, 693 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 694 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 695 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 696 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 697 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 698 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 699 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 700 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 701 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 702 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 703 { 0, 0 }, 704 }; 705 int i; 706 707 for (i = 0; dspcode[i].reg != 0; i++) 708 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 709 DELAY(40); 710 } 711 712 static void 713 bcm5411_load_dspcode(struct mii_softc *sc) 714 { 715 static const struct { 716 int reg; 717 uint16_t val; 718 } dspcode[] = { 719 { 0x1c, 0x8c23 }, 720 { 0x1c, 0x8ca3 }, 721 { 0x1c, 0x8c23 }, 722 { 0, 0 }, 723 }; 724 int i; 725 726 for (i = 0; dspcode[i].reg != 0; i++) 727 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 728 } 729 730 static void 731 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 732 { 733 static const struct { 734 int reg; 735 uint16_t val; 736 } dspcode[] = { 737 { 0x1c, 0x8d68 }, 738 { 0x1c, 0x8d68 }, 739 { 0, 0 }, 740 }; 741 int i; 742 743 for (i = 0; dspcode[i].reg != 0; i++) 744 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 745 } 746 747 static void 748 brgphy_fixup_adc_bug(struct mii_softc *sc) 749 { 750 static const struct { 751 int reg; 752 uint16_t val; 753 } dspcode[] = { 754 { BRGPHY_MII_AUXCTL, 0x0c00 }, 755 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 756 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 757 { 0, 0 }, 758 }; 759 int i; 760 761 for (i = 0; dspcode[i].reg != 0; i++) 762 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 763 } 764 765 static void 766 brgphy_fixup_adjust_trim(struct mii_softc *sc) 767 { 768 static const struct { 769 int reg; 770 uint16_t val; 771 } dspcode[] = { 772 { BRGPHY_MII_AUXCTL, 0x0c00 }, 773 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 774 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 775 { BRGPHY_MII_TEST1, 0x0014 }, 776 { BRGPHY_MII_AUXCTL, 0x0400 }, 777 { 0, 0 }, 778 }; 779 int i; 780 781 for (i = 0; dspcode[i].reg != 0; i++) 782 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 783 } 784 785 static void 786 brgphy_fixup_ber_bug(struct mii_softc *sc) 787 { 788 static const struct { 789 int reg; 790 uint16_t val; 791 } dspcode[] = { 792 { BRGPHY_MII_AUXCTL, 0x0c00 }, 793 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 794 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 795 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 796 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 797 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 798 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 799 { BRGPHY_MII_AUXCTL, 0x0400 }, 800 { 0, 0 }, 801 }; 802 int i; 803 804 for (i = 0; dspcode[i].reg != 0; i++) 805 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 806 } 807 808 static void 809 brgphy_fixup_crc_bug(struct mii_softc *sc) 810 { 811 static const struct { 812 int reg; 813 uint16_t val; 814 } dspcode[] = { 815 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 816 { 0x1c, 0x8c68 }, 817 { 0x1c, 0x8d68 }, 818 { 0x1c, 0x8c68 }, 819 { 0, 0 }, 820 }; 821 int i; 822 823 for (i = 0; dspcode[i].reg != 0; i++) 824 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 825 } 826 827 static void 828 brgphy_fixup_jitter_bug(struct mii_softc *sc) 829 { 830 static const struct { 831 int reg; 832 uint16_t val; 833 } dspcode[] = { 834 { BRGPHY_MII_AUXCTL, 0x0c00 }, 835 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 836 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 837 { BRGPHY_MII_AUXCTL, 0x0400 }, 838 { 0, 0 }, 839 }; 840 int i; 841 842 for (i = 0; dspcode[i].reg != 0; i++) 843 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 844 } 845 846 847 static void 848 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 849 { 850 uint32_t val; 851 852 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 853 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 854 val &= ~(1 << 8); 855 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 856 857 } 858 859 860 static void 861 brgphy_ethernet_wirespeed(struct mii_softc *sc) 862 { 863 uint32_t val; 864 865 /* Enable Ethernet@WireSpeed. */ 866 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 867 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 868 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 869 } 870 871 872 static void 873 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 874 { 875 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 876 uint32_t val; 877 878 /* Set or clear jumbo frame settings in the PHY. */ 879 if (mtu > ETHER_MAX_LEN) { 880 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 881 /* BCM5401 PHY cannot read-modify-write. */ 882 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 883 } else { 884 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 885 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 886 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 887 val | BRGPHY_AUXCTL_LONG_PKT); 888 } 889 890 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 891 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 892 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 893 } else { 894 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 895 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 896 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 897 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 898 899 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 900 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 901 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 902 } 903 } 904 905 static void 906 brgphy_reset(struct mii_softc *sc) 907 { 908 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 909 struct bge_softc *bge_sc = NULL; 910 struct bce_softc *bce_sc = NULL; 911 struct ifnet *ifp; 912 913 /* Perform a standard PHY reset. */ 914 mii_phy_reset(sc); 915 916 /* Handle any PHY specific procedures following the reset. */ 917 switch (bsc->mii_oui) { 918 case MII_OUI_BROADCOM: 919 break; 920 case MII_OUI_xxBROADCOM: 921 switch (bsc->mii_model) { 922 case MII_MODEL_xxBROADCOM_BCM5400: 923 bcm5401_load_dspcode(sc); 924 break; 925 case MII_MODEL_xxBROADCOM_BCM5401: 926 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 927 bcm5401_load_dspcode(sc); 928 break; 929 case MII_MODEL_xxBROADCOM_BCM5411: 930 bcm5411_load_dspcode(sc); 931 break; 932 } 933 break; 934 case MII_OUI_xxBROADCOM_ALT1: 935 break; 936 } 937 938 ifp = sc->mii_pdata->mii_ifp; 939 940 /* Find the driver associated with this PHY. */ 941 if (strcmp(ifp->if_dname, "bge") == 0) { 942 bge_sc = ifp->if_softc; 943 } else if (strcmp(ifp->if_dname, "bce") == 0) { 944 bce_sc = ifp->if_softc; 945 } 946 947 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 948 if (bge_sc) { 949 /* Fix up various bugs */ 950 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) 951 brgphy_fixup_5704_a0_bug(sc); 952 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) 953 brgphy_fixup_adc_bug(sc); 954 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) 955 brgphy_fixup_adjust_trim(sc); 956 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) 957 brgphy_fixup_ber_bug(sc); 958 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) 959 brgphy_fixup_crc_bug(sc); 960 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) 961 brgphy_fixup_jitter_bug(sc); 962 963 brgphy_jumbo_settings(sc, ifp->if_mtu); 964 965 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED) 966 brgphy_ethernet_wirespeed(sc); 967 968 /* Enable Link LED on Dell boxes */ 969 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { 970 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 971 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 972 ~BRGPHY_PHY_EXTCTL_3_LED); 973 } 974 975 /* Adjust output voltage (From Linux driver) */ 976 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 977 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 978 979 /* Handle any bce (NetXtreme II) workarounds. */ 980 } else if (bce_sc) { 981 982 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 983 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 984 985 /* Store autoneg capabilities/results in digital block (Page 0) */ 986 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 987 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 988 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 989 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 990 991 /* Enable fiber mode and autodetection */ 992 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 993 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 994 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 995 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 996 997 /* Enable parallel detection */ 998 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 999 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1000 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1001 1002 /* Advertise 2.5G support through next page during autoneg */ 1003 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1004 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1005 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1006 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1007 1008 /* Increase TX signal amplitude */ 1009 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1010 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1011 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1012 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1013 BRGPHY_5708S_TX_MISC_PG5); 1014 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1015 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1016 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1017 BRGPHY_5708S_DIG_PG0); 1018 } 1019 1020 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1021 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1022 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1023 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1024 BRGPHY_5708S_TX_MISC_PG5); 1025 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1026 bce_sc->bce_port_hw_cfg & 1027 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1028 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1029 BRGPHY_5708S_DIG_PG0); 1030 } 1031 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1032 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1033 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1034 brgphy_fixup_disable_early_dac(sc); 1035 1036 brgphy_jumbo_settings(sc, ifp->if_mtu); 1037 brgphy_ethernet_wirespeed(sc); 1038 } else { 1039 brgphy_fixup_ber_bug(sc); 1040 brgphy_jumbo_settings(sc, ifp->if_mtu); 1041 brgphy_ethernet_wirespeed(sc); 1042 } 1043 1044 } 1045 } 1046 1047