1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2000 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/bus.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/ethernet.h> 53 #include <net/if_media.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include "miidevs.h" 58 59 #include <dev/mii/brgphyreg.h> 60 #include <net/if_arp.h> 61 #include <machine/bus.h> 62 #include <dev/bge/if_bgereg.h> 63 #include <dev/bce/if_bcereg.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include "miibus_if.h" 69 70 static int brgphy_probe(device_t); 71 static int brgphy_attach(device_t); 72 73 struct brgphy_softc { 74 struct mii_softc mii_sc; 75 int serdes_flags; /* Keeps track of the serdes type used */ 76 #define BRGPHY_5706S 0x0001 77 #define BRGPHY_5708S 0x0002 78 #define BRGPHY_NOANWAIT 0x0004 79 #define BRGPHY_5709S 0x0008 80 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 81 }; 82 83 static device_method_t brgphy_methods[] = { 84 /* device interface */ 85 DEVMETHOD(device_probe, brgphy_probe), 86 DEVMETHOD(device_attach, brgphy_attach), 87 DEVMETHOD(device_detach, mii_phy_detach), 88 DEVMETHOD(device_shutdown, bus_generic_shutdown), 89 DEVMETHOD_END 90 }; 91 92 static driver_t brgphy_driver = { 93 "brgphy", 94 brgphy_methods, 95 sizeof(struct brgphy_softc) 96 }; 97 98 DRIVER_MODULE(brgphy, miibus, brgphy_driver, 0, 0); 99 100 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 101 static void brgphy_setmedia(struct mii_softc *, int); 102 static void brgphy_status(struct mii_softc *); 103 static void brgphy_mii_phy_auto(struct mii_softc *, int); 104 static void brgphy_reset(struct mii_softc *); 105 static void brgphy_enable_loopback(struct mii_softc *); 106 static void bcm5401_load_dspcode(struct mii_softc *); 107 static void bcm5411_load_dspcode(struct mii_softc *); 108 static void bcm54k2_load_dspcode(struct mii_softc *); 109 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 110 static void brgphy_fixup_adc_bug(struct mii_softc *); 111 static void brgphy_fixup_adjust_trim(struct mii_softc *); 112 static void brgphy_fixup_ber_bug(struct mii_softc *); 113 static void brgphy_fixup_crc_bug(struct mii_softc *); 114 static void brgphy_fixup_jitter_bug(struct mii_softc *); 115 static void brgphy_ethernet_wirespeed(struct mii_softc *); 116 static void brgphy_bcm54xx_clock_delay(struct mii_softc *); 117 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 118 119 static const struct mii_phydesc brgphys[] = { 120 MII_PHY_DESC(BROADCOM, BCM5400), 121 MII_PHY_DESC(BROADCOM, BCM5401), 122 MII_PHY_DESC(BROADCOM, BCM5402), 123 MII_PHY_DESC(BROADCOM, BCM5411), 124 MII_PHY_DESC(BROADCOM, BCM5404), 125 MII_PHY_DESC(BROADCOM, BCM5424), 126 MII_PHY_DESC(BROADCOM, BCM54K2), 127 MII_PHY_DESC(BROADCOM, BCM5701), 128 MII_PHY_DESC(BROADCOM, BCM5703), 129 MII_PHY_DESC(BROADCOM, BCM5704), 130 MII_PHY_DESC(BROADCOM, BCM5705), 131 MII_PHY_DESC(BROADCOM, BCM5706), 132 MII_PHY_DESC(BROADCOM, BCM5714), 133 MII_PHY_DESC(BROADCOM, BCM5421), 134 MII_PHY_DESC(BROADCOM, BCM5750), 135 MII_PHY_DESC(BROADCOM, BCM5752), 136 MII_PHY_DESC(BROADCOM, BCM5780), 137 MII_PHY_DESC(BROADCOM, BCM5708C), 138 MII_PHY_DESC(BROADCOM, BCM5466), 139 MII_PHY_DESC(BROADCOM2, BCM5478), 140 MII_PHY_DESC(BROADCOM2, BCM5488), 141 MII_PHY_DESC(BROADCOM2, BCM5482), 142 MII_PHY_DESC(BROADCOM2, BCM5708S), 143 MII_PHY_DESC(BROADCOM2, BCM5709C), 144 MII_PHY_DESC(BROADCOM2, BCM5709S), 145 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 146 MII_PHY_DESC(BROADCOM2, BCM5722), 147 MII_PHY_DESC(BROADCOM2, BCM5755), 148 MII_PHY_DESC(BROADCOM2, BCM5754), 149 MII_PHY_DESC(BROADCOM2, BCM5761), 150 MII_PHY_DESC(BROADCOM2, BCM5784), 151 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 152 MII_PHY_DESC(BROADCOM2, BCM5785), 153 #endif 154 MII_PHY_DESC(BROADCOM3, BCM54616S), 155 MII_PHY_DESC(BROADCOM3, BCM54618SE), 156 MII_PHY_DESC(BROADCOM3, BCM5717C), 157 MII_PHY_DESC(BROADCOM3, BCM5719C), 158 MII_PHY_DESC(BROADCOM3, BCM5720C), 159 MII_PHY_DESC(BROADCOM3, BCM57765), 160 MII_PHY_DESC(BROADCOM3, BCM57780), 161 MII_PHY_DESC(BROADCOM4, BCM54213PE), 162 MII_PHY_DESC(BROADCOM4, BCM5725C), 163 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 164 MII_PHY_END 165 }; 166 167 static const struct mii_phy_funcs brgphy_funcs = { 168 brgphy_service, 169 brgphy_status, 170 brgphy_reset 171 }; 172 173 static const struct hs21_type { 174 const uint32_t id; 175 const char *prod; 176 } hs21_type_lists[] = { 177 { 0x57081021, "IBM eServer BladeCenter HS21" }, 178 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" }, 179 }; 180 181 static int 182 detect_hs21(struct bce_softc *bce_sc) 183 { 184 char *sysenv; 185 int found, i; 186 187 found = 0; 188 sysenv = kern_getenv("smbios.system.product"); 189 if (sysenv == NULL) 190 return (found); 191 for (i = 0; i < nitems(hs21_type_lists); i++) { 192 if (bce_sc->bce_chipid == hs21_type_lists[i].id && 193 strncmp(sysenv, hs21_type_lists[i].prod, 194 strlen(hs21_type_lists[i].prod)) == 0) { 195 found++; 196 break; 197 } 198 } 199 freeenv(sysenv); 200 return (found); 201 } 202 203 /* Search for our PHY in the list of known PHYs */ 204 static int 205 brgphy_probe(device_t dev) 206 { 207 208 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 209 } 210 211 /* Attach the PHY to the MII bus */ 212 static int 213 brgphy_attach(device_t dev) 214 { 215 struct brgphy_softc *bsc; 216 struct bge_softc *bge_sc = NULL; 217 struct bce_softc *bce_sc = NULL; 218 struct mii_softc *sc; 219 220 bsc = device_get_softc(dev); 221 sc = &bsc->mii_sc; 222 223 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 224 &brgphy_funcs, 0); 225 226 bsc->serdes_flags = 0; 227 228 /* Find the MAC driver associated with this PHY. */ 229 if (mii_dev_mac_match(dev, "bge")) 230 bge_sc = mii_dev_mac_softc(dev); 231 else if (mii_dev_mac_match(dev, "bce")) 232 bce_sc = mii_dev_mac_softc(dev); 233 234 /* Handle any special cases based on the PHY ID */ 235 switch (sc->mii_mpd_oui) { 236 case MII_OUI_BROADCOM: 237 switch (sc->mii_mpd_model) { 238 case MII_MODEL_BROADCOM_BCM5706: 239 case MII_MODEL_BROADCOM_BCM5714: 240 /* 241 * The 5464 PHY used in the 5706 supports both copper 242 * and fiber interfaces over GMII. Need to check the 243 * shadow registers to see which mode is actually 244 * in effect, and therefore whether we have 5706C or 245 * 5706S. 246 */ 247 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 248 BRGPHY_SHADOW_1C_MODE_CTRL); 249 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 250 BRGPHY_SHADOW_1C_ENA_1000X) { 251 bsc->serdes_flags |= BRGPHY_5706S; 252 sc->mii_flags |= MIIF_HAVEFIBER; 253 } 254 break; 255 } 256 break; 257 case MII_OUI_BROADCOM2: 258 switch (sc->mii_mpd_model) { 259 case MII_MODEL_BROADCOM2_BCM5708S: 260 bsc->serdes_flags |= BRGPHY_5708S; 261 sc->mii_flags |= MIIF_HAVEFIBER; 262 break; 263 case MII_MODEL_BROADCOM2_BCM5709S: 264 /* 265 * XXX 266 * 5720S and 5709S shares the same PHY id. 267 * Assume 5720S PHY if parent device is bge(4). 268 */ 269 if (bge_sc != NULL) 270 bsc->serdes_flags |= BRGPHY_5708S; 271 else 272 bsc->serdes_flags |= BRGPHY_5709S; 273 sc->mii_flags |= MIIF_HAVEFIBER; 274 break; 275 } 276 break; 277 } 278 279 PHY_RESET(sc); 280 281 /* Read the PHY's capabilities. */ 282 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 283 if (sc->mii_capabilities & BMSR_EXTSTAT) 284 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 285 device_printf(dev, " "); 286 287 /* Add the supported media types */ 288 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 289 mii_phy_add_media(sc); 290 printf("\n"); 291 } else { 292 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 293 ifmedia_add(&sc->mii_pdata->mii_media, 294 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 295 0, NULL); 296 printf("1000baseSX-FDX, "); 297 /* 298 * 2.5G support is a software enabled feature 299 * on the 5708S and 5709S. 300 */ 301 if (bce_sc && (bce_sc->bce_phy_flags & 302 BCE_PHY_2_5G_CAPABLE_FLAG)) { 303 ifmedia_add(&sc->mii_pdata->mii_media, 304 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, 305 sc->mii_inst), 0, NULL); 306 printf("2500baseSX-FDX, "); 307 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 308 (detect_hs21(bce_sc) != 0)) { 309 /* 310 * There appears to be certain silicon revision 311 * in IBM HS21 blades that is having issues with 312 * this driver wating for the auto-negotiation to 313 * complete. This happens with a specific chip id 314 * only and when the 1000baseSX-FDX is the only 315 * mode. Workaround this issue since it's unlikely 316 * to be ever addressed. 317 */ 318 printf("auto-neg workaround, "); 319 bsc->serdes_flags |= BRGPHY_NOANWAIT; 320 } 321 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER, 322 IFM_AUTO, 0, sc->mii_inst), 0, NULL); 323 printf("auto\n"); 324 } 325 326 MIIBUS_MEDIAINIT(sc->mii_dev); 327 return (0); 328 } 329 330 static int 331 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 332 { 333 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 334 int val; 335 336 switch (cmd) { 337 case MII_POLLSTAT: 338 break; 339 case MII_MEDIACHG: 340 /* Todo: Why is this here? Is it really needed? */ 341 PHY_RESET(sc); /* XXX hardware bug work-around */ 342 343 switch (IFM_SUBTYPE(ife->ifm_media)) { 344 case IFM_AUTO: 345 brgphy_mii_phy_auto(sc, ife->ifm_media); 346 break; 347 case IFM_2500_SX: 348 case IFM_1000_SX: 349 case IFM_1000_T: 350 case IFM_100_TX: 351 case IFM_10_T: 352 brgphy_setmedia(sc, ife->ifm_media); 353 break; 354 default: 355 return (EINVAL); 356 } 357 break; 358 case MII_TICK: 359 /* Bail if autoneg isn't in process. */ 360 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 361 sc->mii_ticks = 0; 362 break; 363 } 364 365 /* 366 * Check to see if we have link. If we do, we don't 367 * need to restart the autonegotiation process. 368 */ 369 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 370 if (val & BMSR_LINK) { 371 sc->mii_ticks = 0; /* Reset autoneg timer. */ 372 break; 373 } 374 375 /* Announce link loss right after it happens. */ 376 if (sc->mii_ticks++ == 0) 377 break; 378 379 /* Only retry autonegotiation every mii_anegticks seconds. */ 380 if (sc->mii_ticks <= sc->mii_anegticks) 381 break; 382 383 /* Retry autonegotiation */ 384 sc->mii_ticks = 0; 385 brgphy_mii_phy_auto(sc, ife->ifm_media); 386 break; 387 } 388 389 /* Update the media status. */ 390 PHY_STATUS(sc); 391 392 /* 393 * Callback if something changed. Note that we need to poke 394 * the DSP on the Broadcom PHYs if the media changes. 395 */ 396 if (sc->mii_media_active != mii->mii_media_active || 397 sc->mii_media_status != mii->mii_media_status || 398 cmd == MII_MEDIACHG) { 399 switch (sc->mii_mpd_oui) { 400 case MII_OUI_BROADCOM: 401 switch (sc->mii_mpd_model) { 402 case MII_MODEL_BROADCOM_BCM5400: 403 bcm5401_load_dspcode(sc); 404 break; 405 case MII_MODEL_BROADCOM_BCM5401: 406 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 407 bcm5401_load_dspcode(sc); 408 break; 409 case MII_MODEL_BROADCOM_BCM5411: 410 bcm5411_load_dspcode(sc); 411 break; 412 case MII_MODEL_BROADCOM_BCM54K2: 413 bcm54k2_load_dspcode(sc); 414 break; 415 } 416 break; 417 case MII_OUI_BROADCOM4: 418 switch (sc->mii_mpd_model) { 419 case MII_MODEL_BROADCOM4_BCM54213PE: 420 brgphy_bcm54xx_clock_delay(sc); 421 break; 422 } 423 } 424 } 425 mii_phy_update(sc, cmd); 426 return (0); 427 } 428 429 /****************************************************************************/ 430 /* Sets the PHY link speed. */ 431 /* */ 432 /* Returns: */ 433 /* None */ 434 /****************************************************************************/ 435 static void 436 brgphy_setmedia(struct mii_softc *sc, int media) 437 { 438 int bmcr = 0, gig; 439 440 switch (IFM_SUBTYPE(media)) { 441 case IFM_2500_SX: 442 break; 443 case IFM_1000_SX: 444 case IFM_1000_T: 445 bmcr = BRGPHY_S1000; 446 break; 447 case IFM_100_TX: 448 bmcr = BRGPHY_S100; 449 break; 450 case IFM_10_T: 451 default: 452 bmcr = BRGPHY_S10; 453 break; 454 } 455 456 if ((media & IFM_FDX) != 0) { 457 bmcr |= BRGPHY_BMCR_FDX; 458 gig = BRGPHY_1000CTL_AFD; 459 } else { 460 gig = BRGPHY_1000CTL_AHD; 461 } 462 463 /* Force loopback to disconnect PHY from Ethernet medium. */ 464 brgphy_enable_loopback(sc); 465 466 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 467 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 468 469 if (IFM_SUBTYPE(media) != IFM_1000_T && 470 IFM_SUBTYPE(media) != IFM_1000_SX) { 471 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 472 return; 473 } 474 475 if (IFM_SUBTYPE(media) == IFM_1000_T) { 476 gig |= BRGPHY_1000CTL_MSE; 477 if ((media & IFM_ETH_MASTER) != 0) 478 gig |= BRGPHY_1000CTL_MSC; 479 } 480 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 481 PHY_WRITE(sc, BRGPHY_MII_BMCR, 482 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 483 } 484 485 /****************************************************************************/ 486 /* Set the media status based on the PHY settings. */ 487 /* */ 488 /* Returns: */ 489 /* None */ 490 /****************************************************************************/ 491 static void 492 brgphy_status(struct mii_softc *sc) 493 { 494 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 495 struct mii_data *mii = sc->mii_pdata; 496 int aux, bmcr, bmsr, val, xstat; 497 u_int flowstat; 498 499 mii->mii_media_status = IFM_AVALID; 500 mii->mii_media_active = IFM_ETHER; 501 502 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 503 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 504 505 if (bmcr & BRGPHY_BMCR_LOOP) { 506 mii->mii_media_active |= IFM_LOOP; 507 } 508 509 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 510 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 511 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 512 /* Erg, still trying, I guess... */ 513 mii->mii_media_active |= IFM_NONE; 514 return; 515 } 516 517 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 518 /* 519 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 520 * wedges at least the PHY of BCM5704 (but not others). 521 */ 522 flowstat = mii_phy_flowstatus(sc); 523 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 524 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 525 526 /* If copper link is up, get the negotiated speed/duplex. */ 527 if (aux & BRGPHY_AUXSTS_LINK) { 528 mii->mii_media_status |= IFM_ACTIVE; 529 switch (aux & BRGPHY_AUXSTS_AN_RES) { 530 case BRGPHY_RES_1000FD: 531 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 532 case BRGPHY_RES_1000HD: 533 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 534 case BRGPHY_RES_100FD: 535 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 536 case BRGPHY_RES_100T4: 537 mii->mii_media_active |= IFM_100_T4; break; 538 case BRGPHY_RES_100HD: 539 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 540 case BRGPHY_RES_10FD: 541 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 542 case BRGPHY_RES_10HD: 543 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 544 default: 545 mii->mii_media_active |= IFM_NONE; break; 546 } 547 548 if ((mii->mii_media_active & IFM_FDX) != 0) 549 mii->mii_media_active |= flowstat; 550 551 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 552 (xstat & BRGPHY_1000STS_MSR) != 0) 553 mii->mii_media_active |= IFM_ETH_MASTER; 554 } 555 } else { 556 /* Todo: Add support for flow control. */ 557 /* If serdes link is up, get the negotiated speed/duplex. */ 558 if (bmsr & BRGPHY_BMSR_LINK) { 559 mii->mii_media_status |= IFM_ACTIVE; 560 } 561 562 /* Check the link speed/duplex based on the PHY type. */ 563 if (bsc->serdes_flags & BRGPHY_5706S) { 564 mii->mii_media_active |= IFM_1000_SX; 565 566 /* If autoneg enabled, read negotiated duplex settings */ 567 if (bmcr & BRGPHY_BMCR_AUTOEN) { 568 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 569 if (val & BRGPHY_SERDES_ANAR_FDX) 570 mii->mii_media_active |= IFM_FDX; 571 else 572 mii->mii_media_active |= IFM_HDX; 573 } 574 } else if (bsc->serdes_flags & BRGPHY_5708S) { 575 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 576 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 577 578 /* Check for MRBE auto-negotiated speed results. */ 579 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 580 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 581 mii->mii_media_active |= IFM_10_FL; break; 582 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 583 mii->mii_media_active |= IFM_100_FX; break; 584 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 585 mii->mii_media_active |= IFM_1000_SX; break; 586 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 587 mii->mii_media_active |= IFM_2500_SX; break; 588 } 589 590 /* Check for MRBE auto-negotiated duplex results. */ 591 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 592 mii->mii_media_active |= IFM_FDX; 593 else 594 mii->mii_media_active |= IFM_HDX; 595 } else if (bsc->serdes_flags & BRGPHY_5709S) { 596 /* Select GP Status Block of the AN MMD, get autoneg results. */ 597 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 598 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 599 600 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 601 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 602 603 /* Check for MRBE auto-negotiated speed results. */ 604 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 605 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 606 mii->mii_media_active |= IFM_10_FL; break; 607 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 608 mii->mii_media_active |= IFM_100_FX; break; 609 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 610 mii->mii_media_active |= IFM_1000_SX; break; 611 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 612 mii->mii_media_active |= IFM_2500_SX; break; 613 } 614 615 /* Check for MRBE auto-negotiated duplex results. */ 616 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 617 mii->mii_media_active |= IFM_FDX; 618 else 619 mii->mii_media_active |= IFM_HDX; 620 } 621 } 622 } 623 624 static void 625 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 626 { 627 int anar, ktcr = 0; 628 629 PHY_RESET(sc); 630 631 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 632 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 633 if ((media & IFM_FLOW) != 0 || 634 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 635 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 636 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 637 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 638 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 639 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 640 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 641 PHY_READ(sc, BRGPHY_MII_1000CTL); 642 } else { 643 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 644 if ((media & IFM_FLOW) != 0 || 645 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 646 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 647 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 648 } 649 650 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 651 BRGPHY_BMCR_STARTNEG); 652 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 653 } 654 655 /* Enable loopback to force the link down. */ 656 static void 657 brgphy_enable_loopback(struct mii_softc *sc) 658 { 659 int i; 660 661 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 662 for (i = 0; i < 15000; i++) { 663 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 664 break; 665 DELAY(10); 666 } 667 } 668 669 /* Turn off tap power management on 5401. */ 670 static void 671 bcm5401_load_dspcode(struct mii_softc *sc) 672 { 673 static const struct { 674 int reg; 675 uint16_t val; 676 } dspcode[] = { 677 { BRGPHY_MII_AUXCTL, 0x0c20 }, 678 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 679 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 680 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 681 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 682 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 683 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 684 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 685 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 686 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 687 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 688 { 0, 0 }, 689 }; 690 int i; 691 692 for (i = 0; dspcode[i].reg != 0; i++) 693 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 694 DELAY(40); 695 } 696 697 static void 698 bcm5411_load_dspcode(struct mii_softc *sc) 699 { 700 static const struct { 701 int reg; 702 uint16_t val; 703 } dspcode[] = { 704 { 0x1c, 0x8c23 }, 705 { 0x1c, 0x8ca3 }, 706 { 0x1c, 0x8c23 }, 707 { 0, 0 }, 708 }; 709 int i; 710 711 for (i = 0; dspcode[i].reg != 0; i++) 712 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 713 } 714 715 void 716 bcm54k2_load_dspcode(struct mii_softc *sc) 717 { 718 static const struct { 719 int reg; 720 uint16_t val; 721 } dspcode[] = { 722 { 4, 0x01e1 }, 723 { 9, 0x0300 }, 724 { 0, 0 }, 725 }; 726 int i; 727 728 for (i = 0; dspcode[i].reg != 0; i++) 729 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 730 731 } 732 733 static void 734 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 735 { 736 static const struct { 737 int reg; 738 uint16_t val; 739 } dspcode[] = { 740 { 0x1c, 0x8d68 }, 741 { 0x1c, 0x8d68 }, 742 { 0, 0 }, 743 }; 744 int i; 745 746 for (i = 0; dspcode[i].reg != 0; i++) 747 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 748 } 749 750 static void 751 brgphy_fixup_adc_bug(struct mii_softc *sc) 752 { 753 static const struct { 754 int reg; 755 uint16_t val; 756 } dspcode[] = { 757 { BRGPHY_MII_AUXCTL, 0x0c00 }, 758 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 759 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 760 { 0, 0 }, 761 }; 762 int i; 763 764 for (i = 0; dspcode[i].reg != 0; i++) 765 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 766 } 767 768 static void 769 brgphy_fixup_adjust_trim(struct mii_softc *sc) 770 { 771 static const struct { 772 int reg; 773 uint16_t val; 774 } dspcode[] = { 775 { BRGPHY_MII_AUXCTL, 0x0c00 }, 776 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 777 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 778 { BRGPHY_MII_TEST1, 0x0014 }, 779 { BRGPHY_MII_AUXCTL, 0x0400 }, 780 { 0, 0 }, 781 }; 782 int i; 783 784 for (i = 0; dspcode[i].reg != 0; i++) 785 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 786 } 787 788 static void 789 brgphy_fixup_ber_bug(struct mii_softc *sc) 790 { 791 static const struct { 792 int reg; 793 uint16_t val; 794 } dspcode[] = { 795 { BRGPHY_MII_AUXCTL, 0x0c00 }, 796 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 797 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 798 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 799 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 800 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 801 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 802 { BRGPHY_MII_AUXCTL, 0x0400 }, 803 { 0, 0 }, 804 }; 805 int i; 806 807 for (i = 0; dspcode[i].reg != 0; i++) 808 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 809 } 810 811 static void 812 brgphy_fixup_crc_bug(struct mii_softc *sc) 813 { 814 static const struct { 815 int reg; 816 uint16_t val; 817 } dspcode[] = { 818 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 819 { 0x1c, 0x8c68 }, 820 { 0x1c, 0x8d68 }, 821 { 0x1c, 0x8c68 }, 822 { 0, 0 }, 823 }; 824 int i; 825 826 for (i = 0; dspcode[i].reg != 0; i++) 827 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 828 } 829 830 static void 831 brgphy_fixup_jitter_bug(struct mii_softc *sc) 832 { 833 static const struct { 834 int reg; 835 uint16_t val; 836 } dspcode[] = { 837 { BRGPHY_MII_AUXCTL, 0x0c00 }, 838 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 839 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 840 { BRGPHY_MII_AUXCTL, 0x0400 }, 841 { 0, 0 }, 842 }; 843 int i; 844 845 for (i = 0; dspcode[i].reg != 0; i++) 846 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 847 } 848 849 static void 850 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 851 { 852 uint32_t val; 853 854 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 855 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 856 val &= ~(1 << 8); 857 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 858 859 } 860 861 static void 862 brgphy_ethernet_wirespeed(struct mii_softc *sc) 863 { 864 uint32_t val; 865 866 /* Enable Ethernet@WireSpeed. */ 867 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 868 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 869 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 870 } 871 872 static void 873 brgphy_bcm54xx_clock_delay(struct mii_softc *sc) 874 { 875 uint16_t val; 876 877 if (!(sc->mii_flags & (MIIF_RX_DELAY | MIIF_TX_DELAY))) 878 /* Adjusting the clocks in rgmii mode causes packet losses. */ 879 return; 880 881 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC | 882 BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT); 883 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 884 val &= BRGPHY_AUXCTL_MISC_DATA_MASK; 885 if (sc->mii_flags & MIIF_RX_DELAY) 886 val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; 887 else 888 val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN; 889 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN | 890 BRGPHY_AUXCTL_SHADOW_MISC | val); 891 892 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_CLK_CTRL); 893 val = PHY_READ(sc, BRGPHY_MII_SHADOW_1C); 894 val &= BRGPHY_SHADOW_1C_DATA_MASK; 895 if (sc->mii_flags & MIIF_TX_DELAY) 896 val |= BRGPHY_SHADOW_1C_GTXCLK_EN; 897 else 898 val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN; 899 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_WRITE_EN | 900 BRGPHY_SHADOW_1C_CLK_CTRL | val); 901 } 902 903 static void 904 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 905 { 906 uint32_t val; 907 908 /* Set or clear jumbo frame settings in the PHY. */ 909 if (mtu > ETHER_MAX_LEN) { 910 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 911 /* BCM5401 PHY cannot read-modify-write. */ 912 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 913 } else { 914 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 915 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 916 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 917 val | BRGPHY_AUXCTL_LONG_PKT); 918 } 919 920 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 921 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 922 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 923 } else { 924 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 925 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 926 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 927 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 928 929 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 930 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 931 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 932 } 933 } 934 935 static void 936 brgphy_reset(struct mii_softc *sc) 937 { 938 struct bge_softc *bge_sc = NULL; 939 struct bce_softc *bce_sc = NULL; 940 if_t ifp; 941 int i, val; 942 943 /* 944 * Perform a reset. Note that at least some Broadcom PHYs default to 945 * being powered down as well as isolated after a reset but don't work 946 * if one or both of these bits are cleared. However, they just work 947 * fine if both bits remain set, so we don't use mii_phy_reset() here. 948 */ 949 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 950 951 /* Wait 100ms for it to complete. */ 952 for (i = 0; i < 100; i++) { 953 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 954 break; 955 DELAY(1000); 956 } 957 958 /* Handle any PHY specific procedures following the reset. */ 959 switch (sc->mii_mpd_oui) { 960 case MII_OUI_BROADCOM: 961 switch (sc->mii_mpd_model) { 962 case MII_MODEL_BROADCOM_BCM5400: 963 bcm5401_load_dspcode(sc); 964 break; 965 case MII_MODEL_BROADCOM_BCM5401: 966 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 967 bcm5401_load_dspcode(sc); 968 break; 969 case MII_MODEL_BROADCOM_BCM5411: 970 bcm5411_load_dspcode(sc); 971 break; 972 case MII_MODEL_BROADCOM_BCM54K2: 973 bcm54k2_load_dspcode(sc); 974 break; 975 } 976 break; 977 case MII_OUI_BROADCOM3: 978 switch (sc->mii_mpd_model) { 979 case MII_MODEL_BROADCOM3_BCM5717C: 980 case MII_MODEL_BROADCOM3_BCM5719C: 981 case MII_MODEL_BROADCOM3_BCM5720C: 982 case MII_MODEL_BROADCOM3_BCM57765: 983 return; 984 } 985 break; 986 case MII_OUI_BROADCOM4: 987 return; 988 } 989 990 ifp = sc->mii_pdata->mii_ifp; 991 992 /* Find the driver associated with this PHY. */ 993 if (mii_phy_mac_match(sc, "bge")) 994 bge_sc = mii_phy_mac_softc(sc); 995 else if (mii_phy_mac_match(sc, "bce")) 996 bce_sc = mii_phy_mac_softc(sc); 997 998 if (bge_sc) { 999 /* Fix up various bugs */ 1000 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 1001 brgphy_fixup_5704_a0_bug(sc); 1002 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 1003 brgphy_fixup_adc_bug(sc); 1004 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 1005 brgphy_fixup_adjust_trim(sc); 1006 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 1007 brgphy_fixup_ber_bug(sc); 1008 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 1009 brgphy_fixup_crc_bug(sc); 1010 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 1011 brgphy_fixup_jitter_bug(sc); 1012 1013 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 1014 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1015 1016 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 1017 brgphy_ethernet_wirespeed(sc); 1018 1019 /* Enable Link LED on Dell boxes */ 1020 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 1021 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1022 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 1023 ~BRGPHY_PHY_EXTCTL_3_LED); 1024 } 1025 1026 /* Adjust output voltage (From Linux driver) */ 1027 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 1028 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 1029 } else if (bce_sc) { 1030 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 1031 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1032 /* Store autoneg capabilities/results in digital block (Page 0) */ 1033 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 1034 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 1035 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 1036 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 1037 1038 /* Enable fiber mode and autodetection */ 1039 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 1040 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 1041 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 1042 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 1043 1044 /* Enable parallel detection */ 1045 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1046 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1047 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1048 1049 /* Advertise 2.5G support through next page during autoneg */ 1050 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1051 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1052 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1053 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1054 1055 /* Increase TX signal amplitude */ 1056 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1057 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1058 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1059 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1060 BRGPHY_5708S_TX_MISC_PG5); 1061 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1062 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1063 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1064 BRGPHY_5708S_DIG_PG0); 1065 } 1066 1067 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1068 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1069 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1070 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1071 BRGPHY_5708S_TX_MISC_PG5); 1072 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1073 bce_sc->bce_port_hw_cfg & 1074 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1075 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1076 BRGPHY_5708S_DIG_PG0); 1077 } 1078 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1079 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1080 /* Select the SerDes Digital block of the AN MMD. */ 1081 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1082 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1083 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1084 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1085 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1086 1087 /* Select the Over 1G block of the AN MMD. */ 1088 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1089 1090 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1091 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1092 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1093 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1094 else 1095 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1096 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1097 1098 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1099 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1100 1101 /* Enable MRBE speed autoneg. */ 1102 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1103 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1104 BRGPHY_MRBE_MSG_PG5_NP_T2; 1105 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1106 1107 /* Select the Clause 73 User B0 block of the AN MMD. */ 1108 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1109 1110 /* Enable MRBE speed autoneg. */ 1111 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1112 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1113 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1114 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1115 1116 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1117 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1118 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1119 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1120 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1121 brgphy_fixup_disable_early_dac(sc); 1122 1123 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1124 brgphy_ethernet_wirespeed(sc); 1125 } else { 1126 brgphy_fixup_ber_bug(sc); 1127 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1128 brgphy_ethernet_wirespeed(sc); 1129 } 1130 } 1131 } 1132