1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 48 #include <machine/clock.h> 49 50 #include <net/if.h> 51 #include <net/ethernet.h> 52 #include <net/if_media.h> 53 54 #include <dev/mii/mii.h> 55 #include <dev/mii/miivar.h> 56 #include "miidevs.h" 57 58 #include <dev/mii/brgphyreg.h> 59 #include <net/if_arp.h> 60 #include <machine/bus.h> 61 #include <dev/bge/if_bgereg.h> 62 #include <dev/bce/if_bcereg.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 #include "miibus_if.h" 68 69 static int brgphy_probe(device_t); 70 static int brgphy_attach(device_t); 71 72 static device_method_t brgphy_methods[] = { 73 /* device interface */ 74 DEVMETHOD(device_probe, brgphy_probe), 75 DEVMETHOD(device_attach, brgphy_attach), 76 DEVMETHOD(device_detach, mii_phy_detach), 77 DEVMETHOD(device_shutdown, bus_generic_shutdown), 78 { 0, 0 } 79 }; 80 81 static devclass_t brgphy_devclass; 82 83 static driver_t brgphy_driver = { 84 "brgphy", 85 brgphy_methods, 86 sizeof(struct mii_softc) 87 }; 88 89 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 90 91 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 92 static void brgphy_status(struct mii_softc *); 93 static int brgphy_mii_phy_auto(struct mii_softc *); 94 static void brgphy_reset(struct mii_softc *); 95 static void brgphy_loop(struct mii_softc *); 96 static void bcm5401_load_dspcode(struct mii_softc *); 97 static void bcm5411_load_dspcode(struct mii_softc *); 98 static void bcm5703_load_dspcode(struct mii_softc *); 99 static void bcm5750_load_dspcode(struct mii_softc *); 100 static int brgphy_mii_model; 101 102 static int 103 brgphy_probe(device_t dev) 104 { 105 struct mii_attach_args *ma; 106 107 ma = device_get_ivars(dev); 108 109 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 110 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 111 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 112 return(0); 113 } 114 115 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 116 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 117 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 118 return(0); 119 } 120 121 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 122 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 123 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 124 return(0); 125 } 126 127 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 128 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 129 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 130 return(0); 131 } 132 133 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 134 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 135 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 136 return(0); 137 } 138 139 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 140 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 141 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 142 return(0); 143 } 144 145 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 146 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 147 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 148 return(0); 149 } 150 151 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 152 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750) { 153 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5750); 154 return(0); 155 } 156 157 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 158 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5714) { 159 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5714); 160 return(0); 161 } 162 163 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 164 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5780) { 165 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5780); 166 return (0); 167 } 168 169 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 170 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5706C) { 171 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5706C); 172 return(0); 173 } 174 175 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 176 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5708C) { 177 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5708C); 178 return(0); 179 } 180 181 return(ENXIO); 182 } 183 184 static int 185 brgphy_attach(device_t dev) 186 { 187 struct mii_softc *sc; 188 struct mii_attach_args *ma; 189 struct mii_data *mii; 190 const char *sep = ""; 191 struct bge_softc *bge_sc = NULL; 192 struct bce_softc *bce_sc = NULL; 193 int fast_ether_only = FALSE; 194 195 sc = device_get_softc(dev); 196 ma = device_get_ivars(dev); 197 sc->mii_dev = device_get_parent(dev); 198 mii = device_get_softc(sc->mii_dev); 199 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 200 201 sc->mii_inst = mii->mii_instance; 202 sc->mii_phy = ma->mii_phyno; 203 sc->mii_service = brgphy_service; 204 sc->mii_pdata = mii; 205 206 sc->mii_flags |= MIIF_NOISOLATE; 207 mii->mii_instance++; 208 209 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 210 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 211 212 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 213 BMCR_ISO); 214 #if 0 215 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 216 BMCR_LOOP|BMCR_S100); 217 #endif 218 219 brgphy_mii_model = MII_MODEL(ma->mii_id2); 220 brgphy_reset(sc); 221 222 223 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 224 sc->mii_capabilities &= ~BMSR_ANEG; 225 device_printf(dev, " "); 226 mii_add_media(sc); 227 228 /* Find the driver associated with this PHY. */ 229 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) { 230 bge_sc = mii->mii_ifp->if_softc; 231 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) { 232 bce_sc = mii->mii_ifp->if_softc; 233 } 234 235 /* The 590x chips are 10/100 only. */ 236 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 237 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 238 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 239 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 240 fast_ether_only = TRUE; 241 242 if (fast_ether_only == FALSE) { 243 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 244 sc->mii_inst), BRGPHY_BMCR_FDX); 245 PRINT(", 1000baseTX"); 246 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 247 IFM_FDX, sc->mii_inst), 0); 248 PRINT("1000baseTX-FDX"); 249 } 250 251 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 252 PRINT("auto"); 253 254 printf("\n"); 255 #undef ADD 256 #undef PRINT 257 258 MIIBUS_MEDIAINIT(sc->mii_dev); 259 return(0); 260 } 261 262 static int 263 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 264 { 265 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 266 int reg, speed, gig; 267 268 switch (cmd) { 269 case MII_POLLSTAT: 270 /* 271 * If we're not polling our PHY instance, just return. 272 */ 273 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 274 return (0); 275 break; 276 277 case MII_MEDIACHG: 278 /* 279 * If the media indicates a different PHY instance, 280 * isolate ourselves. 281 */ 282 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 283 reg = PHY_READ(sc, MII_BMCR); 284 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 285 return (0); 286 } 287 288 /* 289 * If the interface is not up, don't do anything. 290 */ 291 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 292 break; 293 294 brgphy_reset(sc); /* XXX hardware bug work-around */ 295 296 switch (IFM_SUBTYPE(ife->ifm_media)) { 297 case IFM_AUTO: 298 #ifdef foo 299 /* 300 * If we're already in auto mode, just return. 301 */ 302 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 303 return (0); 304 #endif 305 (void) brgphy_mii_phy_auto(sc); 306 break; 307 case IFM_1000_T: 308 speed = BRGPHY_S1000; 309 goto setit; 310 case IFM_100_TX: 311 speed = BRGPHY_S100; 312 goto setit; 313 case IFM_10_T: 314 speed = BRGPHY_S10; 315 setit: 316 brgphy_loop(sc); 317 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 318 speed |= BRGPHY_BMCR_FDX; 319 gig = BRGPHY_1000CTL_AFD; 320 } else { 321 gig = BRGPHY_1000CTL_AHD; 322 } 323 324 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 325 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 326 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 327 328 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 329 break; 330 331 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 332 PHY_WRITE(sc, BRGPHY_MII_BMCR, 333 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 334 335 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 336 break; 337 338 /* 339 * When settning the link manually, one side must 340 * be the master and the other the slave. However 341 * ifmedia doesn't give us a good way to specify 342 * this, so we fake it by using one of the LINK 343 * flags. If LINK0 is set, we program the PHY to 344 * be a master, otherwise it's a slave. 345 */ 346 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 347 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 348 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 349 } else { 350 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 351 gig|BRGPHY_1000CTL_MSE); 352 } 353 break; 354 #ifdef foo 355 case IFM_NONE: 356 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 357 break; 358 #endif 359 case IFM_100_T4: 360 default: 361 return (EINVAL); 362 } 363 break; 364 365 case MII_TICK: 366 /* 367 * If we're not currently selected, just return. 368 */ 369 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 370 return (0); 371 372 /* 373 * Is the interface even up? 374 */ 375 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 376 return (0); 377 378 /* 379 * Only used for autonegotiation. 380 */ 381 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 382 break; 383 384 /* 385 * Check to see if we have link. If we do, we don't 386 * need to restart the autonegotiation process. Read 387 * the BMSR twice in case it's latched. 388 */ 389 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 390 if (reg & BRGPHY_AUXSTS_LINK) 391 break; 392 393 /* 394 * Only retry autonegotiation every 5 seconds. 395 */ 396 if (++sc->mii_ticks <= 5) 397 break; 398 399 sc->mii_ticks = 0; 400 brgphy_mii_phy_auto(sc); 401 break; 402 } 403 404 /* Update the media status. */ 405 brgphy_status(sc); 406 407 /* 408 * Callback if something changed. Note that we need to poke 409 * the DSP on the Broadcom PHYs if the media changes. 410 * 411 */ 412 if (sc->mii_media_active != mii->mii_media_active || 413 sc->mii_media_status != mii->mii_media_status || 414 cmd == MII_MEDIACHG) { 415 switch (brgphy_mii_model) { 416 case MII_MODEL_xxBROADCOM_BCM5400: 417 case MII_MODEL_xxBROADCOM_BCM5401: 418 bcm5401_load_dspcode(sc); 419 break; 420 case MII_MODEL_xxBROADCOM_BCM5411: 421 bcm5411_load_dspcode(sc); 422 break; 423 } 424 } 425 mii_phy_update(sc, cmd); 426 return (0); 427 } 428 429 static void 430 brgphy_status(struct mii_softc *sc) 431 { 432 struct mii_data *mii = sc->mii_pdata; 433 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 434 int bmsr, bmcr; 435 436 mii->mii_media_status = IFM_AVALID; 437 mii->mii_media_active = IFM_ETHER; 438 439 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 440 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 441 mii->mii_media_status |= IFM_ACTIVE; 442 443 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 444 445 if (bmcr & BRGPHY_BMCR_LOOP) 446 mii->mii_media_active |= IFM_LOOP; 447 448 if (bmcr & BRGPHY_BMCR_AUTOEN) { 449 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 450 /* Erg, still trying, I guess... */ 451 mii->mii_media_active |= IFM_NONE; 452 return; 453 } 454 455 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 456 BRGPHY_AUXSTS_AN_RES) { 457 case BRGPHY_RES_1000FD: 458 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 459 break; 460 case BRGPHY_RES_1000HD: 461 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 462 break; 463 case BRGPHY_RES_100FD: 464 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 465 break; 466 case BRGPHY_RES_100T4: 467 mii->mii_media_active |= IFM_100_T4; 468 break; 469 case BRGPHY_RES_100HD: 470 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 471 break; 472 case BRGPHY_RES_10FD: 473 mii->mii_media_active |= IFM_10_T | IFM_FDX; 474 break; 475 case BRGPHY_RES_10HD: 476 mii->mii_media_active |= IFM_10_T | IFM_HDX; 477 break; 478 default: 479 mii->mii_media_active |= IFM_NONE; 480 break; 481 } 482 return; 483 } 484 485 mii->mii_media_active = ife->ifm_media; 486 487 return; 488 } 489 490 491 static int 492 brgphy_mii_phy_auto(struct mii_softc *mii) 493 { 494 int ktcr = 0; 495 496 brgphy_loop(mii); 497 brgphy_reset(mii); 498 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 499 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 500 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 501 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 502 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 503 DELAY(1000); 504 PHY_WRITE(mii, BRGPHY_MII_ANAR, 505 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 506 DELAY(1000); 507 PHY_WRITE(mii, BRGPHY_MII_BMCR, 508 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 509 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 510 return (EJUSTRETURN); 511 } 512 513 static void 514 brgphy_loop(struct mii_softc *sc) 515 { 516 u_int32_t bmsr; 517 int i; 518 519 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 520 for (i = 0; i < 15000; i++) { 521 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 522 if (!(bmsr & BRGPHY_BMSR_LINK)) { 523 #if 0 524 device_printf(sc->mii_dev, "looped %d\n", i); 525 #endif 526 break; 527 } 528 DELAY(10); 529 } 530 } 531 532 /* Turn off tap power management on 5401. */ 533 static void 534 bcm5401_load_dspcode(struct mii_softc *sc) 535 { 536 static const struct { 537 int reg; 538 uint16_t val; 539 } dspcode[] = { 540 { BRGPHY_MII_AUXCTL, 0x0c20 }, 541 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 542 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 543 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 544 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 545 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 546 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 547 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 548 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 549 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 550 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 551 { 0, 0 }, 552 }; 553 int i; 554 555 for (i = 0; dspcode[i].reg != 0; i++) 556 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 557 DELAY(40); 558 } 559 560 static void 561 bcm5411_load_dspcode(struct mii_softc *sc) 562 { 563 static const struct { 564 int reg; 565 uint16_t val; 566 } dspcode[] = { 567 { 0x1c, 0x8c23 }, 568 { 0x1c, 0x8ca3 }, 569 { 0x1c, 0x8c23 }, 570 { 0, 0 }, 571 }; 572 int i; 573 574 for (i = 0; dspcode[i].reg != 0; i++) 575 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 576 } 577 578 static void 579 bcm5703_load_dspcode(struct mii_softc *sc) 580 { 581 static const struct { 582 int reg; 583 uint16_t val; 584 } dspcode[] = { 585 { BRGPHY_MII_AUXCTL, 0x0c00 }, 586 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 587 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 588 { 0, 0 }, 589 }; 590 int i; 591 592 for (i = 0; dspcode[i].reg != 0; i++) 593 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 594 } 595 596 static void 597 bcm5704_load_dspcode(struct mii_softc *sc) 598 { 599 static const struct { 600 int reg; 601 u_int16_t val; 602 } dspcode[] = { 603 { 0x1c, 0x8d68 }, 604 { 0x1c, 0x8d68 }, 605 { 0, 0 }, 606 }; 607 int i; 608 609 for (i = 0; dspcode[i].reg != 0; i++) 610 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 611 } 612 613 static void 614 bcm5750_load_dspcode(struct mii_softc *sc) 615 { 616 static const struct { 617 int reg; 618 u_int16_t val; 619 } dspcode[] = { 620 { 0x18, 0x0c00 }, 621 { 0x17, 0x000a }, 622 { 0x15, 0x310b }, 623 { 0x17, 0x201f }, 624 { 0x15, 0x9506 }, 625 { 0x17, 0x401f }, 626 { 0x15, 0x14e2 }, 627 { 0x18, 0x0400 }, 628 { 0, 0 }, 629 }; 630 int i; 631 632 for (i = 0; dspcode[i].reg != 0; i++) 633 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 634 } 635 636 static void 637 brgphy_reset(struct mii_softc *sc) 638 { 639 u_int32_t val; 640 struct ifnet *ifp; 641 struct bge_softc *bge_sc = NULL; 642 struct bce_softc *bce_sc = NULL; 643 644 mii_phy_reset(sc); 645 646 switch (brgphy_mii_model) { 647 case MII_MODEL_xxBROADCOM_BCM5400: 648 case MII_MODEL_xxBROADCOM_BCM5401: 649 bcm5401_load_dspcode(sc); 650 break; 651 case MII_MODEL_xxBROADCOM_BCM5411: 652 bcm5411_load_dspcode(sc); 653 break; 654 case MII_MODEL_xxBROADCOM_BCM5703: 655 bcm5703_load_dspcode(sc); 656 break; 657 case MII_MODEL_xxBROADCOM_BCM5704: 658 bcm5704_load_dspcode(sc); 659 break; 660 case MII_MODEL_xxBROADCOM_BCM5750: 661 case MII_MODEL_xxBROADCOM_BCM5714: 662 case MII_MODEL_xxBROADCOM_BCM5780: 663 case MII_MODEL_xxBROADCOM_BCM5706C: 664 case MII_MODEL_xxBROADCOM_BCM5708C: 665 bcm5750_load_dspcode(sc); 666 break; 667 } 668 669 ifp = sc->mii_pdata->mii_ifp; 670 671 /* Find the driver associated with this PHY. */ 672 if (strcmp(ifp->if_dname, "bge") == 0) { 673 bge_sc = ifp->if_softc; 674 } else if (strcmp(ifp->if_dname, "bce") == 0) { 675 bce_sc = ifp->if_softc; 676 } 677 678 /* Handle any NetXtreme/bge workarounds. */ 679 if (bge_sc) { 680 /* 681 * Don't enable Ethernet@WireSpeed for the 5700 or the 682 * 5705 A1 and A2 chips. Make sure we only do this test 683 * on "bge" NICs, since other drivers may use this same 684 * PHY subdriver. 685 */ 686 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 687 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 688 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2) 689 return; 690 691 /* Enable Ethernet@WireSpeed. */ 692 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 693 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 694 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 695 696 /* Enable Link LED on Dell boxes */ 697 if (bge_sc->bge_no_3_led) { 698 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 699 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 700 & ~BRGPHY_PHY_EXTCTL_3_LED); 701 } 702 } else if (bce_sc) { 703 704 /* Set or clear jumbo frame settings in the PHY. */ 705 if (ifp->if_mtu > ETHER_MAX_LEN) { 706 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 707 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 708 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 709 val | BRGPHY_AUXCTL_LONG_PKT); 710 711 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 712 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 713 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 714 } else { 715 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 716 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 717 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 718 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 719 720 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 721 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 722 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 723 } 724 725 /* Enable Ethernet@Wirespeed */ 726 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 727 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 728 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4))); 729 } 730 } 731