1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/brgphyreg.h> 56 #include <net/if_arp.h> 57 #include <machine/bus.h> 58 #include <dev/bge/if_bgereg.h> 59 #include <dev/bce/if_bcereg.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 #include "miibus_if.h" 65 66 static int brgphy_probe(device_t); 67 static int brgphy_attach(device_t); 68 69 struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int mii_model; 72 int mii_rev; 73 }; 74 75 static device_method_t brgphy_methods[] = { 76 /* device interface */ 77 DEVMETHOD(device_probe, brgphy_probe), 78 DEVMETHOD(device_attach, brgphy_attach), 79 DEVMETHOD(device_detach, mii_phy_detach), 80 DEVMETHOD(device_shutdown, bus_generic_shutdown), 81 { 0, 0 } 82 }; 83 84 static devclass_t brgphy_devclass; 85 86 static driver_t brgphy_driver = { 87 "brgphy", 88 brgphy_methods, 89 sizeof(struct brgphy_softc) 90 }; 91 92 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 93 94 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 95 static void brgphy_setmedia(struct mii_softc *, int, int); 96 static void brgphy_status(struct mii_softc *); 97 static int brgphy_mii_phy_auto(struct mii_softc *); 98 static void brgphy_reset(struct mii_softc *); 99 static void brgphy_loop(struct mii_softc *); 100 static int bcm5706_is_tbi(device_t); 101 static void bcm5401_load_dspcode(struct mii_softc *); 102 static void bcm5411_load_dspcode(struct mii_softc *); 103 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 104 static void brgphy_fixup_adc_bug(struct mii_softc *); 105 static void brgphy_fixup_adjust_trim(struct mii_softc *); 106 static void brgphy_fixup_ber_bug(struct mii_softc *); 107 static void brgphy_fixup_crc_bug(struct mii_softc *); 108 static void brgphy_fixup_jitter_bug(struct mii_softc *); 109 static void brgphy_ethernet_wirespeed(struct mii_softc *); 110 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 111 112 static const struct mii_phydesc brgphys[] = { 113 MII_PHY_DESC(xxBROADCOM, BCM5400), 114 MII_PHY_DESC(xxBROADCOM, BCM5401), 115 MII_PHY_DESC(xxBROADCOM, BCM5411), 116 MII_PHY_DESC(xxBROADCOM, BCM5701), 117 MII_PHY_DESC(xxBROADCOM, BCM5703), 118 MII_PHY_DESC(xxBROADCOM, BCM5704), 119 MII_PHY_DESC(xxBROADCOM, BCM5705), 120 MII_PHY_DESC(xxBROADCOM, BCM5706C), 121 MII_PHY_DESC(xxBROADCOM, BCM5714), 122 MII_PHY_DESC(xxBROADCOM, BCM5750), 123 MII_PHY_DESC(xxBROADCOM, BCM5752), 124 MII_PHY_DESC(xxBROADCOM, BCM5754), 125 MII_PHY_DESC(xxBROADCOM, BCM5780), 126 MII_PHY_DESC(xxBROADCOM, BCM5708C), 127 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 128 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 129 MII_PHY_END 130 }; 131 132 static int 133 brgphy_probe(device_t dev) 134 { 135 struct mii_attach_args *ma; 136 int error; 137 138 error = mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT); 139 if (error != BUS_PROBE_DEFAULT) 140 return (error); 141 142 ma = device_get_ivars(dev); 143 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 144 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5706C) { 145 /* 146 * Broadcom uses the same MII model ID on two 147 * different types of phys. The first is found on the 148 * BCM 5706 and is supported by this driver. The 149 * other is found on the BCM 5706S and 5708S and is 150 * supported by the gentbi(4) driver, so we check to 151 * see if this phy is supported by gentbi(4) and fail 152 * the probe if so. 153 */ 154 if (bcm5706_is_tbi(dev)) 155 return (ENXIO); 156 } 157 return (error); 158 } 159 160 static int 161 brgphy_attach(device_t dev) 162 { 163 struct brgphy_softc *bsc; 164 struct mii_softc *sc; 165 struct mii_attach_args *ma; 166 struct mii_data *mii; 167 const char *sep = ""; 168 struct bge_softc *bge_sc = NULL; 169 struct bce_softc *bce_sc = NULL; 170 int fast_ether_only = FALSE; 171 172 bsc = device_get_softc(dev); 173 sc = &bsc->mii_sc; 174 ma = device_get_ivars(dev); 175 sc->mii_dev = device_get_parent(dev); 176 mii = device_get_softc(sc->mii_dev); 177 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 178 179 sc->mii_inst = mii->mii_instance; 180 sc->mii_phy = ma->mii_phyno; 181 sc->mii_service = brgphy_service; 182 sc->mii_pdata = mii; 183 184 sc->mii_flags |= MIIF_NOISOLATE; 185 mii->mii_instance++; 186 187 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 188 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 189 190 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 191 BMCR_ISO); 192 #if 0 193 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 194 BMCR_LOOP | BMCR_S100); 195 #endif 196 197 bsc->mii_model = MII_MODEL(ma->mii_id2); 198 bsc->mii_rev = MII_REV(ma->mii_id2); 199 brgphy_reset(sc); 200 201 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 202 sc->mii_capabilities &= ~BMSR_ANEG; 203 device_printf(dev, " "); 204 mii_add_media(sc); 205 206 /* Find the driver associated with this PHY. */ 207 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) { 208 bge_sc = mii->mii_ifp->if_softc; 209 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) { 210 bce_sc = mii->mii_ifp->if_softc; 211 } 212 213 /* The 590x chips are 10/100 only. */ 214 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 215 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 216 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 217 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 218 fast_ether_only = TRUE; 219 220 if (fast_ether_only == FALSE) { 221 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 222 sc->mii_inst), BRGPHY_BMCR_FDX); 223 PRINT(", 1000baseTX"); 224 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 225 IFM_FDX, sc->mii_inst), 0); 226 PRINT("1000baseTX-FDX"); 227 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 228 } else 229 sc->mii_anegticks = MII_ANEGTICKS; 230 231 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 232 PRINT("auto"); 233 234 printf("\n"); 235 #undef ADD 236 #undef PRINT 237 238 MIIBUS_MEDIAINIT(sc->mii_dev); 239 return (0); 240 } 241 242 static int 243 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 244 { 245 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 246 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 247 248 switch (cmd) { 249 case MII_POLLSTAT: 250 /* If we're not polling our PHY instance, just return. */ 251 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 252 return (0); 253 break; 254 case MII_MEDIACHG: 255 /* 256 * If the media indicates a different PHY instance, 257 * isolate ourselves. 258 */ 259 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 260 PHY_WRITE(sc, MII_BMCR, 261 PHY_READ(sc, MII_BMCR) | BMCR_ISO); 262 return (0); 263 } 264 265 /* If the interface is not up, don't do anything. */ 266 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 267 break; 268 269 brgphy_reset(sc); /* XXX hardware bug work-around */ 270 271 switch (IFM_SUBTYPE(ife->ifm_media)) { 272 case IFM_AUTO: 273 #ifdef foo 274 /* If we're already in auto mode, just return. */ 275 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 276 return (0); 277 #endif 278 (void)brgphy_mii_phy_auto(sc); 279 break; 280 case IFM_1000_T: 281 case IFM_100_TX: 282 case IFM_10_T: 283 brgphy_setmedia(sc, ife->ifm_media, 284 mii->mii_ifp->if_flags & IFF_LINK0); 285 break; 286 #ifdef foo 287 case IFM_NONE: 288 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 289 break; 290 #endif 291 case IFM_100_T4: 292 default: 293 return (EINVAL); 294 } 295 break; 296 case MII_TICK: 297 /* If we're not currently selected, just return. */ 298 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 299 return (0); 300 301 /* Is the interface even up? */ 302 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 303 return (0); 304 305 /* Only used for autonegotiation. */ 306 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 307 sc->mii_ticks = 0; /* Reset autoneg timer. */ 308 break; 309 } 310 311 /* 312 * Check to see if we have link. If we do, we don't 313 * need to restart the autonegotiation process. 314 */ 315 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) { 316 sc->mii_ticks = 0; /* Reset autoneg timer. */ 317 break; 318 } 319 320 /* Announce link loss right after it happens. */ 321 if (sc->mii_ticks++ == 0) 322 break; 323 324 /* Only retry autonegotiation every mii_anegticks seconds. */ 325 if (sc->mii_ticks <= sc->mii_anegticks) 326 return (0); 327 328 sc->mii_ticks = 0; 329 (void)brgphy_mii_phy_auto(sc); 330 break; 331 } 332 333 /* Update the media status. */ 334 brgphy_status(sc); 335 336 /* 337 * Callback if something changed. Note that we need to poke 338 * the DSP on the Broadcom PHYs if the media changes. 339 */ 340 if (sc->mii_media_active != mii->mii_media_active || 341 sc->mii_media_status != mii->mii_media_status || 342 cmd == MII_MEDIACHG) { 343 switch (bsc->mii_model) { 344 case MII_MODEL_xxBROADCOM_BCM5400: 345 bcm5401_load_dspcode(sc); 346 break; 347 case MII_MODEL_xxBROADCOM_BCM5401: 348 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 349 bcm5401_load_dspcode(sc); 350 break; 351 case MII_MODEL_xxBROADCOM_BCM5411: 352 bcm5411_load_dspcode(sc); 353 break; 354 } 355 } 356 mii_phy_update(sc, cmd); 357 return (0); 358 } 359 360 static void 361 brgphy_setmedia(struct mii_softc *sc, int media, int master) 362 { 363 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 364 int bmcr, gig; 365 366 switch (IFM_SUBTYPE(media)) { 367 case IFM_1000_T: 368 bmcr = BRGPHY_S1000; 369 break; 370 case IFM_100_TX: 371 bmcr = BRGPHY_S100; 372 break; 373 case IFM_10_T: 374 default: 375 bmcr = BRGPHY_S10; 376 break; 377 } 378 if ((media & IFM_GMASK) == IFM_FDX) { 379 bmcr |= BRGPHY_BMCR_FDX; 380 gig = BRGPHY_1000CTL_AFD; 381 } else { 382 gig = BRGPHY_1000CTL_AHD; 383 } 384 385 brgphy_loop(sc); 386 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 387 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 388 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 389 390 if (IFM_SUBTYPE(media) != IFM_1000_T) 391 return; 392 393 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 394 PHY_WRITE(sc, BRGPHY_MII_BMCR, 395 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 396 397 if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 398 return; 399 400 /* 401 * When setting the link manually, one side must be the master and 402 * the other the slave. However ifmedia doesn't give us a good way 403 * to specify this, so we fake it by using one of the LINK flags. 404 * If LINK0 is set, we program the PHY to be a master, otherwise 405 * it's a slave. 406 */ 407 if (master) { 408 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 409 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); 410 } else { 411 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 412 gig | BRGPHY_1000CTL_MSE); 413 } 414 } 415 416 static void 417 brgphy_status(struct mii_softc *sc) 418 { 419 struct mii_data *mii = sc->mii_pdata; 420 int aux, bmcr, bmsr; 421 422 mii->mii_media_status = IFM_AVALID; 423 mii->mii_media_active = IFM_ETHER; 424 425 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 426 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 427 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 428 429 if (aux & BRGPHY_AUXSTS_LINK) 430 mii->mii_media_status |= IFM_ACTIVE; 431 432 if (bmcr & BRGPHY_BMCR_LOOP) 433 mii->mii_media_active |= IFM_LOOP; 434 435 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 436 (bmsr & BRGPHY_BMSR_ACOMP) == 0) { 437 /* Erg, still trying, I guess... */ 438 mii->mii_media_active |= IFM_NONE; 439 return; 440 } 441 442 if (aux & BRGPHY_AUXSTS_LINK) { 443 switch (aux & BRGPHY_AUXSTS_AN_RES) { 444 case BRGPHY_RES_1000FD: 445 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 446 break; 447 case BRGPHY_RES_1000HD: 448 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 449 break; 450 case BRGPHY_RES_100FD: 451 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 452 break; 453 case BRGPHY_RES_100T4: 454 mii->mii_media_active |= IFM_100_T4; 455 break; 456 case BRGPHY_RES_100HD: 457 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 458 break; 459 case BRGPHY_RES_10FD: 460 mii->mii_media_active |= IFM_10_T | IFM_FDX; 461 break; 462 case BRGPHY_RES_10HD: 463 mii->mii_media_active |= IFM_10_T | IFM_HDX; 464 break; 465 default: 466 mii->mii_media_active |= IFM_NONE; 467 break; 468 } 469 } else 470 mii->mii_media_active |= IFM_NONE; 471 } 472 473 static int 474 brgphy_mii_phy_auto(struct mii_softc *sc) 475 { 476 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 477 int ktcr = 0; 478 479 brgphy_loop(sc); 480 brgphy_reset(sc); 481 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 482 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 483 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 484 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 485 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 486 DELAY(1000); 487 PHY_WRITE(sc, BRGPHY_MII_ANAR, 488 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); 489 DELAY(1000); 490 PHY_WRITE(sc, BRGPHY_MII_BMCR, 491 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 492 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 493 return (EJUSTRETURN); 494 } 495 496 static void 497 brgphy_loop(struct mii_softc *sc) 498 { 499 int i; 500 501 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 502 for (i = 0; i < 15000; i++) { 503 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) { 504 #if 0 505 device_printf(sc->mii_dev, "looped %d\n", i); 506 #endif 507 break; 508 } 509 DELAY(10); 510 } 511 } 512 513 /* 514 * Check to see if a 5706 phy is really a SerDes phy. Copied from 515 * gentbi_probe(). 516 */ 517 static int 518 bcm5706_is_tbi(device_t dev) 519 { 520 device_t parent; 521 struct mii_attach_args *ma; 522 int bmsr, extsr; 523 524 parent = device_get_parent(dev); 525 ma = device_get_ivars(dev); 526 527 bmsr = MIIBUS_READREG(parent, ma->mii_phyno, MII_BMSR); 528 if ((bmsr & BMSR_EXTSTAT) == 0 || (bmsr & BMSR_MEDIAMASK) != 0) 529 return (0); 530 531 extsr = MIIBUS_READREG(parent, ma->mii_phyno, MII_EXTSR); 532 if (extsr & (EXTSR_1000TFDX|EXTSR_1000THDX)) 533 return (0); 534 535 if (extsr & (EXTSR_1000XFDX|EXTSR_1000XHDX)) 536 return (1); 537 538 return (0); 539 } 540 541 /* Turn off tap power management on 5401. */ 542 static void 543 bcm5401_load_dspcode(struct mii_softc *sc) 544 { 545 static const struct { 546 int reg; 547 uint16_t val; 548 } dspcode[] = { 549 { BRGPHY_MII_AUXCTL, 0x0c20 }, 550 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 551 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 552 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 553 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 554 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 555 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 556 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 557 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 558 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 559 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 560 { 0, 0 }, 561 }; 562 int i; 563 564 for (i = 0; dspcode[i].reg != 0; i++) 565 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 566 DELAY(40); 567 } 568 569 static void 570 bcm5411_load_dspcode(struct mii_softc *sc) 571 { 572 static const struct { 573 int reg; 574 uint16_t val; 575 } dspcode[] = { 576 { 0x1c, 0x8c23 }, 577 { 0x1c, 0x8ca3 }, 578 { 0x1c, 0x8c23 }, 579 { 0, 0 }, 580 }; 581 int i; 582 583 for (i = 0; dspcode[i].reg != 0; i++) 584 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 585 } 586 587 static void 588 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 589 { 590 static const struct { 591 int reg; 592 uint16_t val; 593 } dspcode[] = { 594 { 0x1c, 0x8d68 }, 595 { 0x1c, 0x8d68 }, 596 { 0, 0 }, 597 }; 598 int i; 599 600 for (i = 0; dspcode[i].reg != 0; i++) 601 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 602 } 603 604 static void 605 brgphy_fixup_adc_bug(struct mii_softc *sc) 606 { 607 static const struct { 608 int reg; 609 uint16_t val; 610 } dspcode[] = { 611 { BRGPHY_MII_AUXCTL, 0x0c00 }, 612 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 613 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 614 { 0, 0 }, 615 }; 616 int i; 617 618 for (i = 0; dspcode[i].reg != 0; i++) 619 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 620 } 621 622 static void 623 brgphy_fixup_adjust_trim(struct mii_softc *sc) 624 { 625 static const struct { 626 int reg; 627 uint16_t val; 628 } dspcode[] = { 629 { BRGPHY_MII_AUXCTL, 0x0c00 }, 630 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 631 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 632 { BRGPHY_MII_TEST1, 0x0014 }, 633 { BRGPHY_MII_AUXCTL, 0x0400 }, 634 { 0, 0 }, 635 }; 636 int i; 637 638 for (i = 0; dspcode[i].reg != 0; i++) 639 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 640 } 641 642 static void 643 brgphy_fixup_ber_bug(struct mii_softc *sc) 644 { 645 static const struct { 646 int reg; 647 uint16_t val; 648 } dspcode[] = { 649 { BRGPHY_MII_AUXCTL, 0x0c00 }, 650 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 651 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 652 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 653 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 654 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 655 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 656 { BRGPHY_MII_AUXCTL, 0x0400 }, 657 { 0, 0 }, 658 }; 659 int i; 660 661 for (i = 0; dspcode[i].reg != 0; i++) 662 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 663 } 664 665 static void 666 brgphy_fixup_crc_bug(struct mii_softc *sc) 667 { 668 static const struct { 669 int reg; 670 uint16_t val; 671 } dspcode[] = { 672 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 673 { 0x1c, 0x8c68 }, 674 { 0x1c, 0x8d68 }, 675 { 0x1c, 0x8c68 }, 676 { 0, 0 }, 677 }; 678 int i; 679 680 for (i = 0; dspcode[i].reg != 0; i++) 681 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 682 } 683 684 static void 685 brgphy_fixup_jitter_bug(struct mii_softc *sc) 686 { 687 static const struct { 688 int reg; 689 uint16_t val; 690 } dspcode[] = { 691 { BRGPHY_MII_AUXCTL, 0x0c00 }, 692 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 693 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 694 { BRGPHY_MII_AUXCTL, 0x0400 }, 695 { 0, 0 }, 696 }; 697 int i; 698 699 for (i = 0; dspcode[i].reg != 0; i++) 700 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 701 } 702 703 static void 704 brgphy_ethernet_wirespeed(struct mii_softc *sc) 705 { 706 uint32_t val; 707 708 /* Enable Ethernet@WireSpeed. */ 709 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 710 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 711 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 712 } 713 714 static void 715 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 716 { 717 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 718 uint32_t val; 719 720 /* Set or clear jumbo frame settings in the PHY. */ 721 if (mtu > ETHER_MAX_LEN) { 722 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 723 /* BCM5401 PHY cannot read-modify-write. */ 724 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 725 } else { 726 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 727 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 728 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 729 val | BRGPHY_AUXCTL_LONG_PKT); 730 } 731 732 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 733 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 734 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 735 } else { 736 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 737 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 738 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 739 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 740 741 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 742 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 743 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 744 } 745 } 746 747 static void 748 brgphy_reset(struct mii_softc *sc) 749 { 750 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 751 struct bge_softc *bge_sc = NULL; 752 struct bce_softc *bce_sc = NULL; 753 struct ifnet *ifp; 754 755 mii_phy_reset(sc); 756 757 switch (bsc->mii_model) { 758 case MII_MODEL_xxBROADCOM_BCM5400: 759 bcm5401_load_dspcode(sc); 760 break; 761 case MII_MODEL_xxBROADCOM_BCM5401: 762 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 763 bcm5401_load_dspcode(sc); 764 break; 765 case MII_MODEL_xxBROADCOM_BCM5411: 766 bcm5411_load_dspcode(sc); 767 break; 768 } 769 770 ifp = sc->mii_pdata->mii_ifp; 771 772 /* Find the driver associated with this PHY. */ 773 if (strcmp(ifp->if_dname, "bge") == 0) { 774 bge_sc = ifp->if_softc; 775 } else if (strcmp(ifp->if_dname, "bce") == 0) { 776 bce_sc = ifp->if_softc; 777 } 778 779 /* Handle any NetXtreme/bge workarounds. */ 780 if (bge_sc) { 781 /* Fix up various bugs */ 782 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) 783 brgphy_fixup_5704_a0_bug(sc); 784 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) 785 brgphy_fixup_adc_bug(sc); 786 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) 787 brgphy_fixup_adjust_trim(sc); 788 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) 789 brgphy_fixup_ber_bug(sc); 790 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) 791 brgphy_fixup_crc_bug(sc); 792 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) 793 brgphy_fixup_jitter_bug(sc); 794 795 brgphy_jumbo_settings(sc, ifp->if_mtu); 796 797 /* 798 * Don't enable Ethernet@WireSpeed for the 5700 or the 799 * 5705 A1 and A2 chips. 800 */ 801 if (bge_sc->bge_asicrev != BGE_ASICREV_BCM5700 && 802 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A1 && 803 bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A2) 804 brgphy_ethernet_wirespeed(sc); 805 806 /* Enable Link LED on Dell boxes */ 807 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { 808 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 809 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 810 ~BRGPHY_PHY_EXTCTL_3_LED); 811 } 812 } else if (bce_sc) { 813 brgphy_fixup_ber_bug(sc); 814 brgphy_jumbo_settings(sc, ifp->if_mtu); 815 brgphy_ethernet_wirespeed(sc); 816 } 817 } 818