1 /* 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 35 * 1000mbps; all we need to negotiate here is full or half duplex. 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <machine/clock.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include "miidevs.h" 55 56 #include <dev/mii/brgphyreg.h> 57 58 #include "miibus_if.h" 59 60 static int brgphy_probe(device_t); 61 static int brgphy_attach(device_t); 62 63 static device_method_t brgphy_methods[] = { 64 /* device interface */ 65 DEVMETHOD(device_probe, brgphy_probe), 66 DEVMETHOD(device_attach, brgphy_attach), 67 DEVMETHOD(device_detach, mii_phy_detach), 68 DEVMETHOD(device_shutdown, bus_generic_shutdown), 69 { 0, 0 } 70 }; 71 72 static devclass_t brgphy_devclass; 73 74 static driver_t brgphy_driver = { 75 "brgphy", 76 brgphy_methods, 77 sizeof(struct mii_softc) 78 }; 79 80 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 81 82 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 83 static void brgphy_status(struct mii_softc *); 84 static int brgphy_mii_phy_auto(struct mii_softc *); 85 static void brgphy_reset(struct mii_softc *); 86 static void brgphy_loop(struct mii_softc *); 87 static void bcm5401_load_dspcode(struct mii_softc *); 88 static void bcm5411_load_dspcode(struct mii_softc *); 89 static void bcm5703_load_dspcode(struct mii_softc *); 90 static int brgphy_mii_model; 91 92 static int 93 brgphy_probe(dev) 94 device_t dev; 95 { 96 struct mii_attach_args *ma; 97 98 ma = device_get_ivars(dev); 99 100 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 101 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 102 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 103 return(0); 104 } 105 106 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 107 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 108 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 109 return(0); 110 } 111 112 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 113 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 114 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 115 return(0); 116 } 117 118 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 119 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 120 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 121 return(0); 122 } 123 124 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 125 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 126 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 127 return(0); 128 } 129 130 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 131 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 132 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 133 return(0); 134 } 135 136 return(ENXIO); 137 } 138 139 static int 140 brgphy_attach(dev) 141 device_t dev; 142 { 143 struct mii_softc *sc; 144 struct mii_attach_args *ma; 145 struct mii_data *mii; 146 const char *sep = ""; 147 148 sc = device_get_softc(dev); 149 ma = device_get_ivars(dev); 150 sc->mii_dev = device_get_parent(dev); 151 mii = device_get_softc(sc->mii_dev); 152 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 153 154 sc->mii_inst = mii->mii_instance; 155 sc->mii_phy = ma->mii_phyno; 156 sc->mii_service = brgphy_service; 157 sc->mii_pdata = mii; 158 159 sc->mii_flags |= MIIF_NOISOLATE; 160 mii->mii_instance++; 161 162 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 163 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 164 165 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 166 BMCR_ISO); 167 #if 0 168 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 169 BMCR_LOOP|BMCR_S100); 170 #endif 171 172 brgphy_mii_model = MII_MODEL(ma->mii_id2); 173 brgphy_reset(sc); 174 175 176 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 177 sc->mii_capabilities &= ~BMSR_ANEG; 178 device_printf(dev, " "); 179 mii_add_media(sc); 180 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 181 BRGPHY_BMCR_FDX); 182 PRINT(", 1000baseTX"); 183 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 184 PRINT("1000baseTX-FDX"); 185 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 186 PRINT("auto"); 187 188 printf("\n"); 189 #undef ADD 190 #undef PRINT 191 192 MIIBUS_MEDIAINIT(sc->mii_dev); 193 return(0); 194 } 195 196 static int 197 brgphy_service(sc, mii, cmd) 198 struct mii_softc *sc; 199 struct mii_data *mii; 200 int cmd; 201 { 202 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 203 int reg, speed, gig; 204 205 switch (cmd) { 206 case MII_POLLSTAT: 207 /* 208 * If we're not polling our PHY instance, just return. 209 */ 210 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 211 return (0); 212 break; 213 214 case MII_MEDIACHG: 215 /* 216 * If the media indicates a different PHY instance, 217 * isolate ourselves. 218 */ 219 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 220 reg = PHY_READ(sc, MII_BMCR); 221 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 222 return (0); 223 } 224 225 /* 226 * If the interface is not up, don't do anything. 227 */ 228 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 229 break; 230 231 brgphy_reset(sc); /* XXX hardware bug work-around */ 232 233 switch (IFM_SUBTYPE(ife->ifm_media)) { 234 case IFM_AUTO: 235 #ifdef foo 236 /* 237 * If we're already in auto mode, just return. 238 */ 239 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 240 return (0); 241 #endif 242 (void) brgphy_mii_phy_auto(sc); 243 break; 244 case IFM_1000_T: 245 speed = BRGPHY_S1000; 246 goto setit; 247 case IFM_100_TX: 248 speed = BRGPHY_S100; 249 goto setit; 250 case IFM_10_T: 251 speed = BRGPHY_S10; 252 setit: 253 brgphy_loop(sc); 254 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 255 speed |= BRGPHY_BMCR_FDX; 256 gig = BRGPHY_1000CTL_AFD; 257 } else { 258 gig = BRGPHY_1000CTL_AHD; 259 } 260 261 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 262 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 263 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 264 265 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 266 break; 267 268 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 269 PHY_WRITE(sc, BRGPHY_MII_BMCR, 270 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 271 272 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 273 break; 274 275 /* 276 * When settning the link manually, one side must 277 * be the master and the other the slave. However 278 * ifmedia doesn't give us a good way to specify 279 * this, so we fake it by using one of the LINK 280 * flags. If LINK0 is set, we program the PHY to 281 * be a master, otherwise it's a slave. 282 */ 283 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 284 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 285 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 286 } else { 287 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 288 gig|BRGPHY_1000CTL_MSE); 289 } 290 break; 291 #ifdef foo 292 case IFM_NONE: 293 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 294 break; 295 #endif 296 case IFM_100_T4: 297 default: 298 return (EINVAL); 299 } 300 break; 301 302 case MII_TICK: 303 /* 304 * If we're not currently selected, just return. 305 */ 306 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 307 return (0); 308 309 /* 310 * Is the interface even up? 311 */ 312 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 313 return (0); 314 315 /* 316 * Only used for autonegotiation. 317 */ 318 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 319 break; 320 321 /* 322 * Check to see if we have link. If we do, we don't 323 * need to restart the autonegotiation process. Read 324 * the BMSR twice in case it's latched. 325 */ 326 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 327 if (reg & BRGPHY_AUXSTS_LINK) 328 break; 329 330 /* 331 * Only retry autonegotiation every 5 seconds. 332 */ 333 if (++sc->mii_ticks != 5) 334 return (0); 335 336 sc->mii_ticks = 0; 337 brgphy_mii_phy_auto(sc); 338 return (0); 339 } 340 341 /* Update the media status. */ 342 brgphy_status(sc); 343 344 /* 345 * Callback if something changed. Note that we need to poke 346 * the DSP on the Broadcom PHYs if the media changes. 347 * 348 */ 349 if (sc->mii_media_active != mii->mii_media_active || 350 sc->mii_media_status != mii->mii_media_status || 351 cmd == MII_MEDIACHG) { 352 mii_phy_update(sc, cmd); 353 switch (brgphy_mii_model) { 354 case MII_MODEL_xxBROADCOM_BCM5401: 355 bcm5401_load_dspcode(sc); 356 break; 357 case MII_MODEL_xxBROADCOM_BCM5411: 358 bcm5411_load_dspcode(sc); 359 break; 360 } 361 } 362 return (0); 363 } 364 365 static void 366 brgphy_status(sc) 367 struct mii_softc *sc; 368 { 369 struct mii_data *mii = sc->mii_pdata; 370 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 371 int bmsr, bmcr; 372 373 mii->mii_media_status = IFM_AVALID; 374 mii->mii_media_active = IFM_ETHER; 375 376 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 377 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 378 mii->mii_media_status |= IFM_ACTIVE; 379 380 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 381 382 if (bmcr & BRGPHY_BMCR_LOOP) 383 mii->mii_media_active |= IFM_LOOP; 384 385 if (bmcr & BRGPHY_BMCR_AUTOEN) { 386 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 387 /* Erg, still trying, I guess... */ 388 mii->mii_media_active |= IFM_NONE; 389 return; 390 } 391 392 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 393 BRGPHY_AUXSTS_AN_RES) { 394 case BRGPHY_RES_1000FD: 395 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 396 break; 397 case BRGPHY_RES_1000HD: 398 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 399 break; 400 case BRGPHY_RES_100FD: 401 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 402 break; 403 case BRGPHY_RES_100T4: 404 mii->mii_media_active |= IFM_100_T4; 405 break; 406 case BRGPHY_RES_100HD: 407 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 408 break; 409 case BRGPHY_RES_10FD: 410 mii->mii_media_active |= IFM_10_T | IFM_FDX; 411 break; 412 case BRGPHY_RES_10HD: 413 mii->mii_media_active |= IFM_10_T | IFM_HDX; 414 break; 415 default: 416 mii->mii_media_active |= IFM_NONE; 417 break; 418 } 419 return; 420 } 421 422 mii->mii_media_active = ife->ifm_media; 423 424 return; 425 } 426 427 428 static int 429 brgphy_mii_phy_auto(mii) 430 struct mii_softc *mii; 431 { 432 int ktcr = 0; 433 434 brgphy_loop(mii); 435 brgphy_reset(mii); 436 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 437 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 438 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 439 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 440 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 441 DELAY(1000); 442 PHY_WRITE(mii, BRGPHY_MII_ANAR, 443 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 444 DELAY(1000); 445 PHY_WRITE(mii, BRGPHY_MII_BMCR, 446 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 447 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 448 return (EJUSTRETURN); 449 } 450 451 static void 452 brgphy_loop(struct mii_softc *sc) 453 { 454 u_int32_t bmsr; 455 int i; 456 457 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 458 for (i = 0; i < 15000; i++) { 459 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 460 if (!(bmsr & BRGPHY_BMSR_LINK)) { 461 #if 0 462 device_printf(sc->mii_dev, "looped %d\n", i); 463 #endif 464 break; 465 } 466 DELAY(10); 467 } 468 } 469 470 /* Turn off tap power management on 5401. */ 471 static void 472 bcm5401_load_dspcode(struct mii_softc *sc) 473 { 474 static const struct { 475 int reg; 476 uint16_t val; 477 } dspcode[] = { 478 { BRGPHY_MII_AUXCTL, 0x0c20 }, 479 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 480 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 481 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 482 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 483 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 484 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 485 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 486 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 487 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 488 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 489 { 0, 0 }, 490 }; 491 int i; 492 493 for (i = 0; dspcode[i].reg != 0; i++) 494 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 495 DELAY(40); 496 } 497 498 static void 499 bcm5411_load_dspcode(struct mii_softc *sc) 500 { 501 static const struct { 502 int reg; 503 uint16_t val; 504 } dspcode[] = { 505 { 0x1c, 0x8c23 }, 506 { 0x1c, 0x8ca3 }, 507 { 0x1c, 0x8c23 }, 508 { 0, 0 }, 509 }; 510 int i; 511 512 for (i = 0; dspcode[i].reg != 0; i++) 513 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 514 } 515 516 static void 517 bcm5703_load_dspcode(struct mii_softc *sc) 518 { 519 static const struct { 520 int reg; 521 uint16_t val; 522 } dspcode[] = { 523 { BRGPHY_MII_AUXCTL, 0x0c00 }, 524 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 525 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 526 { 0, 0 }, 527 }; 528 int i; 529 530 for (i = 0; dspcode[i].reg != 0; i++) 531 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 532 } 533 534 static void 535 bcm5704_load_dspcode(struct mii_softc *sc) 536 { 537 static const struct { 538 int reg; 539 u_int16_t val; 540 } dspcode[] = { 541 { 0x1c, 0x8d68 }, 542 { 0x1c, 0x8d68 }, 543 { 0, 0 }, 544 }; 545 int i; 546 547 for (i = 0; dspcode[i].reg != 0; i++) 548 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 549 } 550 551 static void 552 brgphy_reset(struct mii_softc *sc) 553 { 554 u_int32_t val; 555 556 mii_phy_reset(sc); 557 558 switch (brgphy_mii_model) { 559 case MII_MODEL_xxBROADCOM_BCM5401: 560 bcm5401_load_dspcode(sc); 561 break; 562 case MII_MODEL_xxBROADCOM_BCM5411: 563 bcm5411_load_dspcode(sc); 564 break; 565 case MII_MODEL_xxBROADCOM_BCM5703: 566 bcm5703_load_dspcode(sc); 567 break; 568 case MII_MODEL_xxBROADCOM_BCM5704: 569 bcm5704_load_dspcode(sc); 570 break; 571 } 572 573 /* Enable Ethernet@WireSpeed. */ 574 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 575 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 576 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) || (1 << 4)); 577 } 578