1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/brgphyreg.h> 56 #include <net/if_arp.h> 57 #include <machine/bus.h> 58 #include <dev/bge/if_bgereg.h> 59 #include <dev/bce/if_bcereg.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 #include "miibus_if.h" 65 66 static int brgphy_probe(device_t); 67 static int brgphy_attach(device_t); 68 69 struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int serdes_flags; /* Keeps track of the serdes type used */ 72 #define BRGPHY_5706S 0x0001 73 #define BRGPHY_5708S 0x0002 74 #define BRGPHY_NOANWAIT 0x0004 75 #define BRGPHY_5709S 0x0008 76 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 77 }; 78 79 static device_method_t brgphy_methods[] = { 80 /* device interface */ 81 DEVMETHOD(device_probe, brgphy_probe), 82 DEVMETHOD(device_attach, brgphy_attach), 83 DEVMETHOD(device_detach, mii_phy_detach), 84 DEVMETHOD(device_shutdown, bus_generic_shutdown), 85 DEVMETHOD_END 86 }; 87 88 static devclass_t brgphy_devclass; 89 90 static driver_t brgphy_driver = { 91 "brgphy", 92 brgphy_methods, 93 sizeof(struct brgphy_softc) 94 }; 95 96 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 97 98 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 99 static void brgphy_setmedia(struct mii_softc *, int); 100 static void brgphy_status(struct mii_softc *); 101 static void brgphy_mii_phy_auto(struct mii_softc *, int); 102 static void brgphy_reset(struct mii_softc *); 103 static void brgphy_enable_loopback(struct mii_softc *); 104 static void bcm5401_load_dspcode(struct mii_softc *); 105 static void bcm5411_load_dspcode(struct mii_softc *); 106 static void bcm54k2_load_dspcode(struct mii_softc *); 107 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 108 static void brgphy_fixup_adc_bug(struct mii_softc *); 109 static void brgphy_fixup_adjust_trim(struct mii_softc *); 110 static void brgphy_fixup_ber_bug(struct mii_softc *); 111 static void brgphy_fixup_crc_bug(struct mii_softc *); 112 static void brgphy_fixup_jitter_bug(struct mii_softc *); 113 static void brgphy_ethernet_wirespeed(struct mii_softc *); 114 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 115 116 static const struct mii_phydesc brgphys[] = { 117 MII_PHY_DESC(BROADCOM, BCM5400), 118 MII_PHY_DESC(BROADCOM, BCM5401), 119 MII_PHY_DESC(BROADCOM, BCM5411), 120 MII_PHY_DESC(BROADCOM, BCM54K2), 121 MII_PHY_DESC(BROADCOM, BCM5701), 122 MII_PHY_DESC(BROADCOM, BCM5703), 123 MII_PHY_DESC(BROADCOM, BCM5704), 124 MII_PHY_DESC(BROADCOM, BCM5705), 125 MII_PHY_DESC(BROADCOM, BCM5706), 126 MII_PHY_DESC(BROADCOM, BCM5714), 127 MII_PHY_DESC(BROADCOM, BCM5421), 128 MII_PHY_DESC(BROADCOM, BCM5750), 129 MII_PHY_DESC(BROADCOM, BCM5752), 130 MII_PHY_DESC(BROADCOM, BCM5780), 131 MII_PHY_DESC(BROADCOM, BCM5708C), 132 MII_PHY_DESC(BROADCOM2, BCM5482), 133 MII_PHY_DESC(BROADCOM2, BCM5708S), 134 MII_PHY_DESC(BROADCOM2, BCM5709C), 135 MII_PHY_DESC(BROADCOM2, BCM5709S), 136 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 137 MII_PHY_DESC(BROADCOM2, BCM5722), 138 MII_PHY_DESC(BROADCOM2, BCM5755), 139 MII_PHY_DESC(BROADCOM2, BCM5754), 140 MII_PHY_DESC(BROADCOM2, BCM5761), 141 MII_PHY_DESC(BROADCOM2, BCM5784), 142 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 143 MII_PHY_DESC(BROADCOM2, BCM5785), 144 #endif 145 MII_PHY_DESC(BROADCOM3, BCM5717C), 146 MII_PHY_DESC(BROADCOM3, BCM5719C), 147 MII_PHY_DESC(BROADCOM3, BCM5720C), 148 MII_PHY_DESC(BROADCOM3, BCM57765), 149 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 150 MII_PHY_END 151 }; 152 153 static const struct mii_phy_funcs brgphy_funcs = { 154 brgphy_service, 155 brgphy_status, 156 brgphy_reset 157 }; 158 159 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 160 #define HS21_BCM_CHIPID 0x57081021 161 162 static int 163 detect_hs21(struct bce_softc *bce_sc) 164 { 165 char *sysenv; 166 int found; 167 168 found = 0; 169 if (bce_sc->bce_chipid == HS21_BCM_CHIPID) { 170 sysenv = getenv("smbios.system.product"); 171 if (sysenv != NULL) { 172 if (strncmp(sysenv, HS21_PRODUCT_ID, 173 strlen(HS21_PRODUCT_ID)) == 0) 174 found = 1; 175 freeenv(sysenv); 176 } 177 } 178 return (found); 179 } 180 181 /* Search for our PHY in the list of known PHYs */ 182 static int 183 brgphy_probe(device_t dev) 184 { 185 186 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 187 } 188 189 /* Attach the PHY to the MII bus */ 190 static int 191 brgphy_attach(device_t dev) 192 { 193 struct brgphy_softc *bsc; 194 struct bge_softc *bge_sc = NULL; 195 struct bce_softc *bce_sc = NULL; 196 struct mii_softc *sc; 197 struct ifnet *ifp; 198 199 bsc = device_get_softc(dev); 200 sc = &bsc->mii_sc; 201 202 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 203 &brgphy_funcs, 0); 204 205 bsc->serdes_flags = 0; 206 207 /* Handle any special cases based on the PHY ID */ 208 switch (sc->mii_mpd_oui) { 209 case MII_OUI_BROADCOM: 210 switch (sc->mii_mpd_model) { 211 case MII_MODEL_BROADCOM_BCM5706: 212 case MII_MODEL_BROADCOM_BCM5714: 213 /* 214 * The 5464 PHY used in the 5706 supports both copper 215 * and fiber interfaces over GMII. Need to check the 216 * shadow registers to see which mode is actually 217 * in effect, and therefore whether we have 5706C or 218 * 5706S. 219 */ 220 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 221 BRGPHY_SHADOW_1C_MODE_CTRL); 222 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 223 BRGPHY_SHADOW_1C_ENA_1000X) { 224 bsc->serdes_flags |= BRGPHY_5706S; 225 sc->mii_flags |= MIIF_HAVEFIBER; 226 } 227 break; 228 } break; 229 case MII_OUI_BROADCOM2: 230 switch (sc->mii_mpd_model) { 231 case MII_MODEL_BROADCOM2_BCM5708S: 232 bsc->serdes_flags |= BRGPHY_5708S; 233 sc->mii_flags |= MIIF_HAVEFIBER; 234 break; 235 case MII_MODEL_BROADCOM2_BCM5709S: 236 bsc->serdes_flags |= BRGPHY_5709S; 237 sc->mii_flags |= MIIF_HAVEFIBER; 238 break; 239 } 240 break; 241 } 242 243 ifp = sc->mii_pdata->mii_ifp; 244 245 /* Find the MAC driver associated with this PHY. */ 246 if (strcmp(ifp->if_dname, "bge") == 0) { 247 bge_sc = ifp->if_softc; 248 } else if (strcmp(ifp->if_dname, "bce") == 0) { 249 bce_sc = ifp->if_softc; 250 } 251 252 PHY_RESET(sc); 253 254 /* Read the PHY's capabilities. */ 255 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 256 if (sc->mii_capabilities & BMSR_EXTSTAT) 257 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 258 device_printf(dev, " "); 259 260 #define ADD(m, c) ifmedia_add(&sc->mii_pdata->mii_media, (m), (c), NULL) 261 262 /* Add the supported media types */ 263 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 264 mii_phy_add_media(sc); 265 printf("\n"); 266 } else { 267 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 268 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 269 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 270 printf("1000baseSX-FDX, "); 271 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 272 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 273 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 274 printf("2500baseSX-FDX, "); 275 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 276 (detect_hs21(bce_sc) != 0)) { 277 /* 278 * There appears to be certain silicon revision 279 * in IBM HS21 blades that is having issues with 280 * this driver wating for the auto-negotiation to 281 * complete. This happens with a specific chip id 282 * only and when the 1000baseSX-FDX is the only 283 * mode. Workaround this issue since it's unlikely 284 * to be ever addressed. 285 */ 286 printf("auto-neg workaround, "); 287 bsc->serdes_flags |= BRGPHY_NOANWAIT; 288 } 289 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 290 printf("auto\n"); 291 } 292 293 #undef ADD 294 MIIBUS_MEDIAINIT(sc->mii_dev); 295 return (0); 296 } 297 298 static int 299 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 300 { 301 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 302 int val; 303 304 switch (cmd) { 305 case MII_POLLSTAT: 306 break; 307 case MII_MEDIACHG: 308 /* If the interface is not up, don't do anything. */ 309 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 310 break; 311 312 /* Todo: Why is this here? Is it really needed? */ 313 PHY_RESET(sc); /* XXX hardware bug work-around */ 314 315 switch (IFM_SUBTYPE(ife->ifm_media)) { 316 case IFM_AUTO: 317 brgphy_mii_phy_auto(sc, ife->ifm_media); 318 break; 319 case IFM_2500_SX: 320 case IFM_1000_SX: 321 case IFM_1000_T: 322 case IFM_100_TX: 323 case IFM_10_T: 324 brgphy_setmedia(sc, ife->ifm_media); 325 break; 326 default: 327 return (EINVAL); 328 } 329 break; 330 case MII_TICK: 331 /* Bail if the interface isn't up. */ 332 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 333 return (0); 334 335 336 /* Bail if autoneg isn't in process. */ 337 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 338 sc->mii_ticks = 0; 339 break; 340 } 341 342 /* 343 * Check to see if we have link. If we do, we don't 344 * need to restart the autonegotiation process. 345 */ 346 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 347 if (val & BMSR_LINK) { 348 sc->mii_ticks = 0; /* Reset autoneg timer. */ 349 break; 350 } 351 352 /* Announce link loss right after it happens. */ 353 if (sc->mii_ticks++ == 0) 354 break; 355 356 /* Only retry autonegotiation every mii_anegticks seconds. */ 357 if (sc->mii_ticks <= sc->mii_anegticks) 358 break; 359 360 361 /* Retry autonegotiation */ 362 sc->mii_ticks = 0; 363 brgphy_mii_phy_auto(sc, ife->ifm_media); 364 break; 365 } 366 367 /* Update the media status. */ 368 PHY_STATUS(sc); 369 370 /* 371 * Callback if something changed. Note that we need to poke 372 * the DSP on the Broadcom PHYs if the media changes. 373 */ 374 if (sc->mii_media_active != mii->mii_media_active || 375 sc->mii_media_status != mii->mii_media_status || 376 cmd == MII_MEDIACHG) { 377 switch (sc->mii_mpd_oui) { 378 case MII_OUI_BROADCOM: 379 switch (sc->mii_mpd_model) { 380 case MII_MODEL_BROADCOM_BCM5400: 381 bcm5401_load_dspcode(sc); 382 break; 383 case MII_MODEL_BROADCOM_BCM5401: 384 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 385 bcm5401_load_dspcode(sc); 386 break; 387 case MII_MODEL_BROADCOM_BCM5411: 388 bcm5411_load_dspcode(sc); 389 break; 390 case MII_MODEL_BROADCOM_BCM54K2: 391 bcm54k2_load_dspcode(sc); 392 break; 393 } 394 break; 395 } 396 } 397 mii_phy_update(sc, cmd); 398 return (0); 399 } 400 401 /****************************************************************************/ 402 /* Sets the PHY link speed. */ 403 /* */ 404 /* Returns: */ 405 /* None */ 406 /****************************************************************************/ 407 static void 408 brgphy_setmedia(struct mii_softc *sc, int media) 409 { 410 int bmcr = 0, gig; 411 412 switch (IFM_SUBTYPE(media)) { 413 case IFM_2500_SX: 414 break; 415 case IFM_1000_SX: 416 case IFM_1000_T: 417 bmcr = BRGPHY_S1000; 418 break; 419 case IFM_100_TX: 420 bmcr = BRGPHY_S100; 421 break; 422 case IFM_10_T: 423 default: 424 bmcr = BRGPHY_S10; 425 break; 426 } 427 428 if ((media & IFM_FDX) != 0) { 429 bmcr |= BRGPHY_BMCR_FDX; 430 gig = BRGPHY_1000CTL_AFD; 431 } else { 432 gig = BRGPHY_1000CTL_AHD; 433 } 434 435 /* Force loopback to disconnect PHY from Ethernet medium. */ 436 brgphy_enable_loopback(sc); 437 438 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 439 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 440 441 if (IFM_SUBTYPE(media) != IFM_1000_T && 442 IFM_SUBTYPE(media) != IFM_1000_SX) { 443 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 444 return; 445 } 446 447 if (IFM_SUBTYPE(media) == IFM_1000_T) { 448 gig |= BRGPHY_1000CTL_MSE; 449 if ((media & IFM_ETH_MASTER) != 0) 450 gig |= BRGPHY_1000CTL_MSC; 451 } 452 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 453 PHY_WRITE(sc, BRGPHY_MII_BMCR, 454 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 455 } 456 457 /****************************************************************************/ 458 /* Set the media status based on the PHY settings. */ 459 /* */ 460 /* Returns: */ 461 /* None */ 462 /****************************************************************************/ 463 static void 464 brgphy_status(struct mii_softc *sc) 465 { 466 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 467 struct mii_data *mii = sc->mii_pdata; 468 int aux, bmcr, bmsr, val, xstat; 469 u_int flowstat; 470 471 mii->mii_media_status = IFM_AVALID; 472 mii->mii_media_active = IFM_ETHER; 473 474 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 475 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 476 477 if (bmcr & BRGPHY_BMCR_LOOP) { 478 mii->mii_media_active |= IFM_LOOP; 479 } 480 481 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 482 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 483 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 484 /* Erg, still trying, I guess... */ 485 mii->mii_media_active |= IFM_NONE; 486 return; 487 } 488 489 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 490 /* 491 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 492 * wedges at least the PHY of BCM5704 (but not others). 493 */ 494 flowstat = mii_phy_flowstatus(sc); 495 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 496 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 497 498 /* If copper link is up, get the negotiated speed/duplex. */ 499 if (aux & BRGPHY_AUXSTS_LINK) { 500 mii->mii_media_status |= IFM_ACTIVE; 501 switch (aux & BRGPHY_AUXSTS_AN_RES) { 502 case BRGPHY_RES_1000FD: 503 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 504 case BRGPHY_RES_1000HD: 505 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 506 case BRGPHY_RES_100FD: 507 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 508 case BRGPHY_RES_100T4: 509 mii->mii_media_active |= IFM_100_T4; break; 510 case BRGPHY_RES_100HD: 511 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 512 case BRGPHY_RES_10FD: 513 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 514 case BRGPHY_RES_10HD: 515 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 516 default: 517 mii->mii_media_active |= IFM_NONE; break; 518 } 519 520 if ((mii->mii_media_active & IFM_FDX) != 0) 521 mii->mii_media_active |= flowstat; 522 523 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 524 (xstat & BRGPHY_1000STS_MSR) != 0) 525 mii->mii_media_active |= IFM_ETH_MASTER; 526 } 527 } else { 528 /* Todo: Add support for flow control. */ 529 /* If serdes link is up, get the negotiated speed/duplex. */ 530 if (bmsr & BRGPHY_BMSR_LINK) { 531 mii->mii_media_status |= IFM_ACTIVE; 532 } 533 534 /* Check the link speed/duplex based on the PHY type. */ 535 if (bsc->serdes_flags & BRGPHY_5706S) { 536 mii->mii_media_active |= IFM_1000_SX; 537 538 /* If autoneg enabled, read negotiated duplex settings */ 539 if (bmcr & BRGPHY_BMCR_AUTOEN) { 540 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 541 if (val & BRGPHY_SERDES_ANAR_FDX) 542 mii->mii_media_active |= IFM_FDX; 543 else 544 mii->mii_media_active |= IFM_HDX; 545 } 546 } else if (bsc->serdes_flags & BRGPHY_5708S) { 547 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 548 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 549 550 /* Check for MRBE auto-negotiated speed results. */ 551 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 552 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 553 mii->mii_media_active |= IFM_10_FL; break; 554 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 555 mii->mii_media_active |= IFM_100_FX; break; 556 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 557 mii->mii_media_active |= IFM_1000_SX; break; 558 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 559 mii->mii_media_active |= IFM_2500_SX; break; 560 } 561 562 /* Check for MRBE auto-negotiated duplex results. */ 563 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 564 mii->mii_media_active |= IFM_FDX; 565 else 566 mii->mii_media_active |= IFM_HDX; 567 } else if (bsc->serdes_flags & BRGPHY_5709S) { 568 /* Select GP Status Block of the AN MMD, get autoneg results. */ 569 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 570 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 571 572 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 573 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 574 575 /* Check for MRBE auto-negotiated speed results. */ 576 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 577 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 578 mii->mii_media_active |= IFM_10_FL; break; 579 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 580 mii->mii_media_active |= IFM_100_FX; break; 581 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 582 mii->mii_media_active |= IFM_1000_SX; break; 583 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 584 mii->mii_media_active |= IFM_2500_SX; break; 585 } 586 587 /* Check for MRBE auto-negotiated duplex results. */ 588 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 589 mii->mii_media_active |= IFM_FDX; 590 else 591 mii->mii_media_active |= IFM_HDX; 592 } 593 } 594 } 595 596 static void 597 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 598 { 599 int anar, ktcr = 0; 600 601 PHY_RESET(sc); 602 603 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 604 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 605 if ((media & IFM_FLOW) != 0 || 606 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 607 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 608 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 609 } else { 610 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 611 if ((media & IFM_FLOW) != 0 || 612 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 613 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 614 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 615 } 616 617 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 618 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 619 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 620 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 621 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 622 623 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 624 BRGPHY_BMCR_STARTNEG); 625 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 626 } 627 628 /* Enable loopback to force the link down. */ 629 static void 630 brgphy_enable_loopback(struct mii_softc *sc) 631 { 632 int i; 633 634 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 635 for (i = 0; i < 15000; i++) { 636 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 637 break; 638 DELAY(10); 639 } 640 } 641 642 /* Turn off tap power management on 5401. */ 643 static void 644 bcm5401_load_dspcode(struct mii_softc *sc) 645 { 646 static const struct { 647 int reg; 648 uint16_t val; 649 } dspcode[] = { 650 { BRGPHY_MII_AUXCTL, 0x0c20 }, 651 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 652 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 653 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 654 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 655 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 656 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 657 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 658 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 659 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 660 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 661 { 0, 0 }, 662 }; 663 int i; 664 665 for (i = 0; dspcode[i].reg != 0; i++) 666 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 667 DELAY(40); 668 } 669 670 static void 671 bcm5411_load_dspcode(struct mii_softc *sc) 672 { 673 static const struct { 674 int reg; 675 uint16_t val; 676 } dspcode[] = { 677 { 0x1c, 0x8c23 }, 678 { 0x1c, 0x8ca3 }, 679 { 0x1c, 0x8c23 }, 680 { 0, 0 }, 681 }; 682 int i; 683 684 for (i = 0; dspcode[i].reg != 0; i++) 685 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 686 } 687 688 void 689 bcm54k2_load_dspcode(struct mii_softc *sc) 690 { 691 static const struct { 692 int reg; 693 uint16_t val; 694 } dspcode[] = { 695 { 4, 0x01e1 }, 696 { 9, 0x0300 }, 697 { 0, 0 }, 698 }; 699 int i; 700 701 for (i = 0; dspcode[i].reg != 0; i++) 702 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 703 704 } 705 706 static void 707 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 708 { 709 static const struct { 710 int reg; 711 uint16_t val; 712 } dspcode[] = { 713 { 0x1c, 0x8d68 }, 714 { 0x1c, 0x8d68 }, 715 { 0, 0 }, 716 }; 717 int i; 718 719 for (i = 0; dspcode[i].reg != 0; i++) 720 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 721 } 722 723 static void 724 brgphy_fixup_adc_bug(struct mii_softc *sc) 725 { 726 static const struct { 727 int reg; 728 uint16_t val; 729 } dspcode[] = { 730 { BRGPHY_MII_AUXCTL, 0x0c00 }, 731 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 732 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 733 { 0, 0 }, 734 }; 735 int i; 736 737 for (i = 0; dspcode[i].reg != 0; i++) 738 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 739 } 740 741 static void 742 brgphy_fixup_adjust_trim(struct mii_softc *sc) 743 { 744 static const struct { 745 int reg; 746 uint16_t val; 747 } dspcode[] = { 748 { BRGPHY_MII_AUXCTL, 0x0c00 }, 749 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 750 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 751 { BRGPHY_MII_TEST1, 0x0014 }, 752 { BRGPHY_MII_AUXCTL, 0x0400 }, 753 { 0, 0 }, 754 }; 755 int i; 756 757 for (i = 0; dspcode[i].reg != 0; i++) 758 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 759 } 760 761 static void 762 brgphy_fixup_ber_bug(struct mii_softc *sc) 763 { 764 static const struct { 765 int reg; 766 uint16_t val; 767 } dspcode[] = { 768 { BRGPHY_MII_AUXCTL, 0x0c00 }, 769 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 770 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 771 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 772 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 773 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 774 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 775 { BRGPHY_MII_AUXCTL, 0x0400 }, 776 { 0, 0 }, 777 }; 778 int i; 779 780 for (i = 0; dspcode[i].reg != 0; i++) 781 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 782 } 783 784 static void 785 brgphy_fixup_crc_bug(struct mii_softc *sc) 786 { 787 static const struct { 788 int reg; 789 uint16_t val; 790 } dspcode[] = { 791 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 792 { 0x1c, 0x8c68 }, 793 { 0x1c, 0x8d68 }, 794 { 0x1c, 0x8c68 }, 795 { 0, 0 }, 796 }; 797 int i; 798 799 for (i = 0; dspcode[i].reg != 0; i++) 800 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 801 } 802 803 static void 804 brgphy_fixup_jitter_bug(struct mii_softc *sc) 805 { 806 static const struct { 807 int reg; 808 uint16_t val; 809 } dspcode[] = { 810 { BRGPHY_MII_AUXCTL, 0x0c00 }, 811 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 812 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 813 { BRGPHY_MII_AUXCTL, 0x0400 }, 814 { 0, 0 }, 815 }; 816 int i; 817 818 for (i = 0; dspcode[i].reg != 0; i++) 819 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 820 } 821 822 static void 823 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 824 { 825 uint32_t val; 826 827 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 828 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 829 val &= ~(1 << 8); 830 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 831 832 } 833 834 static void 835 brgphy_ethernet_wirespeed(struct mii_softc *sc) 836 { 837 uint32_t val; 838 839 /* Enable Ethernet@WireSpeed. */ 840 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 841 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 842 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 843 } 844 845 static void 846 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 847 { 848 uint32_t val; 849 850 /* Set or clear jumbo frame settings in the PHY. */ 851 if (mtu > ETHER_MAX_LEN) { 852 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 853 /* BCM5401 PHY cannot read-modify-write. */ 854 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 855 } else { 856 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 857 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 858 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 859 val | BRGPHY_AUXCTL_LONG_PKT); 860 } 861 862 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 863 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 864 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 865 } else { 866 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 867 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 868 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 869 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 870 871 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 872 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 873 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 874 } 875 } 876 877 static void 878 brgphy_reset(struct mii_softc *sc) 879 { 880 struct bge_softc *bge_sc = NULL; 881 struct bce_softc *bce_sc = NULL; 882 struct ifnet *ifp; 883 int i, val; 884 885 /* 886 * Perform a reset. Note that at least some Broadcom PHYs default to 887 * being powered down as well as isolated after a reset but don't work 888 * if one or both of these bits are cleared. However, they just work 889 * fine if both bits remain set, so we don't use mii_phy_reset() here. 890 */ 891 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 892 893 /* Wait 100ms for it to complete. */ 894 for (i = 0; i < 100; i++) { 895 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 896 break; 897 DELAY(1000); 898 } 899 900 /* Handle any PHY specific procedures following the reset. */ 901 switch (sc->mii_mpd_oui) { 902 case MII_OUI_BROADCOM: 903 switch (sc->mii_mpd_model) { 904 case MII_MODEL_BROADCOM_BCM5400: 905 bcm5401_load_dspcode(sc); 906 break; 907 case MII_MODEL_BROADCOM_BCM5401: 908 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 909 bcm5401_load_dspcode(sc); 910 break; 911 case MII_MODEL_BROADCOM_BCM5411: 912 bcm5411_load_dspcode(sc); 913 break; 914 case MII_MODEL_BROADCOM_BCM54K2: 915 bcm54k2_load_dspcode(sc); 916 break; 917 } 918 break; 919 } 920 921 ifp = sc->mii_pdata->mii_ifp; 922 923 /* Find the driver associated with this PHY. */ 924 if (strcmp(ifp->if_dname, "bge") == 0) { 925 bge_sc = ifp->if_softc; 926 } else if (strcmp(ifp->if_dname, "bce") == 0) { 927 bce_sc = ifp->if_softc; 928 } 929 930 if (bge_sc) { 931 /* Fix up various bugs */ 932 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 933 brgphy_fixup_5704_a0_bug(sc); 934 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 935 brgphy_fixup_adc_bug(sc); 936 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 937 brgphy_fixup_adjust_trim(sc); 938 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 939 brgphy_fixup_ber_bug(sc); 940 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 941 brgphy_fixup_crc_bug(sc); 942 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 943 brgphy_fixup_jitter_bug(sc); 944 945 brgphy_jumbo_settings(sc, ifp->if_mtu); 946 947 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 948 brgphy_ethernet_wirespeed(sc); 949 950 /* Enable Link LED on Dell boxes */ 951 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 952 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 953 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 954 ~BRGPHY_PHY_EXTCTL_3_LED); 955 } 956 957 /* Adjust output voltage (From Linux driver) */ 958 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 959 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 960 } else if (bce_sc) { 961 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 962 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 963 964 /* Store autoneg capabilities/results in digital block (Page 0) */ 965 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 966 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 967 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 968 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 969 970 /* Enable fiber mode and autodetection */ 971 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 972 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 973 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 974 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 975 976 /* Enable parallel detection */ 977 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 978 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 979 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 980 981 /* Advertise 2.5G support through next page during autoneg */ 982 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 983 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 984 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 985 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 986 987 /* Increase TX signal amplitude */ 988 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 989 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 990 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 991 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 992 BRGPHY_5708S_TX_MISC_PG5); 993 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 994 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 995 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 996 BRGPHY_5708S_DIG_PG0); 997 } 998 999 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1000 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1001 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1002 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1003 BRGPHY_5708S_TX_MISC_PG5); 1004 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1005 bce_sc->bce_port_hw_cfg & 1006 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1007 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1008 BRGPHY_5708S_DIG_PG0); 1009 } 1010 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1011 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1012 1013 /* Select the SerDes Digital block of the AN MMD. */ 1014 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1015 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1016 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1017 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1018 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1019 1020 /* Select the Over 1G block of the AN MMD. */ 1021 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1022 1023 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1024 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1025 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1026 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1027 else 1028 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1029 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1030 1031 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1032 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1033 1034 /* Enable MRBE speed autoneg. */ 1035 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1036 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1037 BRGPHY_MRBE_MSG_PG5_NP_T2; 1038 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1039 1040 /* Select the Clause 73 User B0 block of the AN MMD. */ 1041 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1042 1043 /* Enable MRBE speed autoneg. */ 1044 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1045 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1046 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1047 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1048 1049 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1050 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1051 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1052 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1053 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1054 brgphy_fixup_disable_early_dac(sc); 1055 1056 brgphy_jumbo_settings(sc, ifp->if_mtu); 1057 brgphy_ethernet_wirespeed(sc); 1058 } else { 1059 brgphy_fixup_ber_bug(sc); 1060 brgphy_jumbo_settings(sc, ifp->if_mtu); 1061 brgphy_ethernet_wirespeed(sc); 1062 } 1063 } 1064 } 1065