1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 48 49 #include <net/if.h> 50 #include <net/ethernet.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/brgphyreg.h> 58 #include <net/if_arp.h> 59 #include <machine/bus.h> 60 #include <dev/bge/if_bgereg.h> 61 #include <dev/bce/if_bcereg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 66 #include "miibus_if.h" 67 68 static int brgphy_probe(device_t); 69 static int brgphy_attach(device_t); 70 71 static device_method_t brgphy_methods[] = { 72 /* device interface */ 73 DEVMETHOD(device_probe, brgphy_probe), 74 DEVMETHOD(device_attach, brgphy_attach), 75 DEVMETHOD(device_detach, mii_phy_detach), 76 DEVMETHOD(device_shutdown, bus_generic_shutdown), 77 { 0, 0 } 78 }; 79 80 static devclass_t brgphy_devclass; 81 82 static driver_t brgphy_driver = { 83 "brgphy", 84 brgphy_methods, 85 sizeof(struct mii_softc) 86 }; 87 88 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 89 90 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 91 static void brgphy_status(struct mii_softc *); 92 static int brgphy_mii_phy_auto(struct mii_softc *); 93 static void brgphy_reset(struct mii_softc *); 94 static void brgphy_loop(struct mii_softc *); 95 static void bcm5401_load_dspcode(struct mii_softc *); 96 static void bcm5411_load_dspcode(struct mii_softc *); 97 static void bcm5703_load_dspcode(struct mii_softc *); 98 static void bcm5750_load_dspcode(struct mii_softc *); 99 static int brgphy_mii_model; 100 101 static int 102 brgphy_probe(device_t dev) 103 { 104 struct mii_attach_args *ma; 105 106 ma = device_get_ivars(dev); 107 108 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 109 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 110 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 111 return(0); 112 } 113 114 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 115 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 116 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 117 return(0); 118 } 119 120 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 121 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 122 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 123 return(0); 124 } 125 126 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 127 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 128 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 129 return(0); 130 } 131 132 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 133 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 134 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 135 return(0); 136 } 137 138 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 139 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 140 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 141 return(0); 142 } 143 144 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 145 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 146 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 147 return(0); 148 } 149 150 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 151 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750) { 152 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5750); 153 return(0); 154 } 155 156 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 157 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5714) { 158 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5714); 159 return(0); 160 } 161 162 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 163 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5780) { 164 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5780); 165 return (0); 166 } 167 168 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 169 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5706C) { 170 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5706C); 171 return(0); 172 } 173 174 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 175 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5708C) { 176 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5708C); 177 return(0); 178 } 179 180 return(ENXIO); 181 } 182 183 static int 184 brgphy_attach(device_t dev) 185 { 186 struct mii_softc *sc; 187 struct mii_attach_args *ma; 188 struct mii_data *mii; 189 const char *sep = ""; 190 struct bge_softc *bge_sc = NULL; 191 struct bce_softc *bce_sc = NULL; 192 int fast_ether_only = FALSE; 193 194 sc = device_get_softc(dev); 195 ma = device_get_ivars(dev); 196 sc->mii_dev = device_get_parent(dev); 197 mii = device_get_softc(sc->mii_dev); 198 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 199 200 sc->mii_inst = mii->mii_instance; 201 sc->mii_phy = ma->mii_phyno; 202 sc->mii_service = brgphy_service; 203 sc->mii_pdata = mii; 204 205 sc->mii_flags |= MIIF_NOISOLATE; 206 mii->mii_instance++; 207 208 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 209 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 210 211 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 212 BMCR_ISO); 213 #if 0 214 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 215 BMCR_LOOP|BMCR_S100); 216 #endif 217 218 brgphy_mii_model = MII_MODEL(ma->mii_id2); 219 brgphy_reset(sc); 220 221 222 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 223 sc->mii_capabilities &= ~BMSR_ANEG; 224 device_printf(dev, " "); 225 mii_add_media(sc); 226 227 /* Find the driver associated with this PHY. */ 228 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) { 229 bge_sc = mii->mii_ifp->if_softc; 230 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) { 231 bce_sc = mii->mii_ifp->if_softc; 232 } 233 234 /* The 590x chips are 10/100 only. */ 235 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 236 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 237 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 238 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 239 fast_ether_only = TRUE; 240 241 if (fast_ether_only == FALSE) { 242 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 243 sc->mii_inst), BRGPHY_BMCR_FDX); 244 PRINT(", 1000baseTX"); 245 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 246 IFM_FDX, sc->mii_inst), 0); 247 PRINT("1000baseTX-FDX"); 248 } 249 250 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 251 PRINT("auto"); 252 253 printf("\n"); 254 #undef ADD 255 #undef PRINT 256 257 MIIBUS_MEDIAINIT(sc->mii_dev); 258 return(0); 259 } 260 261 static int 262 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 263 { 264 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 265 int reg, speed, gig; 266 267 switch (cmd) { 268 case MII_POLLSTAT: 269 /* 270 * If we're not polling our PHY instance, just return. 271 */ 272 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 273 return (0); 274 break; 275 276 case MII_MEDIACHG: 277 /* 278 * If the media indicates a different PHY instance, 279 * isolate ourselves. 280 */ 281 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 282 reg = PHY_READ(sc, MII_BMCR); 283 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 284 return (0); 285 } 286 287 /* 288 * If the interface is not up, don't do anything. 289 */ 290 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 291 break; 292 293 brgphy_reset(sc); /* XXX hardware bug work-around */ 294 295 switch (IFM_SUBTYPE(ife->ifm_media)) { 296 case IFM_AUTO: 297 #ifdef foo 298 /* 299 * If we're already in auto mode, just return. 300 */ 301 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 302 return (0); 303 #endif 304 (void) brgphy_mii_phy_auto(sc); 305 break; 306 case IFM_1000_T: 307 speed = BRGPHY_S1000; 308 goto setit; 309 case IFM_100_TX: 310 speed = BRGPHY_S100; 311 goto setit; 312 case IFM_10_T: 313 speed = BRGPHY_S10; 314 setit: 315 brgphy_loop(sc); 316 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 317 speed |= BRGPHY_BMCR_FDX; 318 gig = BRGPHY_1000CTL_AFD; 319 } else { 320 gig = BRGPHY_1000CTL_AHD; 321 } 322 323 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 324 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 325 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 326 327 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 328 break; 329 330 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 331 PHY_WRITE(sc, BRGPHY_MII_BMCR, 332 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 333 334 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 335 break; 336 337 /* 338 * When settning the link manually, one side must 339 * be the master and the other the slave. However 340 * ifmedia doesn't give us a good way to specify 341 * this, so we fake it by using one of the LINK 342 * flags. If LINK0 is set, we program the PHY to 343 * be a master, otherwise it's a slave. 344 */ 345 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 346 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 347 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 348 } else { 349 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 350 gig|BRGPHY_1000CTL_MSE); 351 } 352 break; 353 #ifdef foo 354 case IFM_NONE: 355 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 356 break; 357 #endif 358 case IFM_100_T4: 359 default: 360 return (EINVAL); 361 } 362 break; 363 364 case MII_TICK: 365 /* 366 * If we're not currently selected, just return. 367 */ 368 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 369 return (0); 370 371 /* 372 * Is the interface even up? 373 */ 374 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 375 return (0); 376 377 /* 378 * Only used for autonegotiation. 379 */ 380 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 381 break; 382 383 /* 384 * Check to see if we have link. If we do, we don't 385 * need to restart the autonegotiation process. Read 386 * the BMSR twice in case it's latched. 387 */ 388 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 389 if (reg & BRGPHY_AUXSTS_LINK) 390 break; 391 392 /* 393 * Only retry autonegotiation every 5 seconds. 394 */ 395 if (++sc->mii_ticks <= 5) 396 break; 397 398 sc->mii_ticks = 0; 399 brgphy_mii_phy_auto(sc); 400 break; 401 } 402 403 /* Update the media status. */ 404 brgphy_status(sc); 405 406 /* 407 * Callback if something changed. Note that we need to poke 408 * the DSP on the Broadcom PHYs if the media changes. 409 * 410 */ 411 if (sc->mii_media_active != mii->mii_media_active || 412 sc->mii_media_status != mii->mii_media_status || 413 cmd == MII_MEDIACHG) { 414 switch (brgphy_mii_model) { 415 case MII_MODEL_xxBROADCOM_BCM5400: 416 case MII_MODEL_xxBROADCOM_BCM5401: 417 bcm5401_load_dspcode(sc); 418 break; 419 case MII_MODEL_xxBROADCOM_BCM5411: 420 bcm5411_load_dspcode(sc); 421 break; 422 } 423 } 424 mii_phy_update(sc, cmd); 425 return (0); 426 } 427 428 static void 429 brgphy_status(struct mii_softc *sc) 430 { 431 struct mii_data *mii = sc->mii_pdata; 432 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 433 int bmsr, bmcr; 434 435 mii->mii_media_status = IFM_AVALID; 436 mii->mii_media_active = IFM_ETHER; 437 438 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 439 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 440 mii->mii_media_status |= IFM_ACTIVE; 441 442 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 443 444 if (bmcr & BRGPHY_BMCR_LOOP) 445 mii->mii_media_active |= IFM_LOOP; 446 447 if (bmcr & BRGPHY_BMCR_AUTOEN) { 448 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 449 /* Erg, still trying, I guess... */ 450 mii->mii_media_active |= IFM_NONE; 451 return; 452 } 453 454 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 455 BRGPHY_AUXSTS_AN_RES) { 456 case BRGPHY_RES_1000FD: 457 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 458 break; 459 case BRGPHY_RES_1000HD: 460 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 461 break; 462 case BRGPHY_RES_100FD: 463 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 464 break; 465 case BRGPHY_RES_100T4: 466 mii->mii_media_active |= IFM_100_T4; 467 break; 468 case BRGPHY_RES_100HD: 469 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 470 break; 471 case BRGPHY_RES_10FD: 472 mii->mii_media_active |= IFM_10_T | IFM_FDX; 473 break; 474 case BRGPHY_RES_10HD: 475 mii->mii_media_active |= IFM_10_T | IFM_HDX; 476 break; 477 default: 478 mii->mii_media_active |= IFM_NONE; 479 break; 480 } 481 return; 482 } 483 484 mii->mii_media_active = ife->ifm_media; 485 486 return; 487 } 488 489 490 static int 491 brgphy_mii_phy_auto(struct mii_softc *mii) 492 { 493 int ktcr = 0; 494 495 brgphy_loop(mii); 496 brgphy_reset(mii); 497 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 498 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 499 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 500 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 501 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 502 DELAY(1000); 503 PHY_WRITE(mii, BRGPHY_MII_ANAR, 504 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 505 DELAY(1000); 506 PHY_WRITE(mii, BRGPHY_MII_BMCR, 507 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 508 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 509 return (EJUSTRETURN); 510 } 511 512 static void 513 brgphy_loop(struct mii_softc *sc) 514 { 515 u_int32_t bmsr; 516 int i; 517 518 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 519 for (i = 0; i < 15000; i++) { 520 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 521 if (!(bmsr & BRGPHY_BMSR_LINK)) { 522 #if 0 523 device_printf(sc->mii_dev, "looped %d\n", i); 524 #endif 525 break; 526 } 527 DELAY(10); 528 } 529 } 530 531 /* Turn off tap power management on 5401. */ 532 static void 533 bcm5401_load_dspcode(struct mii_softc *sc) 534 { 535 static const struct { 536 int reg; 537 uint16_t val; 538 } dspcode[] = { 539 { BRGPHY_MII_AUXCTL, 0x0c20 }, 540 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 541 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 542 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 543 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 544 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 545 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 546 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 547 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 548 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 549 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 550 { 0, 0 }, 551 }; 552 int i; 553 554 for (i = 0; dspcode[i].reg != 0; i++) 555 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 556 DELAY(40); 557 } 558 559 static void 560 bcm5411_load_dspcode(struct mii_softc *sc) 561 { 562 static const struct { 563 int reg; 564 uint16_t val; 565 } dspcode[] = { 566 { 0x1c, 0x8c23 }, 567 { 0x1c, 0x8ca3 }, 568 { 0x1c, 0x8c23 }, 569 { 0, 0 }, 570 }; 571 int i; 572 573 for (i = 0; dspcode[i].reg != 0; i++) 574 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 575 } 576 577 static void 578 bcm5703_load_dspcode(struct mii_softc *sc) 579 { 580 static const struct { 581 int reg; 582 uint16_t val; 583 } dspcode[] = { 584 { BRGPHY_MII_AUXCTL, 0x0c00 }, 585 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 586 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 587 { 0, 0 }, 588 }; 589 int i; 590 591 for (i = 0; dspcode[i].reg != 0; i++) 592 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 593 } 594 595 static void 596 bcm5704_load_dspcode(struct mii_softc *sc) 597 { 598 static const struct { 599 int reg; 600 u_int16_t val; 601 } dspcode[] = { 602 { 0x1c, 0x8d68 }, 603 { 0x1c, 0x8d68 }, 604 { 0, 0 }, 605 }; 606 int i; 607 608 for (i = 0; dspcode[i].reg != 0; i++) 609 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 610 } 611 612 static void 613 bcm5750_load_dspcode(struct mii_softc *sc) 614 { 615 static const struct { 616 int reg; 617 u_int16_t val; 618 } dspcode[] = { 619 { 0x18, 0x0c00 }, 620 { 0x17, 0x000a }, 621 { 0x15, 0x310b }, 622 { 0x17, 0x201f }, 623 { 0x15, 0x9506 }, 624 { 0x17, 0x401f }, 625 { 0x15, 0x14e2 }, 626 { 0x18, 0x0400 }, 627 { 0, 0 }, 628 }; 629 int i; 630 631 for (i = 0; dspcode[i].reg != 0; i++) 632 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 633 } 634 635 static void 636 brgphy_reset(struct mii_softc *sc) 637 { 638 u_int32_t val; 639 struct ifnet *ifp; 640 struct bge_softc *bge_sc = NULL; 641 struct bce_softc *bce_sc = NULL; 642 643 mii_phy_reset(sc); 644 645 switch (brgphy_mii_model) { 646 case MII_MODEL_xxBROADCOM_BCM5400: 647 case MII_MODEL_xxBROADCOM_BCM5401: 648 bcm5401_load_dspcode(sc); 649 break; 650 case MII_MODEL_xxBROADCOM_BCM5411: 651 bcm5411_load_dspcode(sc); 652 break; 653 case MII_MODEL_xxBROADCOM_BCM5703: 654 bcm5703_load_dspcode(sc); 655 break; 656 case MII_MODEL_xxBROADCOM_BCM5704: 657 bcm5704_load_dspcode(sc); 658 break; 659 case MII_MODEL_xxBROADCOM_BCM5750: 660 case MII_MODEL_xxBROADCOM_BCM5714: 661 case MII_MODEL_xxBROADCOM_BCM5780: 662 case MII_MODEL_xxBROADCOM_BCM5706C: 663 case MII_MODEL_xxBROADCOM_BCM5708C: 664 bcm5750_load_dspcode(sc); 665 break; 666 } 667 668 ifp = sc->mii_pdata->mii_ifp; 669 670 /* Find the driver associated with this PHY. */ 671 if (strcmp(ifp->if_dname, "bge") == 0) { 672 bge_sc = ifp->if_softc; 673 } else if (strcmp(ifp->if_dname, "bce") == 0) { 674 bce_sc = ifp->if_softc; 675 } 676 677 /* Handle any NetXtreme/bge workarounds. */ 678 if (bge_sc) { 679 /* 680 * Don't enable Ethernet@WireSpeed for the 5700 or the 681 * 5705 A1 and A2 chips. Make sure we only do this test 682 * on "bge" NICs, since other drivers may use this same 683 * PHY subdriver. 684 */ 685 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 686 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 687 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2) 688 return; 689 690 /* Enable Ethernet@WireSpeed. */ 691 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 692 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 693 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 694 695 /* Enable Link LED on Dell boxes */ 696 if (bge_sc->bge_no_3_led) { 697 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 698 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 699 & ~BRGPHY_PHY_EXTCTL_3_LED); 700 } 701 } else if (bce_sc) { 702 703 /* Set or clear jumbo frame settings in the PHY. */ 704 if (ifp->if_mtu > ETHER_MAX_LEN) { 705 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 706 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 707 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 708 val | BRGPHY_AUXCTL_LONG_PKT); 709 710 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 711 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 712 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 713 } else { 714 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 715 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 716 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 717 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 718 719 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 720 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 721 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 722 } 723 724 /* Enable Ethernet@Wirespeed */ 725 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 726 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 727 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4))); 728 } 729 } 730