1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 48 #include <machine/clock.h> 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/brgphyreg.h> 58 #include <net/if_arp.h> 59 #include <machine/bus.h> 60 #include <dev/bge/if_bgereg.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 65 #include "miibus_if.h" 66 67 static int brgphy_probe(device_t); 68 static int brgphy_attach(device_t); 69 70 static device_method_t brgphy_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, brgphy_probe), 73 DEVMETHOD(device_attach, brgphy_attach), 74 DEVMETHOD(device_detach, mii_phy_detach), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 { 0, 0 } 77 }; 78 79 static devclass_t brgphy_devclass; 80 81 static driver_t brgphy_driver = { 82 "brgphy", 83 brgphy_methods, 84 sizeof(struct mii_softc) 85 }; 86 87 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 88 89 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 90 static void brgphy_status(struct mii_softc *); 91 static int brgphy_mii_phy_auto(struct mii_softc *); 92 static void brgphy_reset(struct mii_softc *); 93 static void brgphy_loop(struct mii_softc *); 94 static void bcm5401_load_dspcode(struct mii_softc *); 95 static void bcm5411_load_dspcode(struct mii_softc *); 96 static void bcm5703_load_dspcode(struct mii_softc *); 97 static void bcm5750_load_dspcode(struct mii_softc *); 98 static int brgphy_mii_model; 99 100 static int 101 brgphy_probe(device_t dev) 102 { 103 struct mii_attach_args *ma; 104 105 ma = device_get_ivars(dev); 106 107 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 108 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 109 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 110 return(0); 111 } 112 113 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 114 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 115 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 116 return(0); 117 } 118 119 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 120 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 121 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 122 return(0); 123 } 124 125 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 126 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 127 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 128 return(0); 129 } 130 131 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 132 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 133 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 134 return(0); 135 } 136 137 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 138 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 139 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 140 return(0); 141 } 142 143 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 144 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 145 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 146 return(0); 147 } 148 149 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 150 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750) { 151 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5750); 152 return(0); 153 } 154 155 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 156 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5714) { 157 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5714); 158 return(0); 159 } 160 161 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 162 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5780) { 163 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5780); 164 return(0); 165 } 166 167 return(ENXIO); 168 } 169 170 static int 171 brgphy_attach(device_t dev) 172 { 173 struct mii_softc *sc; 174 struct mii_attach_args *ma; 175 struct mii_data *mii; 176 const char *sep = ""; 177 struct bge_softc *bge_sc; 178 int fast_ether_only = FALSE; 179 180 sc = device_get_softc(dev); 181 ma = device_get_ivars(dev); 182 sc->mii_dev = device_get_parent(dev); 183 mii = device_get_softc(sc->mii_dev); 184 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 185 186 sc->mii_inst = mii->mii_instance; 187 sc->mii_phy = ma->mii_phyno; 188 sc->mii_service = brgphy_service; 189 sc->mii_pdata = mii; 190 191 sc->mii_flags |= MIIF_NOISOLATE; 192 mii->mii_instance++; 193 194 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 195 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 196 197 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 198 BMCR_ISO); 199 #if 0 200 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 201 BMCR_LOOP|BMCR_S100); 202 #endif 203 204 brgphy_mii_model = MII_MODEL(ma->mii_id2); 205 brgphy_reset(sc); 206 207 208 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 209 sc->mii_capabilities &= ~BMSR_ANEG; 210 device_printf(dev, " "); 211 mii_add_media(sc); 212 213 /* The 590x chips are 10/100 only. */ 214 215 bge_sc = mii->mii_ifp->if_softc; 216 217 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 218 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 219 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 220 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 221 fast_ether_only = TRUE; 222 223 if (fast_ether_only == FALSE) { 224 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 225 sc->mii_inst), BRGPHY_BMCR_FDX); 226 PRINT(", 1000baseTX"); 227 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 228 IFM_FDX, sc->mii_inst), 0); 229 PRINT("1000baseTX-FDX"); 230 } 231 232 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 233 PRINT("auto"); 234 235 printf("\n"); 236 #undef ADD 237 #undef PRINT 238 239 MIIBUS_MEDIAINIT(sc->mii_dev); 240 return(0); 241 } 242 243 static int 244 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 245 { 246 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 247 int reg, speed, gig; 248 249 switch (cmd) { 250 case MII_POLLSTAT: 251 /* 252 * If we're not polling our PHY instance, just return. 253 */ 254 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 255 return (0); 256 break; 257 258 case MII_MEDIACHG: 259 /* 260 * If the media indicates a different PHY instance, 261 * isolate ourselves. 262 */ 263 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 264 reg = PHY_READ(sc, MII_BMCR); 265 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 266 return (0); 267 } 268 269 /* 270 * If the interface is not up, don't do anything. 271 */ 272 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 273 break; 274 275 brgphy_reset(sc); /* XXX hardware bug work-around */ 276 277 switch (IFM_SUBTYPE(ife->ifm_media)) { 278 case IFM_AUTO: 279 #ifdef foo 280 /* 281 * If we're already in auto mode, just return. 282 */ 283 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 284 return (0); 285 #endif 286 (void) brgphy_mii_phy_auto(sc); 287 break; 288 case IFM_1000_T: 289 speed = BRGPHY_S1000; 290 goto setit; 291 case IFM_100_TX: 292 speed = BRGPHY_S100; 293 goto setit; 294 case IFM_10_T: 295 speed = BRGPHY_S10; 296 setit: 297 brgphy_loop(sc); 298 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 299 speed |= BRGPHY_BMCR_FDX; 300 gig = BRGPHY_1000CTL_AFD; 301 } else { 302 gig = BRGPHY_1000CTL_AHD; 303 } 304 305 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 306 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 307 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 308 309 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 310 break; 311 312 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 313 PHY_WRITE(sc, BRGPHY_MII_BMCR, 314 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 315 316 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 317 break; 318 319 /* 320 * When settning the link manually, one side must 321 * be the master and the other the slave. However 322 * ifmedia doesn't give us a good way to specify 323 * this, so we fake it by using one of the LINK 324 * flags. If LINK0 is set, we program the PHY to 325 * be a master, otherwise it's a slave. 326 */ 327 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 328 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 329 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 330 } else { 331 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 332 gig|BRGPHY_1000CTL_MSE); 333 } 334 break; 335 #ifdef foo 336 case IFM_NONE: 337 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 338 break; 339 #endif 340 case IFM_100_T4: 341 default: 342 return (EINVAL); 343 } 344 break; 345 346 case MII_TICK: 347 /* 348 * If we're not currently selected, just return. 349 */ 350 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 351 return (0); 352 353 /* 354 * Is the interface even up? 355 */ 356 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 357 return (0); 358 359 /* 360 * Only used for autonegotiation. 361 */ 362 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 363 break; 364 365 /* 366 * Check to see if we have link. If we do, we don't 367 * need to restart the autonegotiation process. Read 368 * the BMSR twice in case it's latched. 369 */ 370 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 371 if (reg & BRGPHY_AUXSTS_LINK) 372 break; 373 374 /* 375 * Only retry autonegotiation every 5 seconds. 376 */ 377 if (++sc->mii_ticks <= 5) 378 break; 379 380 sc->mii_ticks = 0; 381 brgphy_mii_phy_auto(sc); 382 break; 383 } 384 385 /* Update the media status. */ 386 brgphy_status(sc); 387 388 /* 389 * Callback if something changed. Note that we need to poke 390 * the DSP on the Broadcom PHYs if the media changes. 391 * 392 */ 393 if (sc->mii_media_active != mii->mii_media_active || 394 sc->mii_media_status != mii->mii_media_status || 395 cmd == MII_MEDIACHG) { 396 switch (brgphy_mii_model) { 397 case MII_MODEL_xxBROADCOM_BCM5400: 398 case MII_MODEL_xxBROADCOM_BCM5401: 399 bcm5401_load_dspcode(sc); 400 break; 401 case MII_MODEL_xxBROADCOM_BCM5411: 402 bcm5411_load_dspcode(sc); 403 break; 404 } 405 } 406 mii_phy_update(sc, cmd); 407 return (0); 408 } 409 410 static void 411 brgphy_status(struct mii_softc *sc) 412 { 413 struct mii_data *mii = sc->mii_pdata; 414 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 415 int bmsr, bmcr; 416 417 mii->mii_media_status = IFM_AVALID; 418 mii->mii_media_active = IFM_ETHER; 419 420 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 421 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 422 mii->mii_media_status |= IFM_ACTIVE; 423 424 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 425 426 if (bmcr & BRGPHY_BMCR_LOOP) 427 mii->mii_media_active |= IFM_LOOP; 428 429 if (bmcr & BRGPHY_BMCR_AUTOEN) { 430 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 431 /* Erg, still trying, I guess... */ 432 mii->mii_media_active |= IFM_NONE; 433 return; 434 } 435 436 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 437 BRGPHY_AUXSTS_AN_RES) { 438 case BRGPHY_RES_1000FD: 439 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 440 break; 441 case BRGPHY_RES_1000HD: 442 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 443 break; 444 case BRGPHY_RES_100FD: 445 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 446 break; 447 case BRGPHY_RES_100T4: 448 mii->mii_media_active |= IFM_100_T4; 449 break; 450 case BRGPHY_RES_100HD: 451 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 452 break; 453 case BRGPHY_RES_10FD: 454 mii->mii_media_active |= IFM_10_T | IFM_FDX; 455 break; 456 case BRGPHY_RES_10HD: 457 mii->mii_media_active |= IFM_10_T | IFM_HDX; 458 break; 459 default: 460 mii->mii_media_active |= IFM_NONE; 461 break; 462 } 463 return; 464 } 465 466 mii->mii_media_active = ife->ifm_media; 467 468 return; 469 } 470 471 472 static int 473 brgphy_mii_phy_auto(struct mii_softc *mii) 474 { 475 int ktcr = 0; 476 477 brgphy_loop(mii); 478 brgphy_reset(mii); 479 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 480 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 481 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 482 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 483 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 484 DELAY(1000); 485 PHY_WRITE(mii, BRGPHY_MII_ANAR, 486 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 487 DELAY(1000); 488 PHY_WRITE(mii, BRGPHY_MII_BMCR, 489 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 490 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 491 return (EJUSTRETURN); 492 } 493 494 static void 495 brgphy_loop(struct mii_softc *sc) 496 { 497 u_int32_t bmsr; 498 int i; 499 500 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 501 for (i = 0; i < 15000; i++) { 502 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 503 if (!(bmsr & BRGPHY_BMSR_LINK)) { 504 #if 0 505 device_printf(sc->mii_dev, "looped %d\n", i); 506 #endif 507 break; 508 } 509 DELAY(10); 510 } 511 } 512 513 /* Turn off tap power management on 5401. */ 514 static void 515 bcm5401_load_dspcode(struct mii_softc *sc) 516 { 517 static const struct { 518 int reg; 519 uint16_t val; 520 } dspcode[] = { 521 { BRGPHY_MII_AUXCTL, 0x0c20 }, 522 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 523 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 524 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 525 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 526 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 527 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 528 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 529 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 530 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 531 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 532 { 0, 0 }, 533 }; 534 int i; 535 536 for (i = 0; dspcode[i].reg != 0; i++) 537 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 538 DELAY(40); 539 } 540 541 static void 542 bcm5411_load_dspcode(struct mii_softc *sc) 543 { 544 static const struct { 545 int reg; 546 uint16_t val; 547 } dspcode[] = { 548 { 0x1c, 0x8c23 }, 549 { 0x1c, 0x8ca3 }, 550 { 0x1c, 0x8c23 }, 551 { 0, 0 }, 552 }; 553 int i; 554 555 for (i = 0; dspcode[i].reg != 0; i++) 556 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 557 } 558 559 static void 560 bcm5703_load_dspcode(struct mii_softc *sc) 561 { 562 static const struct { 563 int reg; 564 uint16_t val; 565 } dspcode[] = { 566 { BRGPHY_MII_AUXCTL, 0x0c00 }, 567 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 568 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 569 { 0, 0 }, 570 }; 571 int i; 572 573 for (i = 0; dspcode[i].reg != 0; i++) 574 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 575 } 576 577 static void 578 bcm5704_load_dspcode(struct mii_softc *sc) 579 { 580 static const struct { 581 int reg; 582 u_int16_t val; 583 } dspcode[] = { 584 { 0x1c, 0x8d68 }, 585 { 0x1c, 0x8d68 }, 586 { 0, 0 }, 587 }; 588 int i; 589 590 for (i = 0; dspcode[i].reg != 0; i++) 591 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 592 } 593 594 static void 595 bcm5750_load_dspcode(struct mii_softc *sc) 596 { 597 static const struct { 598 int reg; 599 u_int16_t val; 600 } dspcode[] = { 601 { 0x18, 0x0c00 }, 602 { 0x17, 0x000a }, 603 { 0x15, 0x310b }, 604 { 0x17, 0x201f }, 605 { 0x15, 0x9506 }, 606 { 0x17, 0x401f }, 607 { 0x15, 0x14e2 }, 608 { 0x18, 0x0400 }, 609 { 0, 0 }, 610 }; 611 int i; 612 613 for (i = 0; dspcode[i].reg != 0; i++) 614 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 615 } 616 617 static void 618 brgphy_reset(struct mii_softc *sc) 619 { 620 u_int32_t val; 621 struct ifnet *ifp; 622 struct bge_softc *bge_sc; 623 624 mii_phy_reset(sc); 625 626 switch (brgphy_mii_model) { 627 case MII_MODEL_xxBROADCOM_BCM5400: 628 case MII_MODEL_xxBROADCOM_BCM5401: 629 bcm5401_load_dspcode(sc); 630 break; 631 case MII_MODEL_xxBROADCOM_BCM5411: 632 bcm5411_load_dspcode(sc); 633 break; 634 case MII_MODEL_xxBROADCOM_BCM5703: 635 bcm5703_load_dspcode(sc); 636 break; 637 case MII_MODEL_xxBROADCOM_BCM5704: 638 bcm5704_load_dspcode(sc); 639 break; 640 case MII_MODEL_xxBROADCOM_BCM5750: 641 case MII_MODEL_xxBROADCOM_BCM5714: 642 case MII_MODEL_xxBROADCOM_BCM5780: 643 bcm5750_load_dspcode(sc); 644 break; 645 } 646 647 ifp = sc->mii_pdata->mii_ifp; 648 bge_sc = ifp->if_softc; 649 650 /* 651 * Don't enable Ethernet@WireSpeed for the 5700 or the 652 * 5705 A1 and A2 chips. Make sure we only do this test 653 * on "bge" NICs, since other drivers may use this same 654 * PHY subdriver. 655 */ 656 if (strcmp(ifp->if_dname, "bge") == 0 && 657 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 658 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 659 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)) 660 return; 661 662 /* Enable Ethernet@WireSpeed. */ 663 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 664 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 665 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 666 667 /* Enable Link LED on Dell boxes */ 668 if (bge_sc->bge_no_3_led) { 669 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 670 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 671 & ~BRGPHY_PHY_EXTCTL_3_LED); 672 } 673 } 674