1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/ethernet.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/brgphyreg.h> 58 #include <net/if_arp.h> 59 #include <machine/bus.h> 60 #include <dev/bge/if_bgereg.h> 61 #include <dev/bce/if_bcereg.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 66 #include "miibus_if.h" 67 68 static int brgphy_probe(device_t); 69 static int brgphy_attach(device_t); 70 71 struct brgphy_softc { 72 struct mii_softc mii_sc; 73 int serdes_flags; /* Keeps track of the serdes type used */ 74 #define BRGPHY_5706S 0x0001 75 #define BRGPHY_5708S 0x0002 76 #define BRGPHY_NOANWAIT 0x0004 77 #define BRGPHY_5709S 0x0008 78 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 79 }; 80 81 static device_method_t brgphy_methods[] = { 82 /* device interface */ 83 DEVMETHOD(device_probe, brgphy_probe), 84 DEVMETHOD(device_attach, brgphy_attach), 85 DEVMETHOD(device_detach, mii_phy_detach), 86 DEVMETHOD(device_shutdown, bus_generic_shutdown), 87 DEVMETHOD_END 88 }; 89 90 static devclass_t brgphy_devclass; 91 92 static driver_t brgphy_driver = { 93 "brgphy", 94 brgphy_methods, 95 sizeof(struct brgphy_softc) 96 }; 97 98 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 99 100 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 101 static void brgphy_setmedia(struct mii_softc *, int); 102 static void brgphy_status(struct mii_softc *); 103 static void brgphy_mii_phy_auto(struct mii_softc *, int); 104 static void brgphy_reset(struct mii_softc *); 105 static void brgphy_enable_loopback(struct mii_softc *); 106 static void bcm5401_load_dspcode(struct mii_softc *); 107 static void bcm5411_load_dspcode(struct mii_softc *); 108 static void bcm54k2_load_dspcode(struct mii_softc *); 109 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 110 static void brgphy_fixup_adc_bug(struct mii_softc *); 111 static void brgphy_fixup_adjust_trim(struct mii_softc *); 112 static void brgphy_fixup_ber_bug(struct mii_softc *); 113 static void brgphy_fixup_crc_bug(struct mii_softc *); 114 static void brgphy_fixup_jitter_bug(struct mii_softc *); 115 static void brgphy_ethernet_wirespeed(struct mii_softc *); 116 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 117 118 static const struct mii_phydesc brgphys[] = { 119 MII_PHY_DESC(BROADCOM, BCM5400), 120 MII_PHY_DESC(BROADCOM, BCM5401), 121 MII_PHY_DESC(BROADCOM, BCM5411), 122 MII_PHY_DESC(BROADCOM, BCM54K2), 123 MII_PHY_DESC(BROADCOM, BCM5701), 124 MII_PHY_DESC(BROADCOM, BCM5703), 125 MII_PHY_DESC(BROADCOM, BCM5704), 126 MII_PHY_DESC(BROADCOM, BCM5705), 127 MII_PHY_DESC(BROADCOM, BCM5706), 128 MII_PHY_DESC(BROADCOM, BCM5714), 129 MII_PHY_DESC(BROADCOM, BCM5421), 130 MII_PHY_DESC(BROADCOM, BCM5750), 131 MII_PHY_DESC(BROADCOM, BCM5752), 132 MII_PHY_DESC(BROADCOM, BCM5780), 133 MII_PHY_DESC(BROADCOM, BCM5708C), 134 MII_PHY_DESC(BROADCOM, BCM5466), 135 MII_PHY_DESC(BROADCOM2, BCM5482), 136 MII_PHY_DESC(BROADCOM2, BCM5708S), 137 MII_PHY_DESC(BROADCOM2, BCM5709C), 138 MII_PHY_DESC(BROADCOM2, BCM5709S), 139 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 140 MII_PHY_DESC(BROADCOM2, BCM5722), 141 MII_PHY_DESC(BROADCOM2, BCM5755), 142 MII_PHY_DESC(BROADCOM2, BCM5754), 143 MII_PHY_DESC(BROADCOM2, BCM5761), 144 MII_PHY_DESC(BROADCOM2, BCM5784), 145 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 146 MII_PHY_DESC(BROADCOM2, BCM5785), 147 #endif 148 MII_PHY_DESC(BROADCOM3, BCM5717C), 149 MII_PHY_DESC(BROADCOM3, BCM5719C), 150 MII_PHY_DESC(BROADCOM3, BCM5720C), 151 MII_PHY_DESC(BROADCOM3, BCM57765), 152 MII_PHY_DESC(BROADCOM3, BCM57780), 153 MII_PHY_DESC(BROADCOM4, BCM5725C), 154 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 155 MII_PHY_END 156 }; 157 158 static const struct mii_phy_funcs brgphy_funcs = { 159 brgphy_service, 160 brgphy_status, 161 brgphy_reset 162 }; 163 164 static const struct hs21_type { 165 const uint32_t id; 166 const char *prod; 167 } hs21_type_lists[] = { 168 { 0x57081021, "IBM eServer BladeCenter HS21" }, 169 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" }, 170 }; 171 172 static int 173 detect_hs21(struct bce_softc *bce_sc) 174 { 175 char *sysenv; 176 int found, i; 177 178 found = 0; 179 sysenv = kern_getenv("smbios.system.product"); 180 if (sysenv == NULL) 181 return (found); 182 for (i = 0; i < nitems(hs21_type_lists); i++) { 183 if (bce_sc->bce_chipid == hs21_type_lists[i].id && 184 strncmp(sysenv, hs21_type_lists[i].prod, 185 strlen(hs21_type_lists[i].prod)) == 0) { 186 found++; 187 break; 188 } 189 } 190 freeenv(sysenv); 191 return (found); 192 } 193 194 /* Search for our PHY in the list of known PHYs */ 195 static int 196 brgphy_probe(device_t dev) 197 { 198 199 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 200 } 201 202 /* Attach the PHY to the MII bus */ 203 static int 204 brgphy_attach(device_t dev) 205 { 206 struct brgphy_softc *bsc; 207 struct bge_softc *bge_sc = NULL; 208 struct bce_softc *bce_sc = NULL; 209 struct mii_softc *sc; 210 211 bsc = device_get_softc(dev); 212 sc = &bsc->mii_sc; 213 214 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 215 &brgphy_funcs, 0); 216 217 bsc->serdes_flags = 0; 218 219 /* Find the MAC driver associated with this PHY. */ 220 if (mii_dev_mac_match(dev, "bge")) 221 bge_sc = mii_dev_mac_softc(dev); 222 else if (mii_dev_mac_match(dev, "bce")) 223 bce_sc = mii_dev_mac_softc(dev); 224 225 /* Handle any special cases based on the PHY ID */ 226 switch (sc->mii_mpd_oui) { 227 case MII_OUI_BROADCOM: 228 switch (sc->mii_mpd_model) { 229 case MII_MODEL_BROADCOM_BCM5706: 230 case MII_MODEL_BROADCOM_BCM5714: 231 /* 232 * The 5464 PHY used in the 5706 supports both copper 233 * and fiber interfaces over GMII. Need to check the 234 * shadow registers to see which mode is actually 235 * in effect, and therefore whether we have 5706C or 236 * 5706S. 237 */ 238 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 239 BRGPHY_SHADOW_1C_MODE_CTRL); 240 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 241 BRGPHY_SHADOW_1C_ENA_1000X) { 242 bsc->serdes_flags |= BRGPHY_5706S; 243 sc->mii_flags |= MIIF_HAVEFIBER; 244 } 245 break; 246 } 247 break; 248 case MII_OUI_BROADCOM2: 249 switch (sc->mii_mpd_model) { 250 case MII_MODEL_BROADCOM2_BCM5708S: 251 bsc->serdes_flags |= BRGPHY_5708S; 252 sc->mii_flags |= MIIF_HAVEFIBER; 253 break; 254 case MII_MODEL_BROADCOM2_BCM5709S: 255 /* 256 * XXX 257 * 5720S and 5709S shares the same PHY id. 258 * Assume 5720S PHY if parent device is bge(4). 259 */ 260 if (bge_sc != NULL) 261 bsc->serdes_flags |= BRGPHY_5708S; 262 else 263 bsc->serdes_flags |= BRGPHY_5709S; 264 sc->mii_flags |= MIIF_HAVEFIBER; 265 break; 266 } 267 break; 268 } 269 270 PHY_RESET(sc); 271 272 /* Read the PHY's capabilities. */ 273 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 274 if (sc->mii_capabilities & BMSR_EXTSTAT) 275 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 276 device_printf(dev, " "); 277 278 /* Add the supported media types */ 279 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 280 mii_phy_add_media(sc); 281 printf("\n"); 282 } else { 283 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 284 ifmedia_add(&sc->mii_pdata->mii_media, 285 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 286 0, NULL); 287 printf("1000baseSX-FDX, "); 288 /* 289 * 2.5G support is a software enabled feature 290 * on the 5708S and 5709S. 291 */ 292 if (bce_sc && (bce_sc->bce_phy_flags & 293 BCE_PHY_2_5G_CAPABLE_FLAG)) { 294 ifmedia_add(&sc->mii_pdata->mii_media, 295 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, 296 sc->mii_inst), 0, NULL); 297 printf("2500baseSX-FDX, "); 298 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 299 (detect_hs21(bce_sc) != 0)) { 300 /* 301 * There appears to be certain silicon revision 302 * in IBM HS21 blades that is having issues with 303 * this driver wating for the auto-negotiation to 304 * complete. This happens with a specific chip id 305 * only and when the 1000baseSX-FDX is the only 306 * mode. Workaround this issue since it's unlikely 307 * to be ever addressed. 308 */ 309 printf("auto-neg workaround, "); 310 bsc->serdes_flags |= BRGPHY_NOANWAIT; 311 } 312 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER, 313 IFM_AUTO, 0, sc->mii_inst), 0, NULL); 314 printf("auto\n"); 315 } 316 317 MIIBUS_MEDIAINIT(sc->mii_dev); 318 return (0); 319 } 320 321 static int 322 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 323 { 324 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 325 int val; 326 327 switch (cmd) { 328 case MII_POLLSTAT: 329 break; 330 case MII_MEDIACHG: 331 /* Todo: Why is this here? Is it really needed? */ 332 PHY_RESET(sc); /* XXX hardware bug work-around */ 333 334 switch (IFM_SUBTYPE(ife->ifm_media)) { 335 case IFM_AUTO: 336 brgphy_mii_phy_auto(sc, ife->ifm_media); 337 break; 338 case IFM_2500_SX: 339 case IFM_1000_SX: 340 case IFM_1000_T: 341 case IFM_100_TX: 342 case IFM_10_T: 343 brgphy_setmedia(sc, ife->ifm_media); 344 break; 345 default: 346 return (EINVAL); 347 } 348 break; 349 case MII_TICK: 350 /* Bail if autoneg isn't in process. */ 351 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 352 sc->mii_ticks = 0; 353 break; 354 } 355 356 /* 357 * Check to see if we have link. If we do, we don't 358 * need to restart the autonegotiation process. 359 */ 360 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 361 if (val & BMSR_LINK) { 362 sc->mii_ticks = 0; /* Reset autoneg timer. */ 363 break; 364 } 365 366 /* Announce link loss right after it happens. */ 367 if (sc->mii_ticks++ == 0) 368 break; 369 370 /* Only retry autonegotiation every mii_anegticks seconds. */ 371 if (sc->mii_ticks <= sc->mii_anegticks) 372 break; 373 374 375 /* Retry autonegotiation */ 376 sc->mii_ticks = 0; 377 brgphy_mii_phy_auto(sc, ife->ifm_media); 378 break; 379 } 380 381 /* Update the media status. */ 382 PHY_STATUS(sc); 383 384 /* 385 * Callback if something changed. Note that we need to poke 386 * the DSP on the Broadcom PHYs if the media changes. 387 */ 388 if (sc->mii_media_active != mii->mii_media_active || 389 sc->mii_media_status != mii->mii_media_status || 390 cmd == MII_MEDIACHG) { 391 switch (sc->mii_mpd_oui) { 392 case MII_OUI_BROADCOM: 393 switch (sc->mii_mpd_model) { 394 case MII_MODEL_BROADCOM_BCM5400: 395 bcm5401_load_dspcode(sc); 396 break; 397 case MII_MODEL_BROADCOM_BCM5401: 398 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 399 bcm5401_load_dspcode(sc); 400 break; 401 case MII_MODEL_BROADCOM_BCM5411: 402 bcm5411_load_dspcode(sc); 403 break; 404 case MII_MODEL_BROADCOM_BCM54K2: 405 bcm54k2_load_dspcode(sc); 406 break; 407 } 408 break; 409 } 410 } 411 mii_phy_update(sc, cmd); 412 return (0); 413 } 414 415 /****************************************************************************/ 416 /* Sets the PHY link speed. */ 417 /* */ 418 /* Returns: */ 419 /* None */ 420 /****************************************************************************/ 421 static void 422 brgphy_setmedia(struct mii_softc *sc, int media) 423 { 424 int bmcr = 0, gig; 425 426 switch (IFM_SUBTYPE(media)) { 427 case IFM_2500_SX: 428 break; 429 case IFM_1000_SX: 430 case IFM_1000_T: 431 bmcr = BRGPHY_S1000; 432 break; 433 case IFM_100_TX: 434 bmcr = BRGPHY_S100; 435 break; 436 case IFM_10_T: 437 default: 438 bmcr = BRGPHY_S10; 439 break; 440 } 441 442 if ((media & IFM_FDX) != 0) { 443 bmcr |= BRGPHY_BMCR_FDX; 444 gig = BRGPHY_1000CTL_AFD; 445 } else { 446 gig = BRGPHY_1000CTL_AHD; 447 } 448 449 /* Force loopback to disconnect PHY from Ethernet medium. */ 450 brgphy_enable_loopback(sc); 451 452 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 453 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 454 455 if (IFM_SUBTYPE(media) != IFM_1000_T && 456 IFM_SUBTYPE(media) != IFM_1000_SX) { 457 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 458 return; 459 } 460 461 if (IFM_SUBTYPE(media) == IFM_1000_T) { 462 gig |= BRGPHY_1000CTL_MSE; 463 if ((media & IFM_ETH_MASTER) != 0) 464 gig |= BRGPHY_1000CTL_MSC; 465 } 466 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 467 PHY_WRITE(sc, BRGPHY_MII_BMCR, 468 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 469 } 470 471 /****************************************************************************/ 472 /* Set the media status based on the PHY settings. */ 473 /* */ 474 /* Returns: */ 475 /* None */ 476 /****************************************************************************/ 477 static void 478 brgphy_status(struct mii_softc *sc) 479 { 480 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 481 struct mii_data *mii = sc->mii_pdata; 482 int aux, bmcr, bmsr, val, xstat; 483 u_int flowstat; 484 485 mii->mii_media_status = IFM_AVALID; 486 mii->mii_media_active = IFM_ETHER; 487 488 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 489 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 490 491 if (bmcr & BRGPHY_BMCR_LOOP) { 492 mii->mii_media_active |= IFM_LOOP; 493 } 494 495 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 496 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 497 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 498 /* Erg, still trying, I guess... */ 499 mii->mii_media_active |= IFM_NONE; 500 return; 501 } 502 503 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 504 /* 505 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 506 * wedges at least the PHY of BCM5704 (but not others). 507 */ 508 flowstat = mii_phy_flowstatus(sc); 509 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 510 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 511 512 /* If copper link is up, get the negotiated speed/duplex. */ 513 if (aux & BRGPHY_AUXSTS_LINK) { 514 mii->mii_media_status |= IFM_ACTIVE; 515 switch (aux & BRGPHY_AUXSTS_AN_RES) { 516 case BRGPHY_RES_1000FD: 517 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 518 case BRGPHY_RES_1000HD: 519 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 520 case BRGPHY_RES_100FD: 521 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 522 case BRGPHY_RES_100T4: 523 mii->mii_media_active |= IFM_100_T4; break; 524 case BRGPHY_RES_100HD: 525 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 526 case BRGPHY_RES_10FD: 527 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 528 case BRGPHY_RES_10HD: 529 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 530 default: 531 mii->mii_media_active |= IFM_NONE; break; 532 } 533 534 if ((mii->mii_media_active & IFM_FDX) != 0) 535 mii->mii_media_active |= flowstat; 536 537 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 538 (xstat & BRGPHY_1000STS_MSR) != 0) 539 mii->mii_media_active |= IFM_ETH_MASTER; 540 } 541 } else { 542 /* Todo: Add support for flow control. */ 543 /* If serdes link is up, get the negotiated speed/duplex. */ 544 if (bmsr & BRGPHY_BMSR_LINK) { 545 mii->mii_media_status |= IFM_ACTIVE; 546 } 547 548 /* Check the link speed/duplex based on the PHY type. */ 549 if (bsc->serdes_flags & BRGPHY_5706S) { 550 mii->mii_media_active |= IFM_1000_SX; 551 552 /* If autoneg enabled, read negotiated duplex settings */ 553 if (bmcr & BRGPHY_BMCR_AUTOEN) { 554 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 555 if (val & BRGPHY_SERDES_ANAR_FDX) 556 mii->mii_media_active |= IFM_FDX; 557 else 558 mii->mii_media_active |= IFM_HDX; 559 } 560 } else if (bsc->serdes_flags & BRGPHY_5708S) { 561 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 562 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 563 564 /* Check for MRBE auto-negotiated speed results. */ 565 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 566 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 567 mii->mii_media_active |= IFM_10_FL; break; 568 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 569 mii->mii_media_active |= IFM_100_FX; break; 570 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 571 mii->mii_media_active |= IFM_1000_SX; break; 572 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 573 mii->mii_media_active |= IFM_2500_SX; break; 574 } 575 576 /* Check for MRBE auto-negotiated duplex results. */ 577 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 578 mii->mii_media_active |= IFM_FDX; 579 else 580 mii->mii_media_active |= IFM_HDX; 581 } else if (bsc->serdes_flags & BRGPHY_5709S) { 582 /* Select GP Status Block of the AN MMD, get autoneg results. */ 583 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 584 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 585 586 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 587 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 588 589 /* Check for MRBE auto-negotiated speed results. */ 590 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 591 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 592 mii->mii_media_active |= IFM_10_FL; break; 593 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 594 mii->mii_media_active |= IFM_100_FX; break; 595 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 596 mii->mii_media_active |= IFM_1000_SX; break; 597 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 598 mii->mii_media_active |= IFM_2500_SX; break; 599 } 600 601 /* Check for MRBE auto-negotiated duplex results. */ 602 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 603 mii->mii_media_active |= IFM_FDX; 604 else 605 mii->mii_media_active |= IFM_HDX; 606 } 607 } 608 } 609 610 static void 611 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 612 { 613 int anar, ktcr = 0; 614 615 PHY_RESET(sc); 616 617 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 618 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 619 if ((media & IFM_FLOW) != 0 || 620 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 621 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 622 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 623 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 624 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 625 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 626 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 627 PHY_READ(sc, BRGPHY_MII_1000CTL); 628 } else { 629 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 630 if ((media & IFM_FLOW) != 0 || 631 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 632 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 633 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 634 } 635 636 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 637 BRGPHY_BMCR_STARTNEG); 638 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 639 } 640 641 /* Enable loopback to force the link down. */ 642 static void 643 brgphy_enable_loopback(struct mii_softc *sc) 644 { 645 int i; 646 647 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 648 for (i = 0; i < 15000; i++) { 649 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 650 break; 651 DELAY(10); 652 } 653 } 654 655 /* Turn off tap power management on 5401. */ 656 static void 657 bcm5401_load_dspcode(struct mii_softc *sc) 658 { 659 static const struct { 660 int reg; 661 uint16_t val; 662 } dspcode[] = { 663 { BRGPHY_MII_AUXCTL, 0x0c20 }, 664 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 665 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 666 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 667 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 668 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 669 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 670 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 671 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 672 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 673 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 674 { 0, 0 }, 675 }; 676 int i; 677 678 for (i = 0; dspcode[i].reg != 0; i++) 679 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 680 DELAY(40); 681 } 682 683 static void 684 bcm5411_load_dspcode(struct mii_softc *sc) 685 { 686 static const struct { 687 int reg; 688 uint16_t val; 689 } dspcode[] = { 690 { 0x1c, 0x8c23 }, 691 { 0x1c, 0x8ca3 }, 692 { 0x1c, 0x8c23 }, 693 { 0, 0 }, 694 }; 695 int i; 696 697 for (i = 0; dspcode[i].reg != 0; i++) 698 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 699 } 700 701 void 702 bcm54k2_load_dspcode(struct mii_softc *sc) 703 { 704 static const struct { 705 int reg; 706 uint16_t val; 707 } dspcode[] = { 708 { 4, 0x01e1 }, 709 { 9, 0x0300 }, 710 { 0, 0 }, 711 }; 712 int i; 713 714 for (i = 0; dspcode[i].reg != 0; i++) 715 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 716 717 } 718 719 static void 720 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 721 { 722 static const struct { 723 int reg; 724 uint16_t val; 725 } dspcode[] = { 726 { 0x1c, 0x8d68 }, 727 { 0x1c, 0x8d68 }, 728 { 0, 0 }, 729 }; 730 int i; 731 732 for (i = 0; dspcode[i].reg != 0; i++) 733 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 734 } 735 736 static void 737 brgphy_fixup_adc_bug(struct mii_softc *sc) 738 { 739 static const struct { 740 int reg; 741 uint16_t val; 742 } dspcode[] = { 743 { BRGPHY_MII_AUXCTL, 0x0c00 }, 744 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 745 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 746 { 0, 0 }, 747 }; 748 int i; 749 750 for (i = 0; dspcode[i].reg != 0; i++) 751 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 752 } 753 754 static void 755 brgphy_fixup_adjust_trim(struct mii_softc *sc) 756 { 757 static const struct { 758 int reg; 759 uint16_t val; 760 } dspcode[] = { 761 { BRGPHY_MII_AUXCTL, 0x0c00 }, 762 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 763 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 764 { BRGPHY_MII_TEST1, 0x0014 }, 765 { BRGPHY_MII_AUXCTL, 0x0400 }, 766 { 0, 0 }, 767 }; 768 int i; 769 770 for (i = 0; dspcode[i].reg != 0; i++) 771 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 772 } 773 774 static void 775 brgphy_fixup_ber_bug(struct mii_softc *sc) 776 { 777 static const struct { 778 int reg; 779 uint16_t val; 780 } dspcode[] = { 781 { BRGPHY_MII_AUXCTL, 0x0c00 }, 782 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 783 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 784 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 785 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 786 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 787 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 788 { BRGPHY_MII_AUXCTL, 0x0400 }, 789 { 0, 0 }, 790 }; 791 int i; 792 793 for (i = 0; dspcode[i].reg != 0; i++) 794 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 795 } 796 797 static void 798 brgphy_fixup_crc_bug(struct mii_softc *sc) 799 { 800 static const struct { 801 int reg; 802 uint16_t val; 803 } dspcode[] = { 804 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 805 { 0x1c, 0x8c68 }, 806 { 0x1c, 0x8d68 }, 807 { 0x1c, 0x8c68 }, 808 { 0, 0 }, 809 }; 810 int i; 811 812 for (i = 0; dspcode[i].reg != 0; i++) 813 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 814 } 815 816 static void 817 brgphy_fixup_jitter_bug(struct mii_softc *sc) 818 { 819 static const struct { 820 int reg; 821 uint16_t val; 822 } dspcode[] = { 823 { BRGPHY_MII_AUXCTL, 0x0c00 }, 824 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 825 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 826 { BRGPHY_MII_AUXCTL, 0x0400 }, 827 { 0, 0 }, 828 }; 829 int i; 830 831 for (i = 0; dspcode[i].reg != 0; i++) 832 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 833 } 834 835 static void 836 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 837 { 838 uint32_t val; 839 840 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 841 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 842 val &= ~(1 << 8); 843 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 844 845 } 846 847 static void 848 brgphy_ethernet_wirespeed(struct mii_softc *sc) 849 { 850 uint32_t val; 851 852 /* Enable Ethernet@WireSpeed. */ 853 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 854 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 855 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 856 } 857 858 static void 859 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 860 { 861 uint32_t val; 862 863 /* Set or clear jumbo frame settings in the PHY. */ 864 if (mtu > ETHER_MAX_LEN) { 865 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 866 /* BCM5401 PHY cannot read-modify-write. */ 867 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 868 } else { 869 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 870 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 871 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 872 val | BRGPHY_AUXCTL_LONG_PKT); 873 } 874 875 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 876 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 877 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 878 } else { 879 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 880 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 881 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 882 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 883 884 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 885 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 886 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 887 } 888 } 889 890 static void 891 brgphy_reset(struct mii_softc *sc) 892 { 893 struct bge_softc *bge_sc = NULL; 894 struct bce_softc *bce_sc = NULL; 895 if_t ifp; 896 int i, val; 897 898 /* 899 * Perform a reset. Note that at least some Broadcom PHYs default to 900 * being powered down as well as isolated after a reset but don't work 901 * if one or both of these bits are cleared. However, they just work 902 * fine if both bits remain set, so we don't use mii_phy_reset() here. 903 */ 904 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 905 906 /* Wait 100ms for it to complete. */ 907 for (i = 0; i < 100; i++) { 908 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 909 break; 910 DELAY(1000); 911 } 912 913 /* Handle any PHY specific procedures following the reset. */ 914 switch (sc->mii_mpd_oui) { 915 case MII_OUI_BROADCOM: 916 switch (sc->mii_mpd_model) { 917 case MII_MODEL_BROADCOM_BCM5400: 918 bcm5401_load_dspcode(sc); 919 break; 920 case MII_MODEL_BROADCOM_BCM5401: 921 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 922 bcm5401_load_dspcode(sc); 923 break; 924 case MII_MODEL_BROADCOM_BCM5411: 925 bcm5411_load_dspcode(sc); 926 break; 927 case MII_MODEL_BROADCOM_BCM54K2: 928 bcm54k2_load_dspcode(sc); 929 break; 930 } 931 break; 932 case MII_OUI_BROADCOM3: 933 switch (sc->mii_mpd_model) { 934 case MII_MODEL_BROADCOM3_BCM5717C: 935 case MII_MODEL_BROADCOM3_BCM5719C: 936 case MII_MODEL_BROADCOM3_BCM5720C: 937 case MII_MODEL_BROADCOM3_BCM57765: 938 return; 939 } 940 break; 941 case MII_OUI_BROADCOM4: 942 return; 943 } 944 945 ifp = sc->mii_pdata->mii_ifp; 946 947 /* Find the driver associated with this PHY. */ 948 if (mii_phy_mac_match(sc, "bge")) 949 bge_sc = mii_phy_mac_softc(sc); 950 else if (mii_phy_mac_match(sc, "bce")) 951 bce_sc = mii_phy_mac_softc(sc); 952 953 if (bge_sc) { 954 /* Fix up various bugs */ 955 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 956 brgphy_fixup_5704_a0_bug(sc); 957 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 958 brgphy_fixup_adc_bug(sc); 959 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 960 brgphy_fixup_adjust_trim(sc); 961 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 962 brgphy_fixup_ber_bug(sc); 963 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 964 brgphy_fixup_crc_bug(sc); 965 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 966 brgphy_fixup_jitter_bug(sc); 967 968 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 969 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 970 971 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 972 brgphy_ethernet_wirespeed(sc); 973 974 /* Enable Link LED on Dell boxes */ 975 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 976 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 977 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 978 ~BRGPHY_PHY_EXTCTL_3_LED); 979 } 980 981 /* Adjust output voltage (From Linux driver) */ 982 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 983 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 984 } else if (bce_sc) { 985 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 986 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 987 988 /* Store autoneg capabilities/results in digital block (Page 0) */ 989 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 990 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 991 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 992 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 993 994 /* Enable fiber mode and autodetection */ 995 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 996 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 997 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 998 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 999 1000 /* Enable parallel detection */ 1001 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1002 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1003 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1004 1005 /* Advertise 2.5G support through next page during autoneg */ 1006 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1007 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1008 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1009 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1010 1011 /* Increase TX signal amplitude */ 1012 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1013 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1014 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1015 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1016 BRGPHY_5708S_TX_MISC_PG5); 1017 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1018 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1019 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1020 BRGPHY_5708S_DIG_PG0); 1021 } 1022 1023 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1024 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1025 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1026 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1027 BRGPHY_5708S_TX_MISC_PG5); 1028 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1029 bce_sc->bce_port_hw_cfg & 1030 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1031 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1032 BRGPHY_5708S_DIG_PG0); 1033 } 1034 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1035 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1036 1037 /* Select the SerDes Digital block of the AN MMD. */ 1038 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1039 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1040 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1041 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1042 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1043 1044 /* Select the Over 1G block of the AN MMD. */ 1045 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1046 1047 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1048 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1049 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1050 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1051 else 1052 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1053 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1054 1055 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1056 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1057 1058 /* Enable MRBE speed autoneg. */ 1059 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1060 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1061 BRGPHY_MRBE_MSG_PG5_NP_T2; 1062 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1063 1064 /* Select the Clause 73 User B0 block of the AN MMD. */ 1065 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1066 1067 /* Enable MRBE speed autoneg. */ 1068 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1069 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1070 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1071 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1072 1073 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1074 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1075 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1076 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1077 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1078 brgphy_fixup_disable_early_dac(sc); 1079 1080 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1081 brgphy_ethernet_wirespeed(sc); 1082 } else { 1083 brgphy_fixup_ber_bug(sc); 1084 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1085 brgphy_ethernet_wirespeed(sc); 1086 } 1087 } 1088 } 1089