1 /* 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 48 #include <machine/clock.h> 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include "miidevs.h" 56 57 #include <dev/mii/brgphyreg.h> 58 #include <net/if_arp.h> 59 #include <machine/bus.h> 60 #include <dev/bge/if_bgereg.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 65 #include "miibus_if.h" 66 67 static int brgphy_probe(device_t); 68 static int brgphy_attach(device_t); 69 70 static device_method_t brgphy_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, brgphy_probe), 73 DEVMETHOD(device_attach, brgphy_attach), 74 DEVMETHOD(device_detach, mii_phy_detach), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 { 0, 0 } 77 }; 78 79 static devclass_t brgphy_devclass; 80 81 static driver_t brgphy_driver = { 82 "brgphy", 83 brgphy_methods, 84 sizeof(struct mii_softc) 85 }; 86 87 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 88 89 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 90 static void brgphy_status(struct mii_softc *); 91 static int brgphy_mii_phy_auto(struct mii_softc *); 92 static void brgphy_reset(struct mii_softc *); 93 static void brgphy_loop(struct mii_softc *); 94 static void bcm5401_load_dspcode(struct mii_softc *); 95 static void bcm5411_load_dspcode(struct mii_softc *); 96 static void bcm5703_load_dspcode(struct mii_softc *); 97 static int brgphy_mii_model; 98 99 static int 100 brgphy_probe(dev) 101 device_t dev; 102 { 103 struct mii_attach_args *ma; 104 105 ma = device_get_ivars(dev); 106 107 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 108 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 109 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 110 return(0); 111 } 112 113 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 114 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 115 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 116 return(0); 117 } 118 119 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 120 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 121 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 122 return(0); 123 } 124 125 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 126 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 127 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 128 return(0); 129 } 130 131 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 132 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 133 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 134 return(0); 135 } 136 137 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 138 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 139 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 140 return(0); 141 } 142 143 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 144 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 145 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 146 return(0); 147 } 148 149 return(ENXIO); 150 } 151 152 static int 153 brgphy_attach(dev) 154 device_t dev; 155 { 156 struct mii_softc *sc; 157 struct mii_attach_args *ma; 158 struct mii_data *mii; 159 const char *sep = ""; 160 struct bge_softc *bge_sc; 161 int fast_ether_only = FALSE; 162 163 sc = device_get_softc(dev); 164 ma = device_get_ivars(dev); 165 sc->mii_dev = device_get_parent(dev); 166 mii = device_get_softc(sc->mii_dev); 167 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 168 169 sc->mii_inst = mii->mii_instance; 170 sc->mii_phy = ma->mii_phyno; 171 sc->mii_service = brgphy_service; 172 sc->mii_pdata = mii; 173 174 sc->mii_flags |= MIIF_NOISOLATE; 175 mii->mii_instance++; 176 177 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 178 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 179 180 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 181 BMCR_ISO); 182 #if 0 183 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 184 BMCR_LOOP|BMCR_S100); 185 #endif 186 187 brgphy_mii_model = MII_MODEL(ma->mii_id2); 188 brgphy_reset(sc); 189 190 191 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 192 sc->mii_capabilities &= ~BMSR_ANEG; 193 device_printf(dev, " "); 194 mii_add_media(sc); 195 196 /* The 590x chips are 10/100 only. */ 197 198 bge_sc = mii->mii_ifp->if_softc; 199 200 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 201 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 202 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 203 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 204 fast_ether_only = TRUE; 205 206 if (fast_ether_only == FALSE) { 207 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 208 sc->mii_inst), BRGPHY_BMCR_FDX); 209 PRINT(", 1000baseTX"); 210 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 211 IFM_FDX, sc->mii_inst), 0); 212 PRINT("1000baseTX-FDX"); 213 } 214 215 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 216 PRINT("auto"); 217 218 printf("\n"); 219 #undef ADD 220 #undef PRINT 221 222 MIIBUS_MEDIAINIT(sc->mii_dev); 223 return(0); 224 } 225 226 static int 227 brgphy_service(sc, mii, cmd) 228 struct mii_softc *sc; 229 struct mii_data *mii; 230 int cmd; 231 { 232 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 233 int reg, speed, gig; 234 235 switch (cmd) { 236 case MII_POLLSTAT: 237 /* 238 * If we're not polling our PHY instance, just return. 239 */ 240 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 241 return (0); 242 break; 243 244 case MII_MEDIACHG: 245 /* 246 * If the media indicates a different PHY instance, 247 * isolate ourselves. 248 */ 249 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 250 reg = PHY_READ(sc, MII_BMCR); 251 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 252 return (0); 253 } 254 255 /* 256 * If the interface is not up, don't do anything. 257 */ 258 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 259 break; 260 261 brgphy_reset(sc); /* XXX hardware bug work-around */ 262 263 switch (IFM_SUBTYPE(ife->ifm_media)) { 264 case IFM_AUTO: 265 #ifdef foo 266 /* 267 * If we're already in auto mode, just return. 268 */ 269 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 270 return (0); 271 #endif 272 (void) brgphy_mii_phy_auto(sc); 273 break; 274 case IFM_1000_T: 275 speed = BRGPHY_S1000; 276 goto setit; 277 case IFM_100_TX: 278 speed = BRGPHY_S100; 279 goto setit; 280 case IFM_10_T: 281 speed = BRGPHY_S10; 282 setit: 283 brgphy_loop(sc); 284 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 285 speed |= BRGPHY_BMCR_FDX; 286 gig = BRGPHY_1000CTL_AFD; 287 } else { 288 gig = BRGPHY_1000CTL_AHD; 289 } 290 291 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 292 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 293 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 294 295 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 296 break; 297 298 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 299 PHY_WRITE(sc, BRGPHY_MII_BMCR, 300 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 301 302 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 303 break; 304 305 /* 306 * When settning the link manually, one side must 307 * be the master and the other the slave. However 308 * ifmedia doesn't give us a good way to specify 309 * this, so we fake it by using one of the LINK 310 * flags. If LINK0 is set, we program the PHY to 311 * be a master, otherwise it's a slave. 312 */ 313 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 314 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 315 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 316 } else { 317 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 318 gig|BRGPHY_1000CTL_MSE); 319 } 320 break; 321 #ifdef foo 322 case IFM_NONE: 323 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 324 break; 325 #endif 326 case IFM_100_T4: 327 default: 328 return (EINVAL); 329 } 330 break; 331 332 case MII_TICK: 333 /* 334 * If we're not currently selected, just return. 335 */ 336 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 337 return (0); 338 339 /* 340 * Is the interface even up? 341 */ 342 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 343 return (0); 344 345 /* 346 * Only used for autonegotiation. 347 */ 348 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 349 break; 350 351 /* 352 * Check to see if we have link. If we do, we don't 353 * need to restart the autonegotiation process. Read 354 * the BMSR twice in case it's latched. 355 */ 356 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 357 if (reg & BRGPHY_AUXSTS_LINK) 358 break; 359 360 /* 361 * Only retry autonegotiation every 5 seconds. 362 */ 363 if (++sc->mii_ticks <= 5) 364 break; 365 366 sc->mii_ticks = 0; 367 brgphy_mii_phy_auto(sc); 368 return (0); 369 } 370 371 /* Update the media status. */ 372 brgphy_status(sc); 373 374 /* 375 * Callback if something changed. Note that we need to poke 376 * the DSP on the Broadcom PHYs if the media changes. 377 * 378 */ 379 if (sc->mii_media_active != mii->mii_media_active || 380 sc->mii_media_status != mii->mii_media_status || 381 cmd == MII_MEDIACHG) { 382 switch (brgphy_mii_model) { 383 case MII_MODEL_xxBROADCOM_BCM5401: 384 bcm5401_load_dspcode(sc); 385 break; 386 case MII_MODEL_xxBROADCOM_BCM5411: 387 bcm5411_load_dspcode(sc); 388 break; 389 } 390 } 391 mii_phy_update(sc, cmd); 392 return (0); 393 } 394 395 static void 396 brgphy_status(sc) 397 struct mii_softc *sc; 398 { 399 struct mii_data *mii = sc->mii_pdata; 400 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 401 int bmsr, bmcr; 402 403 mii->mii_media_status = IFM_AVALID; 404 mii->mii_media_active = IFM_ETHER; 405 406 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 407 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 408 mii->mii_media_status |= IFM_ACTIVE; 409 410 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 411 412 if (bmcr & BRGPHY_BMCR_LOOP) 413 mii->mii_media_active |= IFM_LOOP; 414 415 if (bmcr & BRGPHY_BMCR_AUTOEN) { 416 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 417 /* Erg, still trying, I guess... */ 418 mii->mii_media_active |= IFM_NONE; 419 return; 420 } 421 422 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 423 BRGPHY_AUXSTS_AN_RES) { 424 case BRGPHY_RES_1000FD: 425 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 426 break; 427 case BRGPHY_RES_1000HD: 428 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 429 break; 430 case BRGPHY_RES_100FD: 431 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 432 break; 433 case BRGPHY_RES_100T4: 434 mii->mii_media_active |= IFM_100_T4; 435 break; 436 case BRGPHY_RES_100HD: 437 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 438 break; 439 case BRGPHY_RES_10FD: 440 mii->mii_media_active |= IFM_10_T | IFM_FDX; 441 break; 442 case BRGPHY_RES_10HD: 443 mii->mii_media_active |= IFM_10_T | IFM_HDX; 444 break; 445 default: 446 mii->mii_media_active |= IFM_NONE; 447 break; 448 } 449 return; 450 } 451 452 mii->mii_media_active = ife->ifm_media; 453 454 return; 455 } 456 457 458 static int 459 brgphy_mii_phy_auto(mii) 460 struct mii_softc *mii; 461 { 462 int ktcr = 0; 463 464 brgphy_loop(mii); 465 brgphy_reset(mii); 466 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 467 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 468 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 469 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 470 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 471 DELAY(1000); 472 PHY_WRITE(mii, BRGPHY_MII_ANAR, 473 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 474 DELAY(1000); 475 PHY_WRITE(mii, BRGPHY_MII_BMCR, 476 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 477 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 478 return (EJUSTRETURN); 479 } 480 481 static void 482 brgphy_loop(struct mii_softc *sc) 483 { 484 u_int32_t bmsr; 485 int i; 486 487 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 488 for (i = 0; i < 15000; i++) { 489 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 490 if (!(bmsr & BRGPHY_BMSR_LINK)) { 491 #if 0 492 device_printf(sc->mii_dev, "looped %d\n", i); 493 #endif 494 break; 495 } 496 DELAY(10); 497 } 498 } 499 500 /* Turn off tap power management on 5401. */ 501 static void 502 bcm5401_load_dspcode(struct mii_softc *sc) 503 { 504 static const struct { 505 int reg; 506 uint16_t val; 507 } dspcode[] = { 508 { BRGPHY_MII_AUXCTL, 0x0c20 }, 509 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 510 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 511 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 512 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 513 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 514 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 515 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 516 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 517 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 518 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 519 { 0, 0 }, 520 }; 521 int i; 522 523 for (i = 0; dspcode[i].reg != 0; i++) 524 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 525 DELAY(40); 526 } 527 528 static void 529 bcm5411_load_dspcode(struct mii_softc *sc) 530 { 531 static const struct { 532 int reg; 533 uint16_t val; 534 } dspcode[] = { 535 { 0x1c, 0x8c23 }, 536 { 0x1c, 0x8ca3 }, 537 { 0x1c, 0x8c23 }, 538 { 0, 0 }, 539 }; 540 int i; 541 542 for (i = 0; dspcode[i].reg != 0; i++) 543 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 544 } 545 546 static void 547 bcm5703_load_dspcode(struct mii_softc *sc) 548 { 549 static const struct { 550 int reg; 551 uint16_t val; 552 } dspcode[] = { 553 { BRGPHY_MII_AUXCTL, 0x0c00 }, 554 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 555 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 556 { 0, 0 }, 557 }; 558 int i; 559 560 for (i = 0; dspcode[i].reg != 0; i++) 561 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 562 } 563 564 static void 565 bcm5704_load_dspcode(struct mii_softc *sc) 566 { 567 static const struct { 568 int reg; 569 u_int16_t val; 570 } dspcode[] = { 571 { 0x1c, 0x8d68 }, 572 { 0x1c, 0x8d68 }, 573 { 0, 0 }, 574 }; 575 int i; 576 577 for (i = 0; dspcode[i].reg != 0; i++) 578 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 579 } 580 581 static void 582 brgphy_reset(struct mii_softc *sc) 583 { 584 u_int32_t val; 585 struct ifnet *ifp; 586 struct bge_softc *bge_sc; 587 588 mii_phy_reset(sc); 589 590 switch (brgphy_mii_model) { 591 case MII_MODEL_xxBROADCOM_BCM5401: 592 bcm5401_load_dspcode(sc); 593 break; 594 case MII_MODEL_xxBROADCOM_BCM5411: 595 bcm5411_load_dspcode(sc); 596 break; 597 case MII_MODEL_xxBROADCOM_BCM5703: 598 bcm5703_load_dspcode(sc); 599 break; 600 case MII_MODEL_xxBROADCOM_BCM5704: 601 bcm5704_load_dspcode(sc); 602 break; 603 } 604 605 ifp = sc->mii_pdata->mii_ifp; 606 bge_sc = ifp->if_softc; 607 608 /* 609 * Don't enable Ethernet@WireSpeed for the 5700 or the 610 * 5705 A1 and A2 chips. Make sure we only do this test 611 * on "bge" NICs, since other drivers may use this same 612 * PHY subdriver. 613 */ 614 if (strcmp(ifp->if_dname, "bge") == 0 && 615 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 616 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 617 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)) 618 return; 619 620 /* Enable Ethernet@WireSpeed. */ 621 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 622 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 623 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 624 625 /* Enable Link LED on Dell boxes */ 626 if (bge_sc->bge_no_3_led) { 627 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 628 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 629 & ~BRGPHY_PHY_EXTCTL_3_LED); 630 } 631 } 632