1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/brgphyreg.h> 56 #include <net/if_arp.h> 57 #include <machine/bus.h> 58 #include <dev/bge/if_bgereg.h> 59 #include <dev/bce/if_bcereg.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 #include "miibus_if.h" 65 66 static int brgphy_probe(device_t); 67 static int brgphy_attach(device_t); 68 69 struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int mii_oui; 72 int mii_model; 73 int mii_rev; 74 int serdes_flags; /* Keeps track of the serdes type used */ 75 #define BRGPHY_5706S 0x0001 76 #define BRGPHY_5708S 0x0002 77 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 78 }; 79 80 static device_method_t brgphy_methods[] = { 81 /* device interface */ 82 DEVMETHOD(device_probe, brgphy_probe), 83 DEVMETHOD(device_attach, brgphy_attach), 84 DEVMETHOD(device_detach, mii_phy_detach), 85 DEVMETHOD(device_shutdown, bus_generic_shutdown), 86 { 0, 0 } 87 }; 88 89 static devclass_t brgphy_devclass; 90 91 static driver_t brgphy_driver = { 92 "brgphy", 93 brgphy_methods, 94 sizeof(struct brgphy_softc) 95 }; 96 97 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 98 99 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 100 static void brgphy_setmedia(struct mii_softc *, int, int); 101 static void brgphy_status(struct mii_softc *); 102 static void brgphy_mii_phy_auto(struct mii_softc *); 103 static void brgphy_reset(struct mii_softc *); 104 static void brgphy_enable_loopback(struct mii_softc *); 105 static void bcm5401_load_dspcode(struct mii_softc *); 106 static void bcm5411_load_dspcode(struct mii_softc *); 107 static void bcm54k2_load_dspcode(struct mii_softc *); 108 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 109 static void brgphy_fixup_adc_bug(struct mii_softc *); 110 static void brgphy_fixup_adjust_trim(struct mii_softc *); 111 static void brgphy_fixup_ber_bug(struct mii_softc *); 112 static void brgphy_fixup_crc_bug(struct mii_softc *); 113 static void brgphy_fixup_jitter_bug(struct mii_softc *); 114 static void brgphy_ethernet_wirespeed(struct mii_softc *); 115 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 116 117 static const struct mii_phydesc brgphys[] = { 118 MII_PHY_DESC(xxBROADCOM, BCM5400), 119 MII_PHY_DESC(xxBROADCOM, BCM5401), 120 MII_PHY_DESC(xxBROADCOM, BCM5411), 121 MII_PHY_DESC(xxBROADCOM, BCM54K2), 122 MII_PHY_DESC(xxBROADCOM, BCM5701), 123 MII_PHY_DESC(xxBROADCOM, BCM5703), 124 MII_PHY_DESC(xxBROADCOM, BCM5704), 125 MII_PHY_DESC(xxBROADCOM, BCM5705), 126 MII_PHY_DESC(xxBROADCOM, BCM5706), 127 MII_PHY_DESC(xxBROADCOM, BCM5714), 128 MII_PHY_DESC(xxBROADCOM, BCM5750), 129 MII_PHY_DESC(xxBROADCOM, BCM5752), 130 MII_PHY_DESC(xxBROADCOM, BCM5754), 131 MII_PHY_DESC(xxBROADCOM, BCM5780), 132 MII_PHY_DESC(xxBROADCOM, BCM5708C), 133 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 134 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), 136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), 137 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), 138 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784), 139 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), 140 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761), 141 MII_PHY_DESC(BROADCOM2, BCM5906), 142 MII_PHY_END 143 }; 144 145 146 /* Search for our PHY in the list of known PHYs */ 147 static int 148 brgphy_probe(device_t dev) 149 { 150 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 151 } 152 153 /* Attach the PHY to the MII bus */ 154 static int 155 brgphy_attach(device_t dev) 156 { 157 struct brgphy_softc *bsc; 158 struct bge_softc *bge_sc = NULL; 159 struct bce_softc *bce_sc = NULL; 160 struct mii_softc *sc; 161 struct mii_attach_args *ma; 162 struct mii_data *mii; 163 struct ifnet *ifp; 164 int fast_ether; 165 166 bsc = device_get_softc(dev); 167 sc = &bsc->mii_sc; 168 ma = device_get_ivars(dev); 169 sc->mii_dev = device_get_parent(dev); 170 mii = device_get_softc(sc->mii_dev); 171 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 172 173 /* Initialize mii_softc structure */ 174 sc->mii_inst = mii->mii_instance; 175 sc->mii_phy = ma->mii_phyno; 176 sc->mii_service = brgphy_service; 177 sc->mii_pdata = mii; 178 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 179 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 180 mii->mii_instance++; 181 182 /* Initialize brgphy_softc structure */ 183 bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 184 bsc->mii_model = MII_MODEL(ma->mii_id2); 185 bsc->mii_rev = MII_REV(ma->mii_id2); 186 bsc->serdes_flags = 0; 187 188 fast_ether = 0; 189 190 if (bootverbose) 191 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", 192 bsc->mii_oui, bsc->mii_model, bsc->mii_rev); 193 194 /* Handle any special cases based on the PHY ID */ 195 switch (bsc->mii_oui) { 196 case MII_OUI_BROADCOM: 197 case MII_OUI_BROADCOM2: 198 break; 199 case MII_OUI_xxBROADCOM: 200 switch (bsc->mii_model) { 201 case MII_MODEL_xxBROADCOM_BCM5706: 202 case MII_MODEL_xxBROADCOM_BCM5714: 203 /* 204 * The 5464 PHY used in the 5706 supports both copper 205 * and fiber interfaces over GMII. Need to check the 206 * shadow registers to see which mode is actually 207 * in effect, and therefore whether we have 5706C or 208 * 5706S. 209 */ 210 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 211 BRGPHY_SHADOW_1C_MODE_CTRL); 212 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 213 BRGPHY_SHADOW_1C_ENA_1000X) { 214 bsc->serdes_flags |= BRGPHY_5706S; 215 sc->mii_flags |= MIIF_HAVEFIBER; 216 } 217 break; 218 } break; 219 case MII_OUI_xxBROADCOM_ALT1: 220 switch (bsc->mii_model) { 221 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: 222 bsc->serdes_flags |= BRGPHY_5708S; 223 sc->mii_flags |= MIIF_HAVEFIBER; 224 break; 225 } break; 226 default: 227 device_printf(dev, "Unrecognized OUI for PHY!\n"); 228 } 229 230 ifp = sc->mii_pdata->mii_ifp; 231 232 /* Find the MAC driver associated with this PHY. */ 233 if (strcmp(ifp->if_dname, "bge") == 0) { 234 bge_sc = ifp->if_softc; 235 } else if (strcmp(ifp->if_dname, "bce") == 0) { 236 bce_sc = ifp->if_softc; 237 } 238 239 /* Todo: Need to add additional controllers such as 5906 & 5787F */ 240 /* The 590x chips are 10/100 only. */ 241 if (bge_sc && 242 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 243 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 244 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 || 245 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 || 246 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) { 247 fast_ether = 1; 248 sc->mii_anegticks = MII_ANEGTICKS; 249 } 250 251 brgphy_reset(sc); 252 253 /* Read the PHY's capabilities. */ 254 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 255 if (sc->mii_capabilities & BMSR_EXTSTAT) 256 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 257 device_printf(dev, " "); 258 259 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 260 261 /* Create an instance of Ethernet media. */ 262 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO); 263 264 /* Add the supported media types */ 265 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 266 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), 267 BRGPHY_S10); 268 printf("10baseT, "); 269 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst), 270 BRGPHY_S10 | BRGPHY_BMCR_FDX); 271 printf("10baseT-FDX, "); 272 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), 273 BRGPHY_S100); 274 printf("100baseTX, "); 275 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst), 276 BRGPHY_S100 | BRGPHY_BMCR_FDX); 277 printf("100baseTX-FDX, "); 278 if (fast_ether == 0) { 279 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 280 BRGPHY_S1000); 281 printf("1000baseT, "); 282 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 283 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 284 printf("1000baseT-FDX, "); 285 } 286 } else { 287 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 288 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 289 printf("1000baseSX-FDX, "); 290 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 291 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 292 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 293 printf("2500baseSX-FDX, "); 294 } 295 } 296 297 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 298 printf("auto\n"); 299 300 #undef ADD 301 MIIBUS_MEDIAINIT(sc->mii_dev); 302 return (0); 303 } 304 305 static int 306 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 307 { 308 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 309 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 310 int error = 0; 311 int val; 312 313 switch (cmd) { 314 case MII_POLLSTAT: 315 /* If we're not polling our PHY instance, just return. */ 316 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 317 goto brgphy_service_exit; 318 break; 319 case MII_MEDIACHG: 320 /* 321 * If the media indicates a different PHY instance, 322 * isolate ourselves. 323 */ 324 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 325 PHY_WRITE(sc, MII_BMCR, 326 PHY_READ(sc, MII_BMCR) | BMCR_ISO); 327 goto brgphy_service_exit; 328 } 329 330 /* If the interface is not up, don't do anything. */ 331 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 332 break; 333 334 /* Todo: Why is this here? Is it really needed? */ 335 brgphy_reset(sc); /* XXX hardware bug work-around */ 336 337 switch (IFM_SUBTYPE(ife->ifm_media)) { 338 case IFM_AUTO: 339 brgphy_mii_phy_auto(sc); 340 break; 341 case IFM_2500_SX: 342 case IFM_1000_SX: 343 case IFM_1000_T: 344 case IFM_100_TX: 345 case IFM_10_T: 346 brgphy_setmedia(sc, ife->ifm_media, 347 mii->mii_ifp->if_flags & IFF_LINK0); 348 break; 349 default: 350 error = EINVAL; 351 goto brgphy_service_exit; 352 } 353 break; 354 case MII_TICK: 355 /* Bail if we're not currently selected. */ 356 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 357 goto brgphy_service_exit; 358 359 /* Bail if the interface isn't up. */ 360 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 361 goto brgphy_service_exit; 362 363 364 /* Bail if autoneg isn't in process. */ 365 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 366 sc->mii_ticks = 0; 367 break; 368 } 369 370 /* 371 * Check to see if we have link. If we do, we don't 372 * need to restart the autonegotiation process. 373 */ 374 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 375 if (val & BMSR_LINK) { 376 sc->mii_ticks = 0; /* Reset autoneg timer. */ 377 break; 378 } 379 380 /* Announce link loss right after it happens. */ 381 if (sc->mii_ticks++ == 0) 382 break; 383 384 /* Only retry autonegotiation every mii_anegticks seconds. */ 385 if (sc->mii_ticks <= sc->mii_anegticks) 386 break; 387 388 389 /* Retry autonegotiation */ 390 sc->mii_ticks = 0; 391 brgphy_mii_phy_auto(sc); 392 break; 393 } 394 395 /* Update the media status. */ 396 brgphy_status(sc); 397 398 /* 399 * Callback if something changed. Note that we need to poke 400 * the DSP on the Broadcom PHYs if the media changes. 401 */ 402 if (sc->mii_media_active != mii->mii_media_active || 403 sc->mii_media_status != mii->mii_media_status || 404 cmd == MII_MEDIACHG) { 405 switch (bsc->mii_oui) { 406 case MII_OUI_BROADCOM: 407 break; 408 case MII_OUI_xxBROADCOM: 409 switch (bsc->mii_model) { 410 case MII_MODEL_xxBROADCOM_BCM5400: 411 bcm5401_load_dspcode(sc); 412 break; 413 case MII_MODEL_xxBROADCOM_BCM5401: 414 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 415 bcm5401_load_dspcode(sc); 416 break; 417 case MII_MODEL_xxBROADCOM_BCM5411: 418 bcm5411_load_dspcode(sc); 419 break; 420 case MII_MODEL_xxBROADCOM_BCM54K2: 421 bcm54k2_load_dspcode(sc); 422 break; 423 } 424 break; 425 case MII_OUI_xxBROADCOM_ALT1: 426 break; 427 } 428 } 429 mii_phy_update(sc, cmd); 430 brgphy_service_exit: 431 return (error); 432 } 433 434 435 /****************************************************************************/ 436 /* Sets the PHY link speed. */ 437 /* */ 438 /* Returns: */ 439 /* None */ 440 /****************************************************************************/ 441 static void 442 brgphy_setmedia(struct mii_softc *sc, int media, int master) 443 { 444 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 445 int bmcr = 0, gig; 446 447 /* Calculate the value for the BMCR register. */ 448 switch (IFM_SUBTYPE(media)) { 449 case IFM_2500_SX: 450 break; 451 case IFM_1000_SX: 452 case IFM_1000_T: 453 bmcr = BRGPHY_S1000; 454 break; 455 case IFM_100_TX: 456 bmcr = BRGPHY_S100; 457 break; 458 case IFM_10_T: 459 default: 460 bmcr = BRGPHY_S10; 461 break; 462 } 463 464 /* Calculate duplex settings for 1000BasetT/1000BaseX. */ 465 if ((media & IFM_GMASK) == IFM_FDX) { 466 bmcr |= BRGPHY_BMCR_FDX; 467 gig = BRGPHY_1000CTL_AFD; 468 } else { 469 gig = BRGPHY_1000CTL_AHD; 470 } 471 472 /* Force loopback to disconnect PHY for Ethernet medium. */ 473 brgphy_enable_loopback(sc); 474 475 /* Disable 1000BaseT advertisements. */ 476 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 477 /* Disable 10/100 advertisements. */ 478 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 479 /* Write forced link speed. */ 480 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 481 482 /* If 10/100 only then configuration is complete. */ 483 if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX)) 484 goto brgphy_setmedia_exit; 485 486 /* Set duplex speed advertisement for 1000BaseT/1000BaseX. */ 487 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 488 /* Restart auto-negotiation for 1000BaseT/1000BaseX. */ 489 PHY_WRITE(sc, BRGPHY_MII_BMCR, 490 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 491 492 /* If not 5701 PHY then configuration is complete. */ 493 if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 494 goto brgphy_setmedia_exit; 495 496 /* 497 * When setting the link manually, one side must be the master and 498 * the other the slave. However ifmedia doesn't give us a good way 499 * to specify this, so we fake it by using one of the LINK flags. 500 * If LINK0 is set, we program the PHY to be a master, otherwise 501 * it's a slave. 502 */ 503 if (master) { 504 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 505 gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); 506 } else { 507 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 508 gig | BRGPHY_1000CTL_MSE); 509 } 510 511 brgphy_setmedia_exit: 512 return; 513 } 514 515 /****************************************************************************/ 516 /* Set the media status based on the PHY settings. */ 517 /* IFM_FLAG0 = 0 (RX flow control disabled) | 1 (enabled) */ 518 /* IFM_FLAG1 = 0 (TX flow control disabled) | 1 (enabled) */ 519 /* */ 520 /* Returns: */ 521 /* None */ 522 /****************************************************************************/ 523 static void 524 brgphy_status(struct mii_softc *sc) 525 { 526 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 527 struct mii_data *mii = sc->mii_pdata; 528 int aux, bmcr, bmsr, anar, anlpar, xstat, val; 529 530 531 mii->mii_media_status = IFM_AVALID; 532 mii->mii_media_active = IFM_ETHER; 533 534 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 535 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 536 anar = PHY_READ(sc, BRGPHY_MII_ANAR); 537 anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR); 538 539 /* Loopback is enabled. */ 540 if (bmcr & BRGPHY_BMCR_LOOP) { 541 542 mii->mii_media_active |= IFM_LOOP; 543 } 544 545 /* Autoneg is still in progress. */ 546 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 547 (bmsr & BRGPHY_BMSR_ACOMP) == 0) { 548 /* Erg, still trying, I guess... */ 549 mii->mii_media_active |= IFM_NONE; 550 goto brgphy_status_exit; 551 } 552 553 /* Autoneg is enabled and complete, link should be up. */ 554 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 555 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 556 557 /* If copper link is up, get the negotiated speed/duplex. */ 558 if (aux & BRGPHY_AUXSTS_LINK) { 559 mii->mii_media_status |= IFM_ACTIVE; 560 switch (aux & BRGPHY_AUXSTS_AN_RES) { 561 case BRGPHY_RES_1000FD: 562 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 563 case BRGPHY_RES_1000HD: 564 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 565 case BRGPHY_RES_100FD: 566 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 567 case BRGPHY_RES_100T4: 568 mii->mii_media_active |= IFM_100_T4; break; 569 case BRGPHY_RES_100HD: 570 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 571 case BRGPHY_RES_10FD: 572 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 573 case BRGPHY_RES_10HD: 574 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 575 default: 576 mii->mii_media_active |= IFM_NONE; break; 577 } 578 } 579 } else { 580 /* If serdes link is up, get the negotiated speed/duplex. */ 581 if (bmsr & BRGPHY_BMSR_LINK) { 582 mii->mii_media_status |= IFM_ACTIVE; 583 } 584 585 /* Check the link speed/duplex based on the PHY type. */ 586 if (bsc->serdes_flags & BRGPHY_5706S) { 587 mii->mii_media_active |= IFM_1000_SX; 588 589 /* If autoneg enabled, read negotiated duplex settings */ 590 if (bmcr & BRGPHY_BMCR_AUTOEN) { 591 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 592 if (val & BRGPHY_SERDES_ANAR_FDX) 593 mii->mii_media_active |= IFM_FDX; 594 else 595 mii->mii_media_active |= IFM_HDX; 596 } 597 598 } else if (bsc->serdes_flags & BRGPHY_5708S) { 599 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 600 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 601 602 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 603 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 604 mii->mii_media_active |= IFM_10_FL; break; 605 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 606 mii->mii_media_active |= IFM_100_FX; break; 607 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 608 mii->mii_media_active |= IFM_1000_SX; break; 609 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 610 mii->mii_media_active |= IFM_2500_SX; break; 611 } 612 613 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 614 mii->mii_media_active |= IFM_FDX; 615 else 616 mii->mii_media_active |= IFM_HDX; 617 } 618 } 619 620 #if 0 621 /* Todo: Change bge/bce to use these settings. */ 622 623 /* Fetch flow control settings from the PHY */ 624 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 625 /* Set FLAG0 is RX is enabled and FLAG1 if TX is enabled */ 626 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) { 627 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; 628 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) && 629 (anlpar & BRPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 630 mii->mii_media_active |= IFM_FLAG1; 631 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) && 632 !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) { 633 mii->mii_media_active |= IFM_FLAG0; 634 } 635 } 636 637 /* Todo: Add support for fiber settings too. */ 638 #endif 639 640 641 brgphy_status_exit: 642 return; 643 } 644 645 static void 646 brgphy_mii_phy_auto(struct mii_softc *sc) 647 { 648 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 649 int ktcr = 0; 650 651 brgphy_reset(sc); 652 653 /* Enable flow control in the advertisement register. */ 654 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 655 /* Pause capability advertisement (pause capable & asymmetric) */ 656 PHY_WRITE(sc, BRGPHY_MII_ANAR, 657 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA | 658 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC); 659 } else { 660 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX | 661 BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE); 662 } 663 664 /* Enable speed in the 1000baseT control register */ 665 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 666 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 667 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 668 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 669 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 670 671 /* Start autonegotiation */ 672 PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 673 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 674 675 } 676 677 678 /* Enable loopback to force the link down. */ 679 static void 680 brgphy_enable_loopback(struct mii_softc *sc) 681 { 682 int i; 683 684 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 685 for (i = 0; i < 15000; i++) { 686 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 687 break; 688 DELAY(10); 689 } 690 } 691 692 /* Turn off tap power management on 5401. */ 693 static void 694 bcm5401_load_dspcode(struct mii_softc *sc) 695 { 696 static const struct { 697 int reg; 698 uint16_t val; 699 } dspcode[] = { 700 { BRGPHY_MII_AUXCTL, 0x0c20 }, 701 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 702 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 703 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 704 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 705 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 706 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 707 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 708 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 709 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 710 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 711 { 0, 0 }, 712 }; 713 int i; 714 715 for (i = 0; dspcode[i].reg != 0; i++) 716 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 717 DELAY(40); 718 } 719 720 static void 721 bcm5411_load_dspcode(struct mii_softc *sc) 722 { 723 static const struct { 724 int reg; 725 uint16_t val; 726 } dspcode[] = { 727 { 0x1c, 0x8c23 }, 728 { 0x1c, 0x8ca3 }, 729 { 0x1c, 0x8c23 }, 730 { 0, 0 }, 731 }; 732 int i; 733 734 for (i = 0; dspcode[i].reg != 0; i++) 735 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 736 } 737 738 void 739 bcm54k2_load_dspcode(struct mii_softc *sc) 740 { 741 static const struct { 742 int reg; 743 uint16_t val; 744 } dspcode[] = { 745 { 4, 0x01e1 }, 746 { 9, 0x0300 }, 747 { 0, 0 }, 748 }; 749 int i; 750 751 for (i = 0; dspcode[i].reg != 0; i++) 752 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 753 754 } 755 756 static void 757 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 758 { 759 static const struct { 760 int reg; 761 uint16_t val; 762 } dspcode[] = { 763 { 0x1c, 0x8d68 }, 764 { 0x1c, 0x8d68 }, 765 { 0, 0 }, 766 }; 767 int i; 768 769 for (i = 0; dspcode[i].reg != 0; i++) 770 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 771 } 772 773 static void 774 brgphy_fixup_adc_bug(struct mii_softc *sc) 775 { 776 static const struct { 777 int reg; 778 uint16_t val; 779 } dspcode[] = { 780 { BRGPHY_MII_AUXCTL, 0x0c00 }, 781 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 782 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 783 { 0, 0 }, 784 }; 785 int i; 786 787 for (i = 0; dspcode[i].reg != 0; i++) 788 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 789 } 790 791 static void 792 brgphy_fixup_adjust_trim(struct mii_softc *sc) 793 { 794 static const struct { 795 int reg; 796 uint16_t val; 797 } dspcode[] = { 798 { BRGPHY_MII_AUXCTL, 0x0c00 }, 799 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 800 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 801 { BRGPHY_MII_TEST1, 0x0014 }, 802 { BRGPHY_MII_AUXCTL, 0x0400 }, 803 { 0, 0 }, 804 }; 805 int i; 806 807 for (i = 0; dspcode[i].reg != 0; i++) 808 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 809 } 810 811 static void 812 brgphy_fixup_ber_bug(struct mii_softc *sc) 813 { 814 static const struct { 815 int reg; 816 uint16_t val; 817 } dspcode[] = { 818 { BRGPHY_MII_AUXCTL, 0x0c00 }, 819 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 820 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 821 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 822 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 823 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 824 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 825 { BRGPHY_MII_AUXCTL, 0x0400 }, 826 { 0, 0 }, 827 }; 828 int i; 829 830 for (i = 0; dspcode[i].reg != 0; i++) 831 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 832 } 833 834 static void 835 brgphy_fixup_crc_bug(struct mii_softc *sc) 836 { 837 static const struct { 838 int reg; 839 uint16_t val; 840 } dspcode[] = { 841 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 842 { 0x1c, 0x8c68 }, 843 { 0x1c, 0x8d68 }, 844 { 0x1c, 0x8c68 }, 845 { 0, 0 }, 846 }; 847 int i; 848 849 for (i = 0; dspcode[i].reg != 0; i++) 850 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 851 } 852 853 static void 854 brgphy_fixup_jitter_bug(struct mii_softc *sc) 855 { 856 static const struct { 857 int reg; 858 uint16_t val; 859 } dspcode[] = { 860 { BRGPHY_MII_AUXCTL, 0x0c00 }, 861 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 862 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 863 { BRGPHY_MII_AUXCTL, 0x0400 }, 864 { 0, 0 }, 865 }; 866 int i; 867 868 for (i = 0; dspcode[i].reg != 0; i++) 869 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 870 } 871 872 873 static void 874 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 875 { 876 uint32_t val; 877 878 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 879 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 880 val &= ~(1 << 8); 881 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 882 883 } 884 885 886 static void 887 brgphy_ethernet_wirespeed(struct mii_softc *sc) 888 { 889 uint32_t val; 890 891 /* Enable Ethernet@WireSpeed. */ 892 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 893 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 894 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 895 } 896 897 898 static void 899 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 900 { 901 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 902 uint32_t val; 903 904 /* Set or clear jumbo frame settings in the PHY. */ 905 if (mtu > ETHER_MAX_LEN) { 906 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 907 /* BCM5401 PHY cannot read-modify-write. */ 908 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 909 } else { 910 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 911 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 912 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 913 val | BRGPHY_AUXCTL_LONG_PKT); 914 } 915 916 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 917 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 918 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 919 } else { 920 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 921 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 922 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 923 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 924 925 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 926 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 927 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 928 } 929 } 930 931 static void 932 brgphy_reset(struct mii_softc *sc) 933 { 934 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 935 struct bge_softc *bge_sc = NULL; 936 struct bce_softc *bce_sc = NULL; 937 struct ifnet *ifp; 938 939 /* Perform a standard PHY reset. */ 940 mii_phy_reset(sc); 941 942 /* Handle any PHY specific procedures following the reset. */ 943 switch (bsc->mii_oui) { 944 case MII_OUI_BROADCOM: 945 break; 946 case MII_OUI_xxBROADCOM: 947 switch (bsc->mii_model) { 948 case MII_MODEL_xxBROADCOM_BCM5400: 949 bcm5401_load_dspcode(sc); 950 break; 951 case MII_MODEL_xxBROADCOM_BCM5401: 952 if (bsc->mii_rev == 1 || bsc->mii_rev == 3) 953 bcm5401_load_dspcode(sc); 954 break; 955 case MII_MODEL_xxBROADCOM_BCM5411: 956 bcm5411_load_dspcode(sc); 957 break; 958 case MII_MODEL_xxBROADCOM_BCM54K2: 959 bcm54k2_load_dspcode(sc); 960 break; 961 } 962 break; 963 case MII_OUI_xxBROADCOM_ALT1: 964 break; 965 } 966 967 ifp = sc->mii_pdata->mii_ifp; 968 969 /* Find the driver associated with this PHY. */ 970 if (strcmp(ifp->if_dname, "bge") == 0) { 971 bge_sc = ifp->if_softc; 972 } else if (strcmp(ifp->if_dname, "bce") == 0) { 973 bce_sc = ifp->if_softc; 974 } 975 976 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 977 if (bge_sc) { 978 /* Fix up various bugs */ 979 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) 980 brgphy_fixup_5704_a0_bug(sc); 981 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) 982 brgphy_fixup_adc_bug(sc); 983 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) 984 brgphy_fixup_adjust_trim(sc); 985 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) 986 brgphy_fixup_ber_bug(sc); 987 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) 988 brgphy_fixup_crc_bug(sc); 989 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) 990 brgphy_fixup_jitter_bug(sc); 991 992 brgphy_jumbo_settings(sc, ifp->if_mtu); 993 994 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED) 995 brgphy_ethernet_wirespeed(sc); 996 997 /* Enable Link LED on Dell boxes */ 998 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { 999 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 1000 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 1001 ~BRGPHY_PHY_EXTCTL_3_LED); 1002 } 1003 1004 /* Adjust output voltage (From Linux driver) */ 1005 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 1006 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 1007 1008 /* Handle any bce (NetXtreme II) workarounds. */ 1009 } else if (bce_sc) { 1010 1011 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 1012 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1013 1014 /* Store autoneg capabilities/results in digital block (Page 0) */ 1015 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 1016 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 1017 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 1018 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 1019 1020 /* Enable fiber mode and autodetection */ 1021 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 1022 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 1023 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 1024 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 1025 1026 /* Enable parallel detection */ 1027 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1028 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1029 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1030 1031 /* Advertise 2.5G support through next page during autoneg */ 1032 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1033 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1034 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1035 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1036 1037 /* Increase TX signal amplitude */ 1038 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1039 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1040 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1041 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1042 BRGPHY_5708S_TX_MISC_PG5); 1043 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1044 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1045 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1046 BRGPHY_5708S_DIG_PG0); 1047 } 1048 1049 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1050 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1051 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1052 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1053 BRGPHY_5708S_TX_MISC_PG5); 1054 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1055 bce_sc->bce_port_hw_cfg & 1056 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1057 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1058 BRGPHY_5708S_DIG_PG0); 1059 } 1060 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1061 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1062 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1063 brgphy_fixup_disable_early_dac(sc); 1064 1065 brgphy_jumbo_settings(sc, ifp->if_mtu); 1066 brgphy_ethernet_wirespeed(sc); 1067 } else { 1068 brgphy_fixup_ber_bug(sc); 1069 brgphy_jumbo_settings(sc, ifp->if_mtu); 1070 brgphy_ethernet_wirespeed(sc); 1071 } 1072 1073 } 1074 } 1075 1076