1 /*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <net/if.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include "miidevs.h" 54 55 #include <dev/mii/brgphyreg.h> 56 #include <net/if_arp.h> 57 #include <machine/bus.h> 58 #include <dev/bge/if_bgereg.h> 59 #include <dev/bce/if_bcereg.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 #include "miibus_if.h" 65 66 static int brgphy_probe(device_t); 67 static int brgphy_attach(device_t); 68 69 struct brgphy_softc { 70 struct mii_softc mii_sc; 71 int serdes_flags; /* Keeps track of the serdes type used */ 72 #define BRGPHY_5706S 0x0001 73 #define BRGPHY_5708S 0x0002 74 #define BRGPHY_NOANWAIT 0x0004 75 #define BRGPHY_5709S 0x0008 76 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 77 }; 78 79 static device_method_t brgphy_methods[] = { 80 /* device interface */ 81 DEVMETHOD(device_probe, brgphy_probe), 82 DEVMETHOD(device_attach, brgphy_attach), 83 DEVMETHOD(device_detach, mii_phy_detach), 84 DEVMETHOD(device_shutdown, bus_generic_shutdown), 85 { 0, 0 } 86 }; 87 88 static devclass_t brgphy_devclass; 89 90 static driver_t brgphy_driver = { 91 "brgphy", 92 brgphy_methods, 93 sizeof(struct brgphy_softc) 94 }; 95 96 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 97 98 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 99 static void brgphy_setmedia(struct mii_softc *, int); 100 static void brgphy_status(struct mii_softc *); 101 static void brgphy_mii_phy_auto(struct mii_softc *, int); 102 static void brgphy_reset(struct mii_softc *); 103 static void brgphy_enable_loopback(struct mii_softc *); 104 static void bcm5401_load_dspcode(struct mii_softc *); 105 static void bcm5411_load_dspcode(struct mii_softc *); 106 static void bcm54k2_load_dspcode(struct mii_softc *); 107 static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 108 static void brgphy_fixup_adc_bug(struct mii_softc *); 109 static void brgphy_fixup_adjust_trim(struct mii_softc *); 110 static void brgphy_fixup_ber_bug(struct mii_softc *); 111 static void brgphy_fixup_crc_bug(struct mii_softc *); 112 static void brgphy_fixup_jitter_bug(struct mii_softc *); 113 static void brgphy_ethernet_wirespeed(struct mii_softc *); 114 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 115 116 static const struct mii_phydesc brgphys[] = { 117 MII_PHY_DESC(BROADCOM, BCM5400), 118 MII_PHY_DESC(BROADCOM, BCM5401), 119 MII_PHY_DESC(BROADCOM, BCM5411), 120 MII_PHY_DESC(BROADCOM, BCM54K2), 121 MII_PHY_DESC(BROADCOM, BCM5701), 122 MII_PHY_DESC(BROADCOM, BCM5703), 123 MII_PHY_DESC(BROADCOM, BCM5704), 124 MII_PHY_DESC(BROADCOM, BCM5705), 125 MII_PHY_DESC(BROADCOM, BCM5706), 126 MII_PHY_DESC(BROADCOM, BCM5714), 127 MII_PHY_DESC(BROADCOM, BCM5421), 128 MII_PHY_DESC(BROADCOM, BCM5750), 129 MII_PHY_DESC(BROADCOM, BCM5752), 130 MII_PHY_DESC(BROADCOM, BCM5780), 131 MII_PHY_DESC(BROADCOM, BCM5708C), 132 MII_PHY_DESC(BROADCOM2, BCM5482), 133 MII_PHY_DESC(BROADCOM2, BCM5708S), 134 MII_PHY_DESC(BROADCOM2, BCM5709C), 135 MII_PHY_DESC(BROADCOM2, BCM5709S), 136 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 137 MII_PHY_DESC(BROADCOM2, BCM5722), 138 MII_PHY_DESC(BROADCOM2, BCM5755), 139 MII_PHY_DESC(BROADCOM2, BCM5754), 140 MII_PHY_DESC(BROADCOM2, BCM5761), 141 MII_PHY_DESC(BROADCOM2, BCM5784), 142 MII_PHY_DESC(BROADCOM3, BCM5717C), 143 MII_PHY_DESC(BROADCOM3, BCM5719C), 144 MII_PHY_DESC(BROADCOM3, BCM5720C), 145 MII_PHY_DESC(BROADCOM3, BCM57765), 146 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 147 MII_PHY_END 148 }; 149 150 static const struct mii_phy_funcs brgphy_funcs = { 151 brgphy_service, 152 brgphy_status, 153 brgphy_reset 154 }; 155 156 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 157 #define HS21_BCM_CHIPID 0x57081021 158 159 static int 160 detect_hs21(struct bce_softc *bce_sc) 161 { 162 char *sysenv; 163 int found; 164 165 found = 0; 166 if (bce_sc->bce_chipid == HS21_BCM_CHIPID) { 167 sysenv = getenv("smbios.system.product"); 168 if (sysenv != NULL) { 169 if (strncmp(sysenv, HS21_PRODUCT_ID, 170 strlen(HS21_PRODUCT_ID)) == 0) 171 found = 1; 172 freeenv(sysenv); 173 } 174 } 175 return (found); 176 } 177 178 /* Search for our PHY in the list of known PHYs */ 179 static int 180 brgphy_probe(device_t dev) 181 { 182 183 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 184 } 185 186 /* Attach the PHY to the MII bus */ 187 static int 188 brgphy_attach(device_t dev) 189 { 190 struct brgphy_softc *bsc; 191 struct bge_softc *bge_sc = NULL; 192 struct bce_softc *bce_sc = NULL; 193 struct mii_softc *sc; 194 struct ifnet *ifp; 195 196 bsc = device_get_softc(dev); 197 sc = &bsc->mii_sc; 198 199 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 200 &brgphy_funcs, 0); 201 202 bsc->serdes_flags = 0; 203 204 /* Handle any special cases based on the PHY ID */ 205 switch (sc->mii_mpd_oui) { 206 case MII_OUI_BROADCOM: 207 switch (sc->mii_mpd_model) { 208 case MII_MODEL_BROADCOM_BCM5706: 209 case MII_MODEL_BROADCOM_BCM5714: 210 /* 211 * The 5464 PHY used in the 5706 supports both copper 212 * and fiber interfaces over GMII. Need to check the 213 * shadow registers to see which mode is actually 214 * in effect, and therefore whether we have 5706C or 215 * 5706S. 216 */ 217 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 218 BRGPHY_SHADOW_1C_MODE_CTRL); 219 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 220 BRGPHY_SHADOW_1C_ENA_1000X) { 221 bsc->serdes_flags |= BRGPHY_5706S; 222 sc->mii_flags |= MIIF_HAVEFIBER; 223 } 224 break; 225 } break; 226 case MII_OUI_BROADCOM2: 227 switch (sc->mii_mpd_model) { 228 case MII_MODEL_BROADCOM2_BCM5708S: 229 bsc->serdes_flags |= BRGPHY_5708S; 230 sc->mii_flags |= MIIF_HAVEFIBER; 231 break; 232 case MII_MODEL_BROADCOM2_BCM5709S: 233 bsc->serdes_flags |= BRGPHY_5709S; 234 sc->mii_flags |= MIIF_HAVEFIBER; 235 break; 236 } 237 break; 238 } 239 240 ifp = sc->mii_pdata->mii_ifp; 241 242 /* Find the MAC driver associated with this PHY. */ 243 if (strcmp(ifp->if_dname, "bge") == 0) { 244 bge_sc = ifp->if_softc; 245 } else if (strcmp(ifp->if_dname, "bce") == 0) { 246 bce_sc = ifp->if_softc; 247 } 248 249 PHY_RESET(sc); 250 251 /* Read the PHY's capabilities. */ 252 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 253 if (sc->mii_capabilities & BMSR_EXTSTAT) 254 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 255 device_printf(dev, " "); 256 257 #define ADD(m, c) ifmedia_add(&sc->mii_pdata->mii_media, (m), (c), NULL) 258 259 /* Add the supported media types */ 260 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 261 mii_phy_add_media(sc); 262 printf("\n"); 263 } else { 264 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 265 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 266 BRGPHY_S1000 | BRGPHY_BMCR_FDX); 267 printf("1000baseSX-FDX, "); 268 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ 269 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { 270 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); 271 printf("2500baseSX-FDX, "); 272 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 273 (detect_hs21(bce_sc) != 0)) { 274 /* 275 * There appears to be certain silicon revision 276 * in IBM HS21 blades that is having issues with 277 * this driver wating for the auto-negotiation to 278 * complete. This happens with a specific chip id 279 * only and when the 1000baseSX-FDX is the only 280 * mode. Workaround this issue since it's unlikely 281 * to be ever addressed. 282 */ 283 printf("auto-neg workaround, "); 284 bsc->serdes_flags |= BRGPHY_NOANWAIT; 285 } 286 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 287 printf("auto\n"); 288 } 289 290 #undef ADD 291 MIIBUS_MEDIAINIT(sc->mii_dev); 292 return (0); 293 } 294 295 static int 296 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 297 { 298 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 299 int val; 300 301 switch (cmd) { 302 case MII_POLLSTAT: 303 break; 304 case MII_MEDIACHG: 305 /* If the interface is not up, don't do anything. */ 306 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 307 break; 308 309 /* Todo: Why is this here? Is it really needed? */ 310 PHY_RESET(sc); /* XXX hardware bug work-around */ 311 312 switch (IFM_SUBTYPE(ife->ifm_media)) { 313 case IFM_AUTO: 314 brgphy_mii_phy_auto(sc, ife->ifm_media); 315 break; 316 case IFM_2500_SX: 317 case IFM_1000_SX: 318 case IFM_1000_T: 319 case IFM_100_TX: 320 case IFM_10_T: 321 brgphy_setmedia(sc, ife->ifm_media); 322 break; 323 default: 324 return (EINVAL); 325 } 326 break; 327 case MII_TICK: 328 /* Bail if the interface isn't up. */ 329 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 330 return (0); 331 332 333 /* Bail if autoneg isn't in process. */ 334 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 335 sc->mii_ticks = 0; 336 break; 337 } 338 339 /* 340 * Check to see if we have link. If we do, we don't 341 * need to restart the autonegotiation process. 342 */ 343 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 344 if (val & BMSR_LINK) { 345 sc->mii_ticks = 0; /* Reset autoneg timer. */ 346 break; 347 } 348 349 /* Announce link loss right after it happens. */ 350 if (sc->mii_ticks++ == 0) 351 break; 352 353 /* Only retry autonegotiation every mii_anegticks seconds. */ 354 if (sc->mii_ticks <= sc->mii_anegticks) 355 break; 356 357 358 /* Retry autonegotiation */ 359 sc->mii_ticks = 0; 360 brgphy_mii_phy_auto(sc, ife->ifm_media); 361 break; 362 } 363 364 /* Update the media status. */ 365 PHY_STATUS(sc); 366 367 /* 368 * Callback if something changed. Note that we need to poke 369 * the DSP on the Broadcom PHYs if the media changes. 370 */ 371 if (sc->mii_media_active != mii->mii_media_active || 372 sc->mii_media_status != mii->mii_media_status || 373 cmd == MII_MEDIACHG) { 374 switch (sc->mii_mpd_oui) { 375 case MII_OUI_BROADCOM: 376 switch (sc->mii_mpd_model) { 377 case MII_MODEL_BROADCOM_BCM5400: 378 bcm5401_load_dspcode(sc); 379 break; 380 case MII_MODEL_BROADCOM_BCM5401: 381 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 382 bcm5401_load_dspcode(sc); 383 break; 384 case MII_MODEL_BROADCOM_BCM5411: 385 bcm5411_load_dspcode(sc); 386 break; 387 case MII_MODEL_BROADCOM_BCM54K2: 388 bcm54k2_load_dspcode(sc); 389 break; 390 } 391 break; 392 } 393 } 394 mii_phy_update(sc, cmd); 395 return (0); 396 } 397 398 /****************************************************************************/ 399 /* Sets the PHY link speed. */ 400 /* */ 401 /* Returns: */ 402 /* None */ 403 /****************************************************************************/ 404 static void 405 brgphy_setmedia(struct mii_softc *sc, int media) 406 { 407 int bmcr = 0, gig; 408 409 switch (IFM_SUBTYPE(media)) { 410 case IFM_2500_SX: 411 break; 412 case IFM_1000_SX: 413 case IFM_1000_T: 414 bmcr = BRGPHY_S1000; 415 break; 416 case IFM_100_TX: 417 bmcr = BRGPHY_S100; 418 break; 419 case IFM_10_T: 420 default: 421 bmcr = BRGPHY_S10; 422 break; 423 } 424 425 if ((media & IFM_FDX) != 0) { 426 bmcr |= BRGPHY_BMCR_FDX; 427 gig = BRGPHY_1000CTL_AFD; 428 } else { 429 gig = BRGPHY_1000CTL_AHD; 430 } 431 432 /* Force loopback to disconnect PHY from Ethernet medium. */ 433 brgphy_enable_loopback(sc); 434 435 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 436 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 437 438 if (IFM_SUBTYPE(media) != IFM_1000_T && 439 IFM_SUBTYPE(media) != IFM_1000_SX) { 440 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 441 return; 442 } 443 444 if (IFM_SUBTYPE(media) == IFM_1000_T) { 445 gig |= BRGPHY_1000CTL_MSE; 446 if ((media & IFM_ETH_MASTER) != 0) 447 gig |= BRGPHY_1000CTL_MSC; 448 } 449 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 450 PHY_WRITE(sc, BRGPHY_MII_BMCR, 451 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 452 } 453 454 /****************************************************************************/ 455 /* Set the media status based on the PHY settings. */ 456 /* */ 457 /* Returns: */ 458 /* None */ 459 /****************************************************************************/ 460 static void 461 brgphy_status(struct mii_softc *sc) 462 { 463 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 464 struct mii_data *mii = sc->mii_pdata; 465 int aux, bmcr, bmsr, val, xstat; 466 u_int flowstat; 467 468 mii->mii_media_status = IFM_AVALID; 469 mii->mii_media_active = IFM_ETHER; 470 471 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 472 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 473 474 if (bmcr & BRGPHY_BMCR_LOOP) { 475 mii->mii_media_active |= IFM_LOOP; 476 } 477 478 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 479 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 480 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 481 /* Erg, still trying, I guess... */ 482 mii->mii_media_active |= IFM_NONE; 483 return; 484 } 485 486 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 487 /* 488 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 489 * wedges at least the PHY of BCM5704 (but not others). 490 */ 491 flowstat = mii_phy_flowstatus(sc); 492 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 493 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 494 495 /* If copper link is up, get the negotiated speed/duplex. */ 496 if (aux & BRGPHY_AUXSTS_LINK) { 497 mii->mii_media_status |= IFM_ACTIVE; 498 switch (aux & BRGPHY_AUXSTS_AN_RES) { 499 case BRGPHY_RES_1000FD: 500 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 501 case BRGPHY_RES_1000HD: 502 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 503 case BRGPHY_RES_100FD: 504 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 505 case BRGPHY_RES_100T4: 506 mii->mii_media_active |= IFM_100_T4; break; 507 case BRGPHY_RES_100HD: 508 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 509 case BRGPHY_RES_10FD: 510 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 511 case BRGPHY_RES_10HD: 512 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 513 default: 514 mii->mii_media_active |= IFM_NONE; break; 515 } 516 517 if ((mii->mii_media_active & IFM_FDX) != 0) 518 mii->mii_media_active |= flowstat; 519 520 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 521 (xstat & BRGPHY_1000STS_MSR) != 0) 522 mii->mii_media_active |= IFM_ETH_MASTER; 523 } 524 } else { 525 /* Todo: Add support for flow control. */ 526 /* If serdes link is up, get the negotiated speed/duplex. */ 527 if (bmsr & BRGPHY_BMSR_LINK) { 528 mii->mii_media_status |= IFM_ACTIVE; 529 } 530 531 /* Check the link speed/duplex based on the PHY type. */ 532 if (bsc->serdes_flags & BRGPHY_5706S) { 533 mii->mii_media_active |= IFM_1000_SX; 534 535 /* If autoneg enabled, read negotiated duplex settings */ 536 if (bmcr & BRGPHY_BMCR_AUTOEN) { 537 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 538 if (val & BRGPHY_SERDES_ANAR_FDX) 539 mii->mii_media_active |= IFM_FDX; 540 else 541 mii->mii_media_active |= IFM_HDX; 542 } 543 } else if (bsc->serdes_flags & BRGPHY_5708S) { 544 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 545 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 546 547 /* Check for MRBE auto-negotiated speed results. */ 548 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 549 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 550 mii->mii_media_active |= IFM_10_FL; break; 551 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 552 mii->mii_media_active |= IFM_100_FX; break; 553 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 554 mii->mii_media_active |= IFM_1000_SX; break; 555 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 556 mii->mii_media_active |= IFM_2500_SX; break; 557 } 558 559 /* Check for MRBE auto-negotiated duplex results. */ 560 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 561 mii->mii_media_active |= IFM_FDX; 562 else 563 mii->mii_media_active |= IFM_HDX; 564 } else if (bsc->serdes_flags & BRGPHY_5709S) { 565 /* Select GP Status Block of the AN MMD, get autoneg results. */ 566 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 567 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 568 569 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 570 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 571 572 /* Check for MRBE auto-negotiated speed results. */ 573 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 574 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 575 mii->mii_media_active |= IFM_10_FL; break; 576 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 577 mii->mii_media_active |= IFM_100_FX; break; 578 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 579 mii->mii_media_active |= IFM_1000_SX; break; 580 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 581 mii->mii_media_active |= IFM_2500_SX; break; 582 } 583 584 /* Check for MRBE auto-negotiated duplex results. */ 585 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 586 mii->mii_media_active |= IFM_FDX; 587 else 588 mii->mii_media_active |= IFM_HDX; 589 } 590 } 591 } 592 593 static void 594 brgphy_mii_phy_auto(struct mii_softc *sc, int media) 595 { 596 int anar, ktcr = 0; 597 598 PHY_RESET(sc); 599 600 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 601 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 602 if ((media & IFM_FLOW) != 0 || 603 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 604 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 605 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 606 } else { 607 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 608 if ((media & IFM_FLOW) != 0 || 609 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 610 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 611 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 612 } 613 614 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 615 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 616 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 617 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 618 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 619 620 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 621 BRGPHY_BMCR_STARTNEG); 622 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 623 } 624 625 /* Enable loopback to force the link down. */ 626 static void 627 brgphy_enable_loopback(struct mii_softc *sc) 628 { 629 int i; 630 631 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 632 for (i = 0; i < 15000; i++) { 633 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 634 break; 635 DELAY(10); 636 } 637 } 638 639 /* Turn off tap power management on 5401. */ 640 static void 641 bcm5401_load_dspcode(struct mii_softc *sc) 642 { 643 static const struct { 644 int reg; 645 uint16_t val; 646 } dspcode[] = { 647 { BRGPHY_MII_AUXCTL, 0x0c20 }, 648 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 649 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 650 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 651 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 652 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 653 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 654 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 655 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 656 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 657 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 658 { 0, 0 }, 659 }; 660 int i; 661 662 for (i = 0; dspcode[i].reg != 0; i++) 663 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 664 DELAY(40); 665 } 666 667 static void 668 bcm5411_load_dspcode(struct mii_softc *sc) 669 { 670 static const struct { 671 int reg; 672 uint16_t val; 673 } dspcode[] = { 674 { 0x1c, 0x8c23 }, 675 { 0x1c, 0x8ca3 }, 676 { 0x1c, 0x8c23 }, 677 { 0, 0 }, 678 }; 679 int i; 680 681 for (i = 0; dspcode[i].reg != 0; i++) 682 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 683 } 684 685 void 686 bcm54k2_load_dspcode(struct mii_softc *sc) 687 { 688 static const struct { 689 int reg; 690 uint16_t val; 691 } dspcode[] = { 692 { 4, 0x01e1 }, 693 { 9, 0x0300 }, 694 { 0, 0 }, 695 }; 696 int i; 697 698 for (i = 0; dspcode[i].reg != 0; i++) 699 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 700 701 } 702 703 static void 704 brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 705 { 706 static const struct { 707 int reg; 708 uint16_t val; 709 } dspcode[] = { 710 { 0x1c, 0x8d68 }, 711 { 0x1c, 0x8d68 }, 712 { 0, 0 }, 713 }; 714 int i; 715 716 for (i = 0; dspcode[i].reg != 0; i++) 717 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 718 } 719 720 static void 721 brgphy_fixup_adc_bug(struct mii_softc *sc) 722 { 723 static const struct { 724 int reg; 725 uint16_t val; 726 } dspcode[] = { 727 { BRGPHY_MII_AUXCTL, 0x0c00 }, 728 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 729 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 730 { 0, 0 }, 731 }; 732 int i; 733 734 for (i = 0; dspcode[i].reg != 0; i++) 735 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 736 } 737 738 static void 739 brgphy_fixup_adjust_trim(struct mii_softc *sc) 740 { 741 static const struct { 742 int reg; 743 uint16_t val; 744 } dspcode[] = { 745 { BRGPHY_MII_AUXCTL, 0x0c00 }, 746 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 747 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 748 { BRGPHY_MII_TEST1, 0x0014 }, 749 { BRGPHY_MII_AUXCTL, 0x0400 }, 750 { 0, 0 }, 751 }; 752 int i; 753 754 for (i = 0; dspcode[i].reg != 0; i++) 755 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 756 } 757 758 static void 759 brgphy_fixup_ber_bug(struct mii_softc *sc) 760 { 761 static const struct { 762 int reg; 763 uint16_t val; 764 } dspcode[] = { 765 { BRGPHY_MII_AUXCTL, 0x0c00 }, 766 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 767 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 768 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 769 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 770 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 771 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 772 { BRGPHY_MII_AUXCTL, 0x0400 }, 773 { 0, 0 }, 774 }; 775 int i; 776 777 for (i = 0; dspcode[i].reg != 0; i++) 778 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 779 } 780 781 static void 782 brgphy_fixup_crc_bug(struct mii_softc *sc) 783 { 784 static const struct { 785 int reg; 786 uint16_t val; 787 } dspcode[] = { 788 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 789 { 0x1c, 0x8c68 }, 790 { 0x1c, 0x8d68 }, 791 { 0x1c, 0x8c68 }, 792 { 0, 0 }, 793 }; 794 int i; 795 796 for (i = 0; dspcode[i].reg != 0; i++) 797 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 798 } 799 800 static void 801 brgphy_fixup_jitter_bug(struct mii_softc *sc) 802 { 803 static const struct { 804 int reg; 805 uint16_t val; 806 } dspcode[] = { 807 { BRGPHY_MII_AUXCTL, 0x0c00 }, 808 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 809 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 810 { BRGPHY_MII_AUXCTL, 0x0400 }, 811 { 0, 0 }, 812 }; 813 int i; 814 815 for (i = 0; dspcode[i].reg != 0; i++) 816 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 817 } 818 819 static void 820 brgphy_fixup_disable_early_dac(struct mii_softc *sc) 821 { 822 uint32_t val; 823 824 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 825 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 826 val &= ~(1 << 8); 827 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 828 829 } 830 831 static void 832 brgphy_ethernet_wirespeed(struct mii_softc *sc) 833 { 834 uint32_t val; 835 836 /* Enable Ethernet@WireSpeed. */ 837 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 838 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 839 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 840 } 841 842 static void 843 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 844 { 845 uint32_t val; 846 847 /* Set or clear jumbo frame settings in the PHY. */ 848 if (mtu > ETHER_MAX_LEN) { 849 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 850 /* BCM5401 PHY cannot read-modify-write. */ 851 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 852 } else { 853 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 854 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 855 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 856 val | BRGPHY_AUXCTL_LONG_PKT); 857 } 858 859 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 860 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 861 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 862 } else { 863 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 864 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 865 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 866 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 867 868 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 869 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 870 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 871 } 872 } 873 874 static void 875 brgphy_reset(struct mii_softc *sc) 876 { 877 struct bge_softc *bge_sc = NULL; 878 struct bce_softc *bce_sc = NULL; 879 struct ifnet *ifp; 880 int i, val; 881 882 /* 883 * Perform a reset. Note that at least some Broadcom PHYs default to 884 * being powered down as well as isolated after a reset but don't work 885 * if one or both of these bits are cleared. However, they just work 886 * fine if both bits remain set, so we don't use mii_phy_reset() here. 887 */ 888 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 889 890 /* Wait 100ms for it to complete. */ 891 for (i = 0; i < 100; i++) { 892 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 893 break; 894 DELAY(1000); 895 } 896 897 /* Handle any PHY specific procedures following the reset. */ 898 switch (sc->mii_mpd_oui) { 899 case MII_OUI_BROADCOM: 900 switch (sc->mii_mpd_model) { 901 case MII_MODEL_BROADCOM_BCM5400: 902 bcm5401_load_dspcode(sc); 903 break; 904 case MII_MODEL_BROADCOM_BCM5401: 905 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 906 bcm5401_load_dspcode(sc); 907 break; 908 case MII_MODEL_BROADCOM_BCM5411: 909 bcm5411_load_dspcode(sc); 910 break; 911 case MII_MODEL_BROADCOM_BCM54K2: 912 bcm54k2_load_dspcode(sc); 913 break; 914 } 915 break; 916 } 917 918 ifp = sc->mii_pdata->mii_ifp; 919 920 /* Find the driver associated with this PHY. */ 921 if (strcmp(ifp->if_dname, "bge") == 0) { 922 bge_sc = ifp->if_softc; 923 } else if (strcmp(ifp->if_dname, "bce") == 0) { 924 bce_sc = ifp->if_softc; 925 } 926 927 if (bge_sc) { 928 /* Fix up various bugs */ 929 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 930 brgphy_fixup_5704_a0_bug(sc); 931 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 932 brgphy_fixup_adc_bug(sc); 933 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 934 brgphy_fixup_adjust_trim(sc); 935 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 936 brgphy_fixup_ber_bug(sc); 937 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 938 brgphy_fixup_crc_bug(sc); 939 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 940 brgphy_fixup_jitter_bug(sc); 941 942 brgphy_jumbo_settings(sc, ifp->if_mtu); 943 944 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 945 brgphy_ethernet_wirespeed(sc); 946 947 /* Enable Link LED on Dell boxes */ 948 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 949 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 950 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 951 ~BRGPHY_PHY_EXTCTL_3_LED); 952 } 953 954 /* Adjust output voltage (From Linux driver) */ 955 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 956 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 957 } else if (bce_sc) { 958 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 959 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 960 961 /* Store autoneg capabilities/results in digital block (Page 0) */ 962 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 963 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 964 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 965 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 966 967 /* Enable fiber mode and autodetection */ 968 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 969 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 970 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 971 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 972 973 /* Enable parallel detection */ 974 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 975 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 976 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 977 978 /* Advertise 2.5G support through next page during autoneg */ 979 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 980 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 981 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 982 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 983 984 /* Increase TX signal amplitude */ 985 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 986 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 987 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 988 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 989 BRGPHY_5708S_TX_MISC_PG5); 990 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 991 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 992 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 993 BRGPHY_5708S_DIG_PG0); 994 } 995 996 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 997 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 998 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 999 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1000 BRGPHY_5708S_TX_MISC_PG5); 1001 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1002 bce_sc->bce_port_hw_cfg & 1003 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1004 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1005 BRGPHY_5708S_DIG_PG0); 1006 } 1007 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1008 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1009 1010 /* Select the SerDes Digital block of the AN MMD. */ 1011 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1012 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1013 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1014 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1015 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1016 1017 /* Select the Over 1G block of the AN MMD. */ 1018 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1019 1020 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1021 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1022 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1023 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1024 else 1025 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1026 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1027 1028 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1029 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1030 1031 /* Enable MRBE speed autoneg. */ 1032 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1033 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1034 BRGPHY_MRBE_MSG_PG5_NP_T2; 1035 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1036 1037 /* Select the Clause 73 User B0 block of the AN MMD. */ 1038 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1039 1040 /* Enable MRBE speed autoneg. */ 1041 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1042 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1043 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1044 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1045 1046 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1047 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1048 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1049 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1050 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1051 brgphy_fixup_disable_early_dac(sc); 1052 1053 brgphy_jumbo_settings(sc, ifp->if_mtu); 1054 brgphy_ethernet_wirespeed(sc); 1055 } else { 1056 brgphy_fixup_ber_bug(sc); 1057 brgphy_jumbo_settings(sc, ifp->if_mtu); 1058 brgphy_ethernet_wirespeed(sc); 1059 } 1060 } 1061 } 1062