1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2000
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 /*
37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/bus.h>
46 #include <sys/taskqueue.h>
47
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/ethernet.h>
51 #include <net/if_media.h>
52
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
55 #include "miidevs.h"
56
57 #include <dev/mii/brgphyreg.h>
58 #include <net/if_arp.h>
59 #include <machine/bus.h>
60 #include <dev/bge/if_bgereg.h>
61 #include <dev/bce/if_bcereg.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65
66 #include "miibus_if.h"
67
68 static int brgphy_probe(device_t);
69 static int brgphy_attach(device_t);
70
71 struct brgphy_softc {
72 struct mii_softc mii_sc;
73 int serdes_flags; /* Keeps track of the serdes type used */
74 #define BRGPHY_5706S 0x0001
75 #define BRGPHY_5708S 0x0002
76 #define BRGPHY_NOANWAIT 0x0004
77 #define BRGPHY_5709S 0x0008
78 int bce_phy_flags; /* PHY flags transferred from the MAC driver */
79 };
80
81 static device_method_t brgphy_methods[] = {
82 /* device interface */
83 DEVMETHOD(device_probe, brgphy_probe),
84 DEVMETHOD(device_attach, brgphy_attach),
85 DEVMETHOD(device_detach, mii_phy_detach),
86 DEVMETHOD(device_shutdown, bus_generic_shutdown),
87 DEVMETHOD_END
88 };
89
90 static driver_t brgphy_driver = {
91 "brgphy",
92 brgphy_methods,
93 sizeof(struct brgphy_softc)
94 };
95
96 DRIVER_MODULE(brgphy, miibus, brgphy_driver, 0, 0);
97
98 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
99 static void brgphy_setmedia(struct mii_softc *, int);
100 static void brgphy_status(struct mii_softc *);
101 static void brgphy_mii_phy_auto(struct mii_softc *, int);
102 static void brgphy_reset(struct mii_softc *);
103 static void brgphy_enable_loopback(struct mii_softc *);
104 static void bcm5401_load_dspcode(struct mii_softc *);
105 static void bcm5411_load_dspcode(struct mii_softc *);
106 static void bcm54k2_load_dspcode(struct mii_softc *);
107 static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
108 static void brgphy_fixup_adc_bug(struct mii_softc *);
109 static void brgphy_fixup_adjust_trim(struct mii_softc *);
110 static void brgphy_fixup_ber_bug(struct mii_softc *);
111 static void brgphy_fixup_crc_bug(struct mii_softc *);
112 static void brgphy_fixup_jitter_bug(struct mii_softc *);
113 static void brgphy_ethernet_wirespeed(struct mii_softc *);
114 static void brgphy_bcm54xx_clock_delay(struct mii_softc *);
115 static void brgphy_jumbo_settings(struct mii_softc *, u_long);
116
117 static const struct mii_phydesc brgphys[] = {
118 MII_PHY_DESC(BROADCOM, BCM5400),
119 MII_PHY_DESC(BROADCOM, BCM5401),
120 MII_PHY_DESC(BROADCOM, BCM5402),
121 MII_PHY_DESC(BROADCOM, BCM5411),
122 MII_PHY_DESC(BROADCOM, BCM5404),
123 MII_PHY_DESC(BROADCOM, BCM5424),
124 MII_PHY_DESC(BROADCOM, BCM54K2),
125 MII_PHY_DESC(BROADCOM, BCM5701),
126 MII_PHY_DESC(BROADCOM, BCM5703),
127 MII_PHY_DESC(BROADCOM, BCM5704),
128 MII_PHY_DESC(BROADCOM, BCM5705),
129 MII_PHY_DESC(BROADCOM, BCM5706),
130 MII_PHY_DESC(BROADCOM, BCM5714),
131 MII_PHY_DESC(BROADCOM, BCM5421),
132 MII_PHY_DESC(BROADCOM, BCM5750),
133 MII_PHY_DESC(BROADCOM, BCM5752),
134 MII_PHY_DESC(BROADCOM, BCM5780),
135 MII_PHY_DESC(BROADCOM, BCM5708C),
136 MII_PHY_DESC(BROADCOM, BCM5466),
137 MII_PHY_DESC(BROADCOM2, BCM5478),
138 MII_PHY_DESC(BROADCOM2, BCM5488),
139 MII_PHY_DESC(BROADCOM2, BCM5482),
140 MII_PHY_DESC(BROADCOM2, BCM5708S),
141 MII_PHY_DESC(BROADCOM2, BCM5709C),
142 MII_PHY_DESC(BROADCOM2, BCM5709S),
143 MII_PHY_DESC(BROADCOM2, BCM5709CAX),
144 MII_PHY_DESC(BROADCOM2, BCM5722),
145 MII_PHY_DESC(BROADCOM2, BCM5755),
146 MII_PHY_DESC(BROADCOM2, BCM5754),
147 MII_PHY_DESC(BROADCOM2, BCM5761),
148 MII_PHY_DESC(BROADCOM2, BCM5784),
149 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */
150 MII_PHY_DESC(BROADCOM2, BCM5785),
151 #endif
152 MII_PHY_DESC(BROADCOM3, BCM54616S),
153 MII_PHY_DESC(BROADCOM3, BCM54618SE),
154 MII_PHY_DESC(BROADCOM3, BCM5717C),
155 MII_PHY_DESC(BROADCOM3, BCM5719C),
156 MII_PHY_DESC(BROADCOM3, BCM5720C),
157 MII_PHY_DESC(BROADCOM3, BCM57765),
158 MII_PHY_DESC(BROADCOM3, BCM57780),
159 MII_PHY_DESC(BROADCOM4, BCM54213PE),
160 MII_PHY_DESC(BROADCOM4, BCM5725C),
161 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
162 MII_PHY_END
163 };
164
165 static const struct mii_phy_funcs brgphy_funcs = {
166 brgphy_service,
167 brgphy_status,
168 brgphy_reset
169 };
170
171 static const struct hs21_type {
172 const uint32_t id;
173 const char *prod;
174 } hs21_type_lists[] = {
175 { 0x57081021, "IBM eServer BladeCenter HS21" },
176 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" },
177 };
178
179 static int
detect_hs21(struct bce_softc * bce_sc)180 detect_hs21(struct bce_softc *bce_sc)
181 {
182 char *sysenv;
183 int found, i;
184
185 found = 0;
186 sysenv = kern_getenv("smbios.system.product");
187 if (sysenv == NULL)
188 return (found);
189 for (i = 0; i < nitems(hs21_type_lists); i++) {
190 if (bce_sc->bce_chipid == hs21_type_lists[i].id &&
191 strncmp(sysenv, hs21_type_lists[i].prod,
192 strlen(hs21_type_lists[i].prod)) == 0) {
193 found++;
194 break;
195 }
196 }
197 freeenv(sysenv);
198 return (found);
199 }
200
201 /* Search for our PHY in the list of known PHYs */
202 static int
brgphy_probe(device_t dev)203 brgphy_probe(device_t dev)
204 {
205
206 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
207 }
208
209 /* Attach the PHY to the MII bus */
210 static int
brgphy_attach(device_t dev)211 brgphy_attach(device_t dev)
212 {
213 struct brgphy_softc *bsc;
214 struct bge_softc *bge_sc = NULL;
215 struct bce_softc *bce_sc = NULL;
216 struct mii_softc *sc;
217
218 bsc = device_get_softc(dev);
219 sc = &bsc->mii_sc;
220
221 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
222 &brgphy_funcs, 0);
223
224 bsc->serdes_flags = 0;
225
226 /* Find the MAC driver associated with this PHY. */
227 if (mii_dev_mac_match(dev, "bge"))
228 bge_sc = mii_dev_mac_softc(dev);
229 else if (mii_dev_mac_match(dev, "bce"))
230 bce_sc = mii_dev_mac_softc(dev);
231
232 /* Handle any special cases based on the PHY ID */
233 switch (sc->mii_mpd_oui) {
234 case MII_OUI_BROADCOM:
235 switch (sc->mii_mpd_model) {
236 case MII_MODEL_BROADCOM_BCM5706:
237 case MII_MODEL_BROADCOM_BCM5714:
238 /*
239 * The 5464 PHY used in the 5706 supports both copper
240 * and fiber interfaces over GMII. Need to check the
241 * shadow registers to see which mode is actually
242 * in effect, and therefore whether we have 5706C or
243 * 5706S.
244 */
245 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
246 BRGPHY_SHADOW_1C_MODE_CTRL);
247 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
248 BRGPHY_SHADOW_1C_ENA_1000X) {
249 bsc->serdes_flags |= BRGPHY_5706S;
250 sc->mii_flags |= MIIF_HAVEFIBER;
251 }
252 break;
253 }
254 break;
255 case MII_OUI_BROADCOM2:
256 switch (sc->mii_mpd_model) {
257 case MII_MODEL_BROADCOM2_BCM5708S:
258 bsc->serdes_flags |= BRGPHY_5708S;
259 sc->mii_flags |= MIIF_HAVEFIBER;
260 break;
261 case MII_MODEL_BROADCOM2_BCM5709S:
262 /*
263 * XXX
264 * 5720S and 5709S shares the same PHY id.
265 * Assume 5720S PHY if parent device is bge(4).
266 */
267 if (bge_sc != NULL)
268 bsc->serdes_flags |= BRGPHY_5708S;
269 else
270 bsc->serdes_flags |= BRGPHY_5709S;
271 sc->mii_flags |= MIIF_HAVEFIBER;
272 break;
273 }
274 break;
275 }
276
277 PHY_RESET(sc);
278
279 /* Read the PHY's capabilities. */
280 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
281 if (sc->mii_capabilities & BMSR_EXTSTAT)
282 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
283 device_printf(dev, " ");
284
285 /* Add the supported media types */
286 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
287 mii_phy_add_media(sc);
288 printf("\n");
289 } else {
290 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
291 ifmedia_add(&sc->mii_pdata->mii_media,
292 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
293 0, NULL);
294 printf("1000baseSX-FDX, ");
295 /*
296 * 2.5G support is a software enabled feature
297 * on the 5708S and 5709S.
298 */
299 if (bce_sc && (bce_sc->bce_phy_flags &
300 BCE_PHY_2_5G_CAPABLE_FLAG)) {
301 ifmedia_add(&sc->mii_pdata->mii_media,
302 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX,
303 sc->mii_inst), 0, NULL);
304 printf("2500baseSX-FDX, ");
305 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
306 (detect_hs21(bce_sc) != 0)) {
307 /*
308 * There appears to be certain silicon revision
309 * in IBM HS21 blades that is having issues with
310 * this driver wating for the auto-negotiation to
311 * complete. This happens with a specific chip id
312 * only and when the 1000baseSX-FDX is the only
313 * mode. Workaround this issue since it's unlikely
314 * to be ever addressed.
315 */
316 printf("auto-neg workaround, ");
317 bsc->serdes_flags |= BRGPHY_NOANWAIT;
318 }
319 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER,
320 IFM_AUTO, 0, sc->mii_inst), 0, NULL);
321 printf("auto\n");
322 }
323
324 MIIBUS_MEDIAINIT(sc->mii_dev);
325 return (0);
326 }
327
328 static int
brgphy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)329 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
330 {
331 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
332 int val;
333
334 switch (cmd) {
335 case MII_POLLSTAT:
336 break;
337 case MII_MEDIACHG:
338 /* Todo: Why is this here? Is it really needed? */
339 PHY_RESET(sc); /* XXX hardware bug work-around */
340
341 switch (IFM_SUBTYPE(ife->ifm_media)) {
342 case IFM_AUTO:
343 brgphy_mii_phy_auto(sc, ife->ifm_media);
344 break;
345 case IFM_2500_SX:
346 case IFM_1000_SX:
347 case IFM_1000_T:
348 case IFM_100_TX:
349 case IFM_10_T:
350 brgphy_setmedia(sc, ife->ifm_media);
351 break;
352 default:
353 return (EINVAL);
354 }
355 break;
356 case MII_TICK:
357 /* Bail if autoneg isn't in process. */
358 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
359 sc->mii_ticks = 0;
360 break;
361 }
362
363 /*
364 * Check to see if we have link. If we do, we don't
365 * need to restart the autonegotiation process.
366 */
367 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
368 if (val & BMSR_LINK) {
369 sc->mii_ticks = 0; /* Reset autoneg timer. */
370 break;
371 }
372
373 /* Announce link loss right after it happens. */
374 if (sc->mii_ticks++ == 0)
375 break;
376
377 /* Only retry autonegotiation every mii_anegticks seconds. */
378 if (sc->mii_ticks <= sc->mii_anegticks)
379 break;
380
381 /* Retry autonegotiation */
382 sc->mii_ticks = 0;
383 brgphy_mii_phy_auto(sc, ife->ifm_media);
384 break;
385 }
386
387 /* Update the media status. */
388 PHY_STATUS(sc);
389
390 /*
391 * Callback if something changed. Note that we need to poke
392 * the DSP on the Broadcom PHYs if the media changes.
393 */
394 if (sc->mii_media_active != mii->mii_media_active ||
395 sc->mii_media_status != mii->mii_media_status ||
396 cmd == MII_MEDIACHG) {
397 switch (sc->mii_mpd_oui) {
398 case MII_OUI_BROADCOM:
399 switch (sc->mii_mpd_model) {
400 case MII_MODEL_BROADCOM_BCM5400:
401 bcm5401_load_dspcode(sc);
402 break;
403 case MII_MODEL_BROADCOM_BCM5401:
404 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
405 bcm5401_load_dspcode(sc);
406 break;
407 case MII_MODEL_BROADCOM_BCM5411:
408 bcm5411_load_dspcode(sc);
409 break;
410 case MII_MODEL_BROADCOM_BCM54K2:
411 bcm54k2_load_dspcode(sc);
412 break;
413 }
414 break;
415 case MII_OUI_BROADCOM4:
416 switch (sc->mii_mpd_model) {
417 case MII_MODEL_BROADCOM4_BCM54213PE:
418 brgphy_bcm54xx_clock_delay(sc);
419 break;
420 }
421 }
422 }
423 mii_phy_update(sc, cmd);
424 return (0);
425 }
426
427 /****************************************************************************/
428 /* Sets the PHY link speed. */
429 /* */
430 /* Returns: */
431 /* None */
432 /****************************************************************************/
433 static void
brgphy_setmedia(struct mii_softc * sc,int media)434 brgphy_setmedia(struct mii_softc *sc, int media)
435 {
436 int bmcr = 0, gig;
437
438 switch (IFM_SUBTYPE(media)) {
439 case IFM_2500_SX:
440 break;
441 case IFM_1000_SX:
442 case IFM_1000_T:
443 bmcr = BRGPHY_S1000;
444 break;
445 case IFM_100_TX:
446 bmcr = BRGPHY_S100;
447 break;
448 case IFM_10_T:
449 default:
450 bmcr = BRGPHY_S10;
451 break;
452 }
453
454 if ((media & IFM_FDX) != 0) {
455 bmcr |= BRGPHY_BMCR_FDX;
456 gig = BRGPHY_1000CTL_AFD;
457 } else {
458 gig = BRGPHY_1000CTL_AHD;
459 }
460
461 /* Force loopback to disconnect PHY from Ethernet medium. */
462 brgphy_enable_loopback(sc);
463
464 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
465 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
466
467 if (IFM_SUBTYPE(media) != IFM_1000_T &&
468 IFM_SUBTYPE(media) != IFM_1000_SX) {
469 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
470 return;
471 }
472
473 if (IFM_SUBTYPE(media) == IFM_1000_T) {
474 gig |= BRGPHY_1000CTL_MSE;
475 if ((media & IFM_ETH_MASTER) != 0)
476 gig |= BRGPHY_1000CTL_MSC;
477 }
478 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
479 PHY_WRITE(sc, BRGPHY_MII_BMCR,
480 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
481 }
482
483 /****************************************************************************/
484 /* Set the media status based on the PHY settings. */
485 /* */
486 /* Returns: */
487 /* None */
488 /****************************************************************************/
489 static void
brgphy_status(struct mii_softc * sc)490 brgphy_status(struct mii_softc *sc)
491 {
492 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
493 struct mii_data *mii = sc->mii_pdata;
494 int aux, bmcr, bmsr, val, xstat;
495 u_int flowstat;
496
497 mii->mii_media_status = IFM_AVALID;
498 mii->mii_media_active = IFM_ETHER;
499
500 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
501 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
502
503 if (bmcr & BRGPHY_BMCR_LOOP) {
504 mii->mii_media_active |= IFM_LOOP;
505 }
506
507 if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
508 (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
509 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
510 /* Erg, still trying, I guess... */
511 mii->mii_media_active |= IFM_NONE;
512 return;
513 }
514
515 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
516 /*
517 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
518 * wedges at least the PHY of BCM5704 (but not others).
519 */
520 flowstat = mii_phy_flowstatus(sc);
521 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
522 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
523
524 /* If copper link is up, get the negotiated speed/duplex. */
525 if (aux & BRGPHY_AUXSTS_LINK) {
526 mii->mii_media_status |= IFM_ACTIVE;
527 switch (aux & BRGPHY_AUXSTS_AN_RES) {
528 case BRGPHY_RES_1000FD:
529 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break;
530 case BRGPHY_RES_1000HD:
531 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break;
532 case BRGPHY_RES_100FD:
533 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
534 case BRGPHY_RES_100T4:
535 mii->mii_media_active |= IFM_100_T4; break;
536 case BRGPHY_RES_100HD:
537 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break;
538 case BRGPHY_RES_10FD:
539 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
540 case BRGPHY_RES_10HD:
541 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
542 default:
543 mii->mii_media_active |= IFM_NONE; break;
544 }
545
546 if ((mii->mii_media_active & IFM_FDX) != 0)
547 mii->mii_media_active |= flowstat;
548
549 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
550 (xstat & BRGPHY_1000STS_MSR) != 0)
551 mii->mii_media_active |= IFM_ETH_MASTER;
552 }
553 } else {
554 /* Todo: Add support for flow control. */
555 /* If serdes link is up, get the negotiated speed/duplex. */
556 if (bmsr & BRGPHY_BMSR_LINK) {
557 mii->mii_media_status |= IFM_ACTIVE;
558 }
559
560 /* Check the link speed/duplex based on the PHY type. */
561 if (bsc->serdes_flags & BRGPHY_5706S) {
562 mii->mii_media_active |= IFM_1000_SX;
563
564 /* If autoneg enabled, read negotiated duplex settings */
565 if (bmcr & BRGPHY_BMCR_AUTOEN) {
566 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
567 if (val & BRGPHY_SERDES_ANAR_FDX)
568 mii->mii_media_active |= IFM_FDX;
569 else
570 mii->mii_media_active |= IFM_HDX;
571 }
572 } else if (bsc->serdes_flags & BRGPHY_5708S) {
573 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
574 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
575
576 /* Check for MRBE auto-negotiated speed results. */
577 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
578 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
579 mii->mii_media_active |= IFM_10_FL; break;
580 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
581 mii->mii_media_active |= IFM_100_FX; break;
582 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
583 mii->mii_media_active |= IFM_1000_SX; break;
584 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
585 mii->mii_media_active |= IFM_2500_SX; break;
586 }
587
588 /* Check for MRBE auto-negotiated duplex results. */
589 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
590 mii->mii_media_active |= IFM_FDX;
591 else
592 mii->mii_media_active |= IFM_HDX;
593 } else if (bsc->serdes_flags & BRGPHY_5709S) {
594 /* Select GP Status Block of the AN MMD, get autoneg results. */
595 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
596 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
597
598 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
599 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
600
601 /* Check for MRBE auto-negotiated speed results. */
602 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
603 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
604 mii->mii_media_active |= IFM_10_FL; break;
605 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
606 mii->mii_media_active |= IFM_100_FX; break;
607 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
608 mii->mii_media_active |= IFM_1000_SX; break;
609 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
610 mii->mii_media_active |= IFM_2500_SX; break;
611 }
612
613 /* Check for MRBE auto-negotiated duplex results. */
614 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
615 mii->mii_media_active |= IFM_FDX;
616 else
617 mii->mii_media_active |= IFM_HDX;
618 }
619 }
620 }
621
622 static void
brgphy_mii_phy_auto(struct mii_softc * sc,int media)623 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
624 {
625 int anar, ktcr = 0;
626
627 PHY_RESET(sc);
628
629 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
630 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
631 if ((media & IFM_FLOW) != 0 ||
632 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
633 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
634 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
635 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
636 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
637 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
638 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
639 PHY_READ(sc, BRGPHY_MII_1000CTL);
640 } else {
641 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
642 if ((media & IFM_FLOW) != 0 ||
643 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
644 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
645 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
646 }
647
648 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
649 BRGPHY_BMCR_STARTNEG);
650 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
651 }
652
653 /* Enable loopback to force the link down. */
654 static void
brgphy_enable_loopback(struct mii_softc * sc)655 brgphy_enable_loopback(struct mii_softc *sc)
656 {
657 int i;
658
659 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
660 for (i = 0; i < 15000; i++) {
661 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
662 break;
663 DELAY(10);
664 }
665 }
666
667 /* Turn off tap power management on 5401. */
668 static void
bcm5401_load_dspcode(struct mii_softc * sc)669 bcm5401_load_dspcode(struct mii_softc *sc)
670 {
671 static const struct {
672 int reg;
673 uint16_t val;
674 } dspcode[] = {
675 { BRGPHY_MII_AUXCTL, 0x0c20 },
676 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
677 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
678 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
679 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
680 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
681 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
682 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
683 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
684 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
685 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
686 { 0, 0 },
687 };
688 int i;
689
690 for (i = 0; dspcode[i].reg != 0; i++)
691 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
692 DELAY(40);
693 }
694
695 static void
bcm5411_load_dspcode(struct mii_softc * sc)696 bcm5411_load_dspcode(struct mii_softc *sc)
697 {
698 static const struct {
699 int reg;
700 uint16_t val;
701 } dspcode[] = {
702 { 0x1c, 0x8c23 },
703 { 0x1c, 0x8ca3 },
704 { 0x1c, 0x8c23 },
705 { 0, 0 },
706 };
707 int i;
708
709 for (i = 0; dspcode[i].reg != 0; i++)
710 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
711 }
712
713 void
bcm54k2_load_dspcode(struct mii_softc * sc)714 bcm54k2_load_dspcode(struct mii_softc *sc)
715 {
716 static const struct {
717 int reg;
718 uint16_t val;
719 } dspcode[] = {
720 { 4, 0x01e1 },
721 { 9, 0x0300 },
722 { 0, 0 },
723 };
724 int i;
725
726 for (i = 0; dspcode[i].reg != 0; i++)
727 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
728
729 }
730
731 static void
brgphy_fixup_5704_a0_bug(struct mii_softc * sc)732 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
733 {
734 static const struct {
735 int reg;
736 uint16_t val;
737 } dspcode[] = {
738 { 0x1c, 0x8d68 },
739 { 0x1c, 0x8d68 },
740 { 0, 0 },
741 };
742 int i;
743
744 for (i = 0; dspcode[i].reg != 0; i++)
745 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
746 }
747
748 static void
brgphy_fixup_adc_bug(struct mii_softc * sc)749 brgphy_fixup_adc_bug(struct mii_softc *sc)
750 {
751 static const struct {
752 int reg;
753 uint16_t val;
754 } dspcode[] = {
755 { BRGPHY_MII_AUXCTL, 0x0c00 },
756 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
757 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
758 { 0, 0 },
759 };
760 int i;
761
762 for (i = 0; dspcode[i].reg != 0; i++)
763 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
764 }
765
766 static void
brgphy_fixup_adjust_trim(struct mii_softc * sc)767 brgphy_fixup_adjust_trim(struct mii_softc *sc)
768 {
769 static const struct {
770 int reg;
771 uint16_t val;
772 } dspcode[] = {
773 { BRGPHY_MII_AUXCTL, 0x0c00 },
774 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
775 { BRGPHY_MII_DSP_RW_PORT, 0x110b },
776 { BRGPHY_MII_TEST1, 0x0014 },
777 { BRGPHY_MII_AUXCTL, 0x0400 },
778 { 0, 0 },
779 };
780 int i;
781
782 for (i = 0; dspcode[i].reg != 0; i++)
783 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
784 }
785
786 static void
brgphy_fixup_ber_bug(struct mii_softc * sc)787 brgphy_fixup_ber_bug(struct mii_softc *sc)
788 {
789 static const struct {
790 int reg;
791 uint16_t val;
792 } dspcode[] = {
793 { BRGPHY_MII_AUXCTL, 0x0c00 },
794 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
795 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
796 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
797 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
798 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
799 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
800 { BRGPHY_MII_AUXCTL, 0x0400 },
801 { 0, 0 },
802 };
803 int i;
804
805 for (i = 0; dspcode[i].reg != 0; i++)
806 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
807 }
808
809 static void
brgphy_fixup_crc_bug(struct mii_softc * sc)810 brgphy_fixup_crc_bug(struct mii_softc *sc)
811 {
812 static const struct {
813 int reg;
814 uint16_t val;
815 } dspcode[] = {
816 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 },
817 { 0x1c, 0x8c68 },
818 { 0x1c, 0x8d68 },
819 { 0x1c, 0x8c68 },
820 { 0, 0 },
821 };
822 int i;
823
824 for (i = 0; dspcode[i].reg != 0; i++)
825 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
826 }
827
828 static void
brgphy_fixup_jitter_bug(struct mii_softc * sc)829 brgphy_fixup_jitter_bug(struct mii_softc *sc)
830 {
831 static const struct {
832 int reg;
833 uint16_t val;
834 } dspcode[] = {
835 { BRGPHY_MII_AUXCTL, 0x0c00 },
836 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
837 { BRGPHY_MII_DSP_RW_PORT, 0x010b },
838 { BRGPHY_MII_AUXCTL, 0x0400 },
839 { 0, 0 },
840 };
841 int i;
842
843 for (i = 0; dspcode[i].reg != 0; i++)
844 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
845 }
846
847 static void
brgphy_fixup_disable_early_dac(struct mii_softc * sc)848 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
849 {
850 uint32_t val;
851
852 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
853 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
854 val &= ~(1 << 8);
855 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
856
857 }
858
859 static void
brgphy_ethernet_wirespeed(struct mii_softc * sc)860 brgphy_ethernet_wirespeed(struct mii_softc *sc)
861 {
862 uint32_t val;
863
864 /* Enable Ethernet@WireSpeed. */
865 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
866 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
867 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
868 }
869
870 static void
brgphy_bcm54xx_clock_delay(struct mii_softc * sc)871 brgphy_bcm54xx_clock_delay(struct mii_softc *sc)
872 {
873 uint16_t val;
874
875 if (!(sc->mii_flags & (MIIF_RX_DELAY | MIIF_TX_DELAY)))
876 /* Adjusting the clocks in rgmii mode causes packet losses. */
877 return;
878
879 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC |
880 BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT);
881 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
882 val &= BRGPHY_AUXCTL_MISC_DATA_MASK;
883 if (sc->mii_flags & MIIF_RX_DELAY)
884 val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
885 else
886 val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
887 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN |
888 BRGPHY_AUXCTL_SHADOW_MISC | val);
889
890 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_CLK_CTRL);
891 val = PHY_READ(sc, BRGPHY_MII_SHADOW_1C);
892 val &= BRGPHY_SHADOW_1C_DATA_MASK;
893 if (sc->mii_flags & MIIF_TX_DELAY)
894 val |= BRGPHY_SHADOW_1C_GTXCLK_EN;
895 else
896 val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN;
897 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_WRITE_EN |
898 BRGPHY_SHADOW_1C_CLK_CTRL | val);
899 }
900
901 static void
brgphy_jumbo_settings(struct mii_softc * sc,u_long mtu)902 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
903 {
904 uint32_t val;
905
906 /* Set or clear jumbo frame settings in the PHY. */
907 if (mtu > ETHER_MAX_LEN) {
908 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
909 /* BCM5401 PHY cannot read-modify-write. */
910 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
911 } else {
912 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
913 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
914 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
915 val | BRGPHY_AUXCTL_LONG_PKT);
916 }
917
918 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
919 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
920 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
921 } else {
922 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
923 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
924 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
925 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
926
927 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
928 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
929 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
930 }
931 }
932
933 static void
brgphy_reset(struct mii_softc * sc)934 brgphy_reset(struct mii_softc *sc)
935 {
936 struct bge_softc *bge_sc = NULL;
937 struct bce_softc *bce_sc = NULL;
938 if_t ifp;
939 int i, val;
940
941 /*
942 * Perform a reset. Note that at least some Broadcom PHYs default to
943 * being powered down as well as isolated after a reset but don't work
944 * if one or both of these bits are cleared. However, they just work
945 * fine if both bits remain set, so we don't use mii_phy_reset() here.
946 */
947 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
948
949 /* Wait 100ms for it to complete. */
950 for (i = 0; i < 100; i++) {
951 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
952 break;
953 DELAY(1000);
954 }
955
956 /* Handle any PHY specific procedures following the reset. */
957 switch (sc->mii_mpd_oui) {
958 case MII_OUI_BROADCOM:
959 switch (sc->mii_mpd_model) {
960 case MII_MODEL_BROADCOM_BCM5400:
961 bcm5401_load_dspcode(sc);
962 break;
963 case MII_MODEL_BROADCOM_BCM5401:
964 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
965 bcm5401_load_dspcode(sc);
966 break;
967 case MII_MODEL_BROADCOM_BCM5411:
968 bcm5411_load_dspcode(sc);
969 break;
970 case MII_MODEL_BROADCOM_BCM54K2:
971 bcm54k2_load_dspcode(sc);
972 break;
973 }
974 break;
975 case MII_OUI_BROADCOM3:
976 switch (sc->mii_mpd_model) {
977 case MII_MODEL_BROADCOM3_BCM5717C:
978 case MII_MODEL_BROADCOM3_BCM5719C:
979 case MII_MODEL_BROADCOM3_BCM5720C:
980 case MII_MODEL_BROADCOM3_BCM57765:
981 return;
982 }
983 break;
984 case MII_OUI_BROADCOM4:
985 return;
986 }
987
988 ifp = sc->mii_pdata->mii_ifp;
989
990 /* Find the driver associated with this PHY. */
991 if (mii_phy_mac_match(sc, "bge"))
992 bge_sc = mii_phy_mac_softc(sc);
993 else if (mii_phy_mac_match(sc, "bce"))
994 bce_sc = mii_phy_mac_softc(sc);
995
996 if (bge_sc) {
997 /* Fix up various bugs */
998 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
999 brgphy_fixup_5704_a0_bug(sc);
1000 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
1001 brgphy_fixup_adc_bug(sc);
1002 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
1003 brgphy_fixup_adjust_trim(sc);
1004 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
1005 brgphy_fixup_ber_bug(sc);
1006 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
1007 brgphy_fixup_crc_bug(sc);
1008 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
1009 brgphy_fixup_jitter_bug(sc);
1010
1011 if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
1012 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1013
1014 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
1015 brgphy_ethernet_wirespeed(sc);
1016
1017 /* Enable Link LED on Dell boxes */
1018 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
1019 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
1020 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
1021 ~BRGPHY_PHY_EXTCTL_3_LED);
1022 }
1023
1024 /* Adjust output voltage (From Linux driver) */
1025 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
1026 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
1027 } else if (bce_sc) {
1028 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
1029 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1030 /* Store autoneg capabilities/results in digital block (Page 0) */
1031 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
1032 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
1033 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
1034 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
1035
1036 /* Enable fiber mode and autodetection */
1037 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
1038 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
1039 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
1040 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
1041
1042 /* Enable parallel detection */
1043 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1044 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1045 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1046
1047 /* Advertise 2.5G support through next page during autoneg */
1048 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1049 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1050 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1051 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1052
1053 /* Increase TX signal amplitude */
1054 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1055 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1056 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1057 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1058 BRGPHY_5708S_TX_MISC_PG5);
1059 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1060 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1061 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1062 BRGPHY_5708S_DIG_PG0);
1063 }
1064
1065 /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1066 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1067 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1068 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1069 BRGPHY_5708S_TX_MISC_PG5);
1070 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1071 bce_sc->bce_port_hw_cfg &
1072 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1073 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1074 BRGPHY_5708S_DIG_PG0);
1075 }
1076 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1077 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1078 /* Select the SerDes Digital block of the AN MMD. */
1079 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1080 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1081 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1082 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1083 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1084
1085 /* Select the Over 1G block of the AN MMD. */
1086 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1087
1088 /* Enable autoneg "Next Page" to advertise 2.5G support. */
1089 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1090 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1091 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1092 else
1093 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1094 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1095
1096 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1097 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1098
1099 /* Enable MRBE speed autoneg. */
1100 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1101 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1102 BRGPHY_MRBE_MSG_PG5_NP_T2;
1103 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1104
1105 /* Select the Clause 73 User B0 block of the AN MMD. */
1106 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1107
1108 /* Enable MRBE speed autoneg. */
1109 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1110 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1111 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1112 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1113
1114 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1115 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1116 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1117 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1118 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1119 brgphy_fixup_disable_early_dac(sc);
1120
1121 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1122 brgphy_ethernet_wirespeed(sc);
1123 } else {
1124 brgphy_fixup_ber_bug(sc);
1125 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1126 brgphy_ethernet_wirespeed(sc);
1127 }
1128 }
1129 }
1130