1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _DEV_MII_AMTPHYREG_H_ 36 #define _DEV_MII_AMTPHYREG_H_ 37 38 /* 39 * AMD Am79C873 registers. 40 */ 41 42 43 #define MII_AMPHY_DSCR 0x10 /* Specified configuration register */a 44 #define DSCR_BP4B5B 0x8000 /* Bypass 4B5B encoding */ 45 #define DSCR_BPSCR 0x4000 /* Bypass scrambler */ 46 #define DSCR_BPALIGN 0x2000 /* Bypass symbol alignment */ 47 #define DSCR_REPEATER 0x0800 /* Repeater mode */ 48 #define DSCR_TX 0x0400 /* TX/FX mode control */ 49 #define DSCR_UTP 0x0200 /* UTP/STP mode control */ 50 #define DSCR_CLK25MDIS 0x0100 /* CLK25M disable */ 51 #define DSCR_FGLNKTX 0x0080 /* Force good link at 100baseTX */ 52 #define DSCR_LINKLEDCTL 0x0020 /* Link LED control */ 53 #define DSCR_FDXLEDCTL 0x0010 /* FDX LED control */ 54 #define DSCR_SMRTS 0x0008 /* Reset state machine */ 55 #define DSCR_MFPSC 0x0004 /* Preamble surpression control */ 56 #define DSCR_SLEEP 0x0002 /* Sleep mode */ 57 #define DSCR_RLOUT 0x0001 /* Remote loopout control */ 58 59 #define MII_AMPHY_DSCSR 0x11 /* Specified configuration and status */ 60 #define DSCSR_100FDX 0x8000 /* 100MBps full duplex */ 61 #define DSCSR_100HDX 0x4000 /* 100Mbps half duplex */ 62 #define DSCSR_10FDX 0x2000 /* 10Mbps full duplex */ 63 #define DSCSR_10HDX 0x1000 /* 10Mbps half duplex */ 64 #define DSCSR_PADDR 0x01F0 /* PHY address */ 65 #define DSCSR_ASTAT 0x000F /* Autonegotiation status */ 66 67 #define ASTAT_COMPLETE 0x8 68 #define ASTAT_PDLINK_READY_FAIL 0x7 69 #define ASTAT_PDLINK_READY 0x6 70 #define ASTAT_CONSTMATCH_FAIL 0x5 71 #define ASTAT_CONSTMATCH 0x4 72 #define ASTAT_ACKMATCH_FAIL 0x3 73 #define ASTAT_ACKMATCH 0x2 74 #define ASTAT_ABILITYMATCH 0x1 75 #define ASTAT_IDLE 0x0 76 77 #define MII_AMPHY_T10CSRSCR 0x12 /* 10baseT configuration/status */ 78 #define T10CSRSCR_LPEN 0x4000 /* Link pulse enable */ 79 #define T10CSRSCR_HBE 0x2000 /* Heartbeat enable */ 80 #define T10CSRSCR_JABEN 0x0800 /* Jabber enable */ 81 #define T10CSRSCR_SER 0x0400 /* Serial mode enable */ 82 #define T10CSRSCR_POLR 0x0001 /* Polarity reversed */ 83 84 #endif /* _DEV_MII_AMTPHYREG_H_ */ 85