1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _DEV_MII_AMTPHYREG_H_ 36 #define _DEV_MII_AMTPHYREG_H_ 37 38 /* 39 * AMD Am79C873 registers. 40 */ 41 42 #define MII_AMPHY_DSCR 0x10 /* Specified configuration register */a 43 #define DSCR_BP4B5B 0x8000 /* Bypass 4B5B encoding */ 44 #define DSCR_BPSCR 0x4000 /* Bypass scrambler */ 45 #define DSCR_BPALIGN 0x2000 /* Bypass symbol alignment */ 46 #define DSCR_REPEATER 0x0800 /* Repeater mode */ 47 #define DSCR_TX 0x0400 /* TX/FX mode control */ 48 #define DSCR_UTP 0x0200 /* UTP/STP mode control */ 49 #define DSCR_CLK25MDIS 0x0100 /* CLK25M disable */ 50 #define DSCR_FGLNKTX 0x0080 /* Force good link at 100baseTX */ 51 #define DSCR_LINKLEDCTL 0x0020 /* Link LED control */ 52 #define DSCR_FDXLEDCTL 0x0010 /* FDX LED control */ 53 #define DSCR_SMRTS 0x0008 /* Reset state machine */ 54 #define DSCR_MFPSC 0x0004 /* Preamble surpression control */ 55 #define DSCR_SLEEP 0x0002 /* Sleep mode */ 56 #define DSCR_RLOUT 0x0001 /* Remote loopout control */ 57 58 #define MII_AMPHY_DSCSR 0x11 /* Specified configuration and status */ 59 #define DSCSR_100FDX 0x8000 /* 100MBps full duplex */ 60 #define DSCSR_100HDX 0x4000 /* 100Mbps half duplex */ 61 #define DSCSR_10FDX 0x2000 /* 10Mbps full duplex */ 62 #define DSCSR_10HDX 0x1000 /* 10Mbps half duplex */ 63 #define DSCSR_PADDR 0x01F0 /* PHY address */ 64 #define DSCSR_ASTAT 0x000F /* Autonegotiation status */ 65 66 #define ASTAT_COMPLETE 0x8 67 #define ASTAT_PDLINK_READY_FAIL 0x7 68 #define ASTAT_PDLINK_READY 0x6 69 #define ASTAT_CONSTMATCH_FAIL 0x5 70 #define ASTAT_CONSTMATCH 0x4 71 #define ASTAT_ACKMATCH_FAIL 0x3 72 #define ASTAT_ACKMATCH 0x2 73 #define ASTAT_ABILITYMATCH 0x1 74 #define ASTAT_IDLE 0x0 75 76 #define MII_AMPHY_T10CSRSCR 0x12 /* 10baseT configuration/status */ 77 #define T10CSRSCR_LPEN 0x4000 /* Link pulse enable */ 78 #define T10CSRSCR_HBE 0x2000 /* Heartbeat enable */ 79 #define T10CSRSCR_JABEN 0x0800 /* Jabber enable */ 80 #define T10CSRSCR_SER 0x0400 /* Serial mode enable */ 81 #define T10CSRSCR_POLR 0x0001 /* Polarity reversed */ 82 83 #endif /* _DEV_MII_AMTPHYREG_H_ */ 84