1 /*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef __IF_MGE_H__ 35 #define __IF_MGE_H__ 36 37 #define MGE_INTR_COUNT 5 /* ETH controller occupies 5 IRQ lines */ 38 #define MGE_TX_DESC_NUM 256 39 #define MGE_RX_DESC_NUM 256 40 #define MGE_RX_QUEUE_NUM 8 41 #define MGE_RX_DEFAULT_QUEUE 0 42 43 #define MGE_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 44 45 /* Interrupt Coalescing types */ 46 #define MGE_IC_RX 0 47 #define MGE_IC_TX 1 48 49 struct mge_desc { 50 uint32_t cmd_status; 51 uint16_t buff_size; 52 uint16_t byte_count; 53 bus_addr_t buffer; 54 bus_addr_t next_desc; 55 }; 56 57 struct mge_desc_wrapper { 58 bus_dmamap_t desc_dmap; 59 struct mge_desc* mge_desc; 60 bus_addr_t mge_desc_paddr; 61 bus_dmamap_t buffer_dmap; 62 struct mbuf* buffer; 63 }; 64 65 struct mge_softc { 66 struct ifnet *ifp; /* per-interface network data */ 67 68 phandle_t node; 69 70 device_t dev; 71 device_t miibus; 72 73 struct mii_data *mii; 74 struct resource *res[1 + MGE_INTR_COUNT]; /* resources */ 75 void *ih_cookie[MGE_INTR_COUNT]; /* interrupt handlers cookies */ 76 struct mtx transmit_lock; /* transmitter lock */ 77 struct mtx receive_lock; /* receiver lock */ 78 79 uint32_t mge_if_flags; 80 uint32_t mge_media_status; 81 82 struct callout wd_callout; 83 int wd_timer; 84 85 bus_dma_tag_t mge_desc_dtag; 86 bus_dma_tag_t mge_tx_dtag; 87 bus_dma_tag_t mge_rx_dtag; 88 bus_addr_t tx_desc_start; 89 bus_addr_t rx_desc_start; 90 uint32_t tx_desc_curr; 91 uint32_t rx_desc_curr; 92 uint32_t tx_desc_used_idx; 93 uint32_t tx_desc_used_count; 94 uint32_t rx_ic_time; 95 uint32_t tx_ic_time; 96 struct mge_desc_wrapper mge_tx_desc[MGE_TX_DESC_NUM]; 97 struct mge_desc_wrapper mge_rx_desc[MGE_RX_DESC_NUM]; 98 99 uint32_t mge_tfut_ipg_max; /* TX FIFO Urgent Threshold */ 100 uint32_t mge_rx_ipg_max; 101 uint32_t mge_tx_arb_cfg; 102 uint32_t mge_tx_tok_cfg; 103 uint32_t mge_tx_tok_cnt; 104 uint16_t mge_mtu; 105 int mge_ver; 106 107 int phyaddr; 108 }; 109 110 111 /* bus access macros */ 112 #define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg)) 113 #define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val)) 114 115 /* Locking macros */ 116 #define MGE_TRANSMIT_LOCK(sc) do { \ 117 mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ 118 mtx_lock(&(sc)->transmit_lock); \ 119 } while (0) 120 121 #define MGE_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) 122 #define MGE_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) 123 124 #define MGE_RECEIVE_LOCK(sc) do { \ 125 mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ 126 mtx_lock(&(sc)->receive_lock); \ 127 } while (0) 128 129 #define MGE_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) 130 #define MGE_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) 131 132 #define MGE_GLOBAL_LOCK(sc) do { \ 133 if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \ 134 (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \ 135 panic("mge deadlock possibility detection!"); \ 136 } \ 137 mtx_lock(&(sc)->transmit_lock); \ 138 mtx_lock(&(sc)->receive_lock); \ 139 } while (0) 140 141 #define MGE_GLOBAL_UNLOCK(sc) do { \ 142 MGE_RECEIVE_UNLOCK(sc); \ 143 MGE_TRANSMIT_UNLOCK(sc); \ 144 } while (0) 145 146 #define MGE_GLOBAL_LOCK_ASSERT(sc) do { \ 147 MGE_TRANSMIT_LOCK_ASSERT(sc); \ 148 MGE_RECEIVE_LOCK_ASSERT(sc); \ 149 } while (0) 150 151 /* SMI-related macros */ 152 #define MGE_REG_PHYDEV 0x000 153 #define MGE_REG_SMI 0x004 154 #define MGE_SMI_READ (1 << 26) 155 #define MGE_SMI_WRITE (0 << 26) 156 #define MGE_SMI_READVALID (1 << 27) 157 #define MGE_SMI_BUSY (1 << 28) 158 159 /* TODO verify the timings and retries count w/specs */ 160 #define MGE_SMI_READ_RETRIES 1000 161 #define MGE_SMI_READ_DELAY 100 162 #define MGE_SMI_WRITE_RETRIES 1000 163 #define MGE_SMI_WRITE_DELAY 100 164 165 /* MGE registers */ 166 #define MGE_INT_CAUSE 0x080 167 #define MGE_INT_MASK 0x084 168 169 #define MGE_PORT_CONFIG 0x400 170 #define PORT_CONFIG_UPM (1 << 0) /* promiscuous */ 171 #define PORT_CONFIG_DFLT_RXQ(val) (((val) & 7) << 1) /* default RX queue */ 172 #define PORT_CONFIG_ARO_RXQ(val) (((val) & 7) << 4) /* ARP RX queue */ 173 #define PORT_CONFIG_REJECT_BCAST (1 << 7) /* reject non-ip and non-arp bcast */ 174 #define PORT_CONFIG_REJECT_IP_BCAST (1 << 8) /* reject ip bcast */ 175 #define PORT_CONFIG_REJECT_ARP__BCAST (1 << 9) /* reject arp bcast */ 176 #define PORT_CONFIG_AMNoTxES (1 << 12) /* Automatic mode not updating Error Summary in Tx descriptor */ 177 #define PORT_CONFIG_TCP_CAP (1 << 14) /* capture tcp to a different queue */ 178 #define PORT_CONFIG_UDP_CAP (1 << 15) /* capture udp to a different queue */ 179 #define PORT_CONFIG_TCPQ (7 << 16) /* queue to capture tcp */ 180 #define PORT_CONFIG_UDPQ (7 << 19) /* queue to capture udp */ 181 #define PORT_CONFIG_BPDUQ (7 << 22) /* queue to capture bpdu */ 182 #define PORT_CONFIG_RXCS (1 << 25) /* calculation Rx TCP checksum include pseudo header */ 183 184 #define MGE_PORT_EXT_CONFIG 0x404 185 #define MGE_MAC_ADDR_L 0x414 186 #define MGE_MAC_ADDR_H 0x418 187 188 #define MGE_SDMA_CONFIG 0x41c 189 #define MGE_SDMA_INT_ON_FRAME_BOUND (1 << 0) 190 #define MGE_SDMA_RX_BURST_SIZE(val) (((val) & 7) << 1) 191 #define MGE_SDMA_TX_BURST_SIZE(val) (((val) & 7) << 22) 192 #define MGE_SDMA_BURST_1_WORD 0x0 193 #define MGE_SDMA_BURST_2_WORD 0x1 194 #define MGE_SDMA_BURST_4_WORD 0x2 195 #define MGE_SDMA_BURST_8_WORD 0x3 196 #define MGE_SDMA_BURST_16_WORD 0x4 197 #define MGE_SDMA_RX_BYTE_SWAP (1 << 4) 198 #define MGE_SDMA_TX_BYTE_SWAP (1 << 5) 199 #define MGE_SDMA_DESC_SWAP_MODE (1 << 6) 200 201 #define MGE_PORT_SERIAL_CTRL 0x43c 202 #define PORT_SERIAL_ENABLE (1 << 0) /* serial port enable */ 203 #define PORT_SERIAL_FORCE_LINKUP (1 << 1) /* force link status to up */ 204 #define PORT_SERIAL_AUTONEG (1 << 2) /* enable autoneg for duplex mode */ 205 #define PORT_SERIAL_AUTONEG_FC (1 << 3) /* enable autoneg for FC */ 206 #define PORT_SERIAL_PAUSE_ADV (1 << 4) /* advertise symmetric FC in autoneg */ 207 #define PORT_SERIAL_FORCE_FC(val) (((val) & 3) << 5) /* pause enable & disable frames conf */ 208 #define PORT_SERIAL_NO_PAUSE_DIS 0x00 209 #define PORT_SERIAL_PAUSE_DIS 0x01 210 #define PORT_SERIAL_FORCE_BP(val) (((val) & 3) << 7) /* transmitting JAM configuration */ 211 #define PORT_SERIAL_NO_JAM 0x00 212 #define PORT_SERIAL_JAM 0x01 213 #define PORT_SERIAL_RES_BIT9 (1 << 9) 214 #define PORT_SERIAL_FORCE_LINK_FAIL (1 << 10) 215 #define PORT_SERIAL_SPEED_AUTONEG (1 << 13) 216 #define PORT_SERIAL_FORCE_DTE_ADV (1 << 14) 217 #define PORT_SERIAL_MRU(val) (((val) & 7) << 17) 218 #define PORT_SERIAL_MRU_1518 0x0 219 #define PORT_SERIAL_MRU_1522 0x1 220 #define PORT_SERIAL_MRU_1552 0x2 221 #define PORT_SERIAL_MRU_9022 0x3 222 #define PORT_SERIAL_MRU_9192 0x4 223 #define PORT_SERIAL_MRU_9700 0x5 224 #define PORT_SERIAL_FULL_DUPLEX (1 << 21) 225 #define PORT_SERIAL_FULL_DUPLEX_FC (1 << 22) 226 #define PORT_SERIAL_GMII_SPEED_1000 (1 << 23) 227 #define PORT_SERIAL_MII_SPEED_100 (1 << 24) 228 229 #define MGE_PORT_STATUS 0x444 230 #define MGE_STATUS_LINKUP (1 << 1) 231 #define MGE_STATUS_FULL_DUPLEX (1 << 2) 232 #define MGE_STATUS_FLOW_CONTROL (1 << 3) 233 #define MGE_STATUS_1000MB (1 << 4) 234 #define MGE_STATUS_100MB (1 << 5) 235 #define MGE_STATUS_TX_IN_PROG (1 << 7) 236 #define MGE_STATUS_TX_FIFO_EMPTY (1 << 10) 237 238 #define MGE_TX_QUEUE_CMD 0x448 239 #define MGE_ENABLE_TXQ (1 << 0) 240 #define MGE_DISABLE_TXQ (1 << 8) 241 242 /* 88F6281 only */ 243 #define MGE_PORT_SERIAL_CTRL1 0x44c 244 #define MGE_PCS_LOOPBACK (1 << 1) 245 #define MGE_RGMII_EN (1 << 3) 246 #define MGE_PORT_RESET (1 << 4) 247 #define MGE_CLK125_BYPASS (1 << 5) 248 #define MGE_INBAND_AUTONEG (1 << 6) 249 #define MGE_INBAND_AUTONEG_BYPASS (1 << 6) 250 #define MGE_INBAND_AUTONEG_RESTART (1 << 7) 251 #define MGE_1000BASEX (1 << 11) 252 #define MGE_BP_COLLISION_COUNT (1 << 15) 253 #define MGE_COLLISION_LIMIT(val) (((val) & 0x3f) << 16) 254 #define MGE_DROP_ODD_PREAMBLE (1 << 22) 255 256 #define MGE_PORT_INT_CAUSE 0x460 257 #define MGE_PORT_INT_MASK 0x468 258 #define MGE_PORT_INT_RX (1 << 0) 259 #define MGE_PORT_INT_EXTEND (1 << 1) 260 #define MGE_PORT_INT_RXQ0 (1 << 2) 261 #define MGE_PORT_INT_RXERR (1 << 10) 262 #define MGE_PORT_INT_RXERRQ0 (1 << 11) 263 #define MGE_PORT_INT_SUM (1 << 31) 264 265 #define MGE_PORT_INT_CAUSE_EXT 0x464 266 #define MGE_PORT_INT_MASK_EXT 0x46C 267 #define MGE_PORT_INT_EXT_TXBUF0 (1 << 0) 268 #define MGE_PORT_INT_EXT_TXERR0 (1 << 8) 269 #define MGE_PORT_INT_EXT_PHYSC (1 << 16) 270 #define MGE_PORT_INT_EXT_RXOR (1 << 18) 271 #define MGE_PORT_INT_EXT_TXUR (1 << 19) 272 #define MGE_PORT_INT_EXT_LC (1 << 20) 273 #define MGE_PORT_INT_EXT_IAR (1 << 23) 274 #define MGE_PORT_INT_EXT_SUM (1 << 31) 275 276 #define MGE_RX_FIFO_URGENT_TRSH 0x470 277 #define MGE_TX_FIFO_URGENT_TRSH 0x474 278 279 #define MGE_FIXED_PRIO_CONF 0x4dc 280 #define MGE_FIXED_PRIO_EN(q) (1 << (q)) 281 282 #define MGE_RX_CUR_DESC_PTR(q) (0x60c + ((q)<<4)) 283 284 #define MGE_RX_QUEUE_CMD 0x680 285 #define MGE_ENABLE_RXQ(q) (1 << ((q) & 0x7)) 286 #define MGE_ENABLE_RXQ_ALL (0xff) 287 #define MGE_DISABLE_RXQ(q) (1 << (((q) & 0x7) + 8)) 288 #define MGE_DISABLE_RXQ_ALL (0xff00) 289 290 #define MGE_TX_CUR_DESC_PTR 0x6c0 291 292 #define MGE_TX_TOKEN_COUNT(q) (0x700 + ((q)<<4)) 293 #define MGE_TX_TOKEN_CONF(q) (0x704 + ((q)<<4)) 294 #define MGE_TX_ARBITER_CONF(q) (0x704 + ((q)<<4)) 295 296 #define MGE_MCAST_REG_NUMBER 64 297 #define MGE_DA_FILTER_SPEC_MCAST(i) (0x1400 + ((i) << 2)) 298 #define MGE_DA_FILTER_OTH_MCAST(i) (0x1500 + ((i) << 2)) 299 300 #define MGE_UCAST_REG_NUMBER 4 301 #define MGE_DA_FILTER_UCAST(i) (0x1600 + ((i) << 2)) 302 303 304 /* TX descriptor bits */ 305 #define MGE_TX_LLC_SNAP (1 << 9) 306 #define MGE_TX_NOT_FRAGMENT (1 << 10) 307 #define MGE_TX_VLAN_TAGGED (1 << 15) 308 #define MGE_TX_UDP (1 << 16) 309 #define MGE_TX_GEN_L4_CSUM (1 << 17) 310 #define MGE_TX_GEN_IP_CSUM (1 << 18) 311 #define MGE_TX_PADDING (1 << 19) 312 #define MGE_TX_LAST (1 << 20) 313 #define MGE_TX_FIRST (1 << 21) 314 #define MGE_TX_ETH_CRC (1 << 22) 315 #define MGE_TX_EN_INT (1 << 23) 316 317 #define MGE_TX_IP_HDR_SIZE(size) ((size << 11) & 0xFFFF) 318 319 /* RX descriptor bits */ 320 #define MGE_ERR_SUMMARY (1 << 0) 321 #define MGE_ERR_MASK (3 << 1) 322 #define MGE_RX_L4_PROTO_MASK (3 << 21) 323 #define MGE_RX_L4_PROTO_TCP (0 << 21) 324 #define MGE_RX_L4_PROTO_UDP (1 << 21) 325 #define MGE_RX_L3_IS_IP (1 << 24) 326 #define MGE_RX_IP_OK (1 << 25) 327 #define MGE_RX_DESC_LAST (1 << 26) 328 #define MGE_RX_DESC_FIRST (1 << 27) 329 #define MGE_RX_ENABLE_INT (1 << 29) 330 #define MGE_RX_L4_CSUM_OK (1 << 30) 331 #define MGE_DMA_OWNED (1 << 31) 332 333 #define MGE_RX_IP_FRAGMENT (1 << 2) 334 335 #define MGE_RX_L4_IS_TCP(status) ((status & MGE_RX_L4_PROTO_MASK) \ 336 == MGE_RX_L4_PROTO_TCP) 337 338 #define MGE_RX_L4_IS_UDP(status) ((status & MGE_RX_L4_PROTO_MASK) \ 339 == MGE_RX_L4_PROTO_UDP) 340 341 /* TX error codes */ 342 #define MGE_TX_ERROR_LC (0 << 1) /* Late collision */ 343 #define MGE_TX_ERROR_UR (1 << 1) /* Underrun error */ 344 #define MGE_TX_ERROR_RL (2 << 1) /* Excessive collision */ 345 346 /* RX error codes */ 347 #define MGE_RX_ERROR_CE (0 << 1) /* CRC error */ 348 #define MGE_RX_ERROR_OR (1 << 1) /* Overrun error */ 349 #define MGE_RX_ERROR_MF (2 << 1) /* Max frame lenght error */ 350 #define MGE_RX_ERROR_RE (3 << 1) /* Resource error */ 351 352 #endif /* __IF_MGE_H__ */ 353