1 /*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef __IF_MGE_H__ 35 #define __IF_MGE_H__ 36 37 #define MGE_INTR_COUNT 5 /* ETH controller occupies 5 IRQ lines */ 38 #define MGE_TX_DESC_NUM 256 39 #define MGE_RX_DESC_NUM 256 40 #define MGE_RX_QUEUE_NUM 8 41 #define MGE_RX_DEFAULT_QUEUE 0 42 43 #define MGE_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 44 45 /* Interrupt Coalescing types */ 46 #define MGE_IC_RX 0 47 #define MGE_IC_TX 1 48 49 struct mge_desc { 50 uint32_t cmd_status; 51 uint16_t buff_size; 52 uint16_t byte_count; 53 bus_addr_t buffer; 54 bus_addr_t next_desc; 55 }; 56 57 struct mge_desc_wrapper { 58 bus_dmamap_t desc_dmap; 59 struct mge_desc* mge_desc; 60 bus_addr_t mge_desc_paddr; 61 bus_dmamap_t buffer_dmap; 62 struct mbuf* buffer; 63 }; 64 65 struct mge_softc { 66 struct ifnet *ifp; /* per-interface network data */ 67 device_t dev; 68 device_t miibus; 69 struct mii_data *mii; 70 struct resource *res[1 + MGE_INTR_COUNT]; /* resources */ 71 void *ih_cookie[MGE_INTR_COUNT]; /* interrupt handlers cookies */ 72 struct mtx transmit_lock; /* transmitter lock */ 73 struct mtx receive_lock; /* receiver lock */ 74 75 uint32_t mge_if_flags; 76 uint32_t mge_media_status; 77 78 struct callout wd_callout; 79 int wd_timer; 80 81 bus_dma_tag_t mge_desc_dtag; 82 bus_dma_tag_t mge_tx_dtag; 83 bus_dma_tag_t mge_rx_dtag; 84 bus_addr_t tx_desc_start; 85 bus_addr_t rx_desc_start; 86 uint32_t tx_desc_curr; 87 uint32_t rx_desc_curr; 88 uint32_t tx_desc_used_idx; 89 uint32_t tx_desc_used_count; 90 uint32_t rx_ic_time; 91 uint32_t tx_ic_time; 92 struct mge_desc_wrapper mge_tx_desc[MGE_TX_DESC_NUM]; 93 struct mge_desc_wrapper mge_rx_desc[MGE_RX_DESC_NUM]; 94 }; 95 96 97 /* bus access macros */ 98 #define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg)) 99 #define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val)) 100 101 /* Locking macros */ 102 #define MGE_TRANSMIT_LOCK(sc) do { \ 103 mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ 104 mtx_lock(&(sc)->transmit_lock); \ 105 } while (0) 106 107 #define MGE_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) 108 #define MGE_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) 109 110 #define MGE_RECEIVE_LOCK(sc) do { \ 111 mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ 112 mtx_lock(&(sc)->receive_lock); \ 113 } while (0) 114 115 #define MGE_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) 116 #define MGE_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) 117 118 #define MGE_GLOBAL_LOCK(sc) do { \ 119 if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \ 120 (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \ 121 panic("mge deadlock possibility detection!"); \ 122 } \ 123 mtx_lock(&(sc)->transmit_lock); \ 124 mtx_lock(&(sc)->receive_lock); \ 125 } while (0) 126 127 #define MGE_GLOBAL_UNLOCK(sc) do { \ 128 MGE_RECEIVE_UNLOCK(sc); \ 129 MGE_TRANSMIT_UNLOCK(sc); \ 130 } while (0) 131 132 #define MGE_GLOBAL_LOCK_ASSERT(sc) do { \ 133 MGE_TRANSMIT_LOCK_ASSERT(sc); \ 134 MGE_RECEIVE_LOCK_ASSERT(sc); \ 135 } while (0) 136 137 /* SMI-related macros */ 138 #define MGE_REG_PHYDEV 0x000 139 #define MGE_REG_SMI 0x004 140 #define MGE_SMI_READ (1 << 26) 141 #define MGE_SMI_WRITE (0 << 26) 142 #define MGE_SMI_READVALID (1 << 27) 143 #define MGE_SMI_BUSY (1 << 28) 144 145 /* TODO verify the timings and retries count w/specs */ 146 #define MGE_SMI_READ_RETRIES 1000 147 #define MGE_SMI_READ_DELAY 100 148 #define MGE_SMI_WRITE_RETRIES 1000 149 #define MGE_SMI_WRITE_DELAY 100 150 151 /* MGE registers */ 152 #define MGE_INT_CAUSE 0x080 153 #define MGE_INT_MASK 0x084 154 155 #define MGE_PORT_CONFIG 0x400 156 #define PORT_CONFIG_UPM (1 << 0) /* promiscuous */ 157 #define PORT_CONFIG_DFLT_RXQ(val) (((val) & 7) << 1) /* default RX queue */ 158 #define PORT_CONFIG_ARO_RXQ(val) (((val) & 7) << 4) /* ARP RX queue */ 159 #define PORT_CONFIG_REJECT_BCAST (1 << 7) /* reject non-ip and non-arp bcast */ 160 #define PORT_CONFIG_REJECT_IP_BCAST (1 << 8) /* reject ip bcast */ 161 #define PORT_CONFIG_REJECT_ARP__BCAST (1 << 9) /* reject arp bcast */ 162 #define PORT_CONFIG_AMNoTxES (1 << 12) /* Automatic mode not updating Error Summary in Tx descriptor */ 163 #define PORT_CONFIG_TCP_CAP (1 << 14) /* capture tcp to a different queue */ 164 #define PORT_CONFIG_UDP_CAP (1 << 15) /* capture udp to a different queue */ 165 #define PORT_CONFIG_TCPQ (7 << 16) /* queue to capture tcp */ 166 #define PORT_CONFIG_UDPQ (7 << 19) /* queue to capture udp */ 167 #define PORT_CONFIG_BPDUQ (7 << 22) /* queue to capture bpdu */ 168 #define PORT_CONFIG_RXCS (1 << 25) /* calculation Rx TCP checksum include pseudo header */ 169 170 #define MGE_PORT_EXT_CONFIG 0x404 171 #define MGE_MAC_ADDR_L 0x414 172 #define MGE_MAC_ADDR_H 0x418 173 174 #define MGE_SDMA_CONFIG 0x41c 175 #define MGE_SDMA_INT_ON_FRAME_BOUND (1 << 0) 176 #define MGE_SDMA_RX_BURST_SIZE(val) (((val) & 7) << 1) 177 #define MGE_SDMA_TX_BURST_SIZE(val) (((val) & 7) << 22) 178 #define MGE_SDMA_BURST_1_WORD 0x0 179 #define MGE_SDMA_BURST_2_WORD 0x1 180 #define MGE_SDMA_BURST_4_WORD 0x2 181 #define MGE_SDMA_BURST_8_WORD 0x3 182 #define MGE_SDMA_BURST_16_WORD 0x4 183 #define MGE_SDMA_RX_BYTE_SWAP (1 << 4) 184 #define MGE_SDMA_TX_BYTE_SWAP (1 << 5) 185 #define MGE_SDMA_DESC_SWAP_MODE (1 << 6) 186 #if defined(MGE_VER2) 187 #define MGE_SDMA_RX_IPG_MAX 0xFFFF 188 #define MGE_SDMA_RX_IPG(val) ((((val) & 0x8000) << 10) | \ 189 (((val) & 0x7fff) << 7)) 190 #else 191 #define MGE_SDMA_RX_IPG_MAX 0x3FFF 192 #define MGE_SDMA_RX_IPG(val) (((val) & 0x3fff) << 8) 193 #endif 194 195 196 #define MGE_PORT_SERIAL_CTRL 0x43c 197 #define PORT_SERIAL_ENABLE (1 << 0) /* serial port enable */ 198 #define PORT_SERIAL_FORCE_LINKUP (1 << 1) /* force link status to up */ 199 #define PORT_SERIAL_AUTONEG (1 << 2) /* enable autoneg for duplex mode */ 200 #define PORT_SERIAL_AUTONEG_FC (1 << 3) /* enable autoneg for FC */ 201 #define PORT_SERIAL_PAUSE_ADV (1 << 4) /* advertise symmetric FC in autoneg */ 202 #define PORT_SERIAL_FORCE_FC(val) (((val) & 3) << 5) /* pause enable & disable frames conf */ 203 #define PORT_SERIAL_NO_PAUSE_DIS 0x00 204 #define PORT_SERIAL_PAUSE_DIS 0x01 205 #define PORT_SERIAL_FORCE_BP(val) (((val) & 3) << 7) /* transmitting JAM configuration */ 206 #define PORT_SERIAL_NO_JAM 0x00 207 #define PORT_SERIAL_JAM 0x01 208 #define PORT_SERIAL_RES_BIT9 (1 << 9) 209 #define PORT_SERIAL_FORCE_LINK_FAIL (1 << 10) 210 #define PORT_SERIAL_SPEED_AUTONEG (1 << 13) 211 #define PORT_SERIAL_FORCE_DTE_ADV (1 << 14) 212 #define PORT_SERIAL_MRU(val) (((val) & 7) << 17) 213 #define PORT_SERIAL_MRU_1518 0x0 214 #define PORT_SERIAL_MRU_1522 0x1 215 #define PORT_SERIAL_MRU_1552 0x2 216 #define PORT_SERIAL_MRU_9022 0x3 217 #define PORT_SERIAL_MRU_9192 0x4 218 #define PORT_SERIAL_MRU_9700 0x5 219 #define PORT_SERIAL_FULL_DUPLEX (1 << 21) 220 #define PORT_SERIAL_FULL_DUPLEX_FC (1 << 22) 221 #define PORT_SERIAL_GMII_SPEED_1000 (1 << 23) 222 #define PORT_SERIAL_MII_SPEED_100 (1 << 24) 223 224 #define MGE_PORT_STATUS 0x444 225 #define MGE_STATUS_LINKUP (1 << 1) 226 #define MGE_STATUS_FULL_DUPLEX (1 << 2) 227 #define MGE_STATUS_FLOW_CONTROL (1 << 3) 228 #define MGE_STATUS_1000MB (1 << 4) 229 #define MGE_STATUS_100MB (1 << 5) 230 #define MGE_STATUS_TX_IN_PROG (1 << 7) 231 #define MGE_STATUS_TX_FIFO_EMPTY (1 << 10) 232 233 #define MGE_TX_QUEUE_CMD 0x448 234 #define MGE_ENABLE_TXQ (1 << 0) 235 #define MGE_DISABLE_TXQ (1 << 8) 236 237 /* 88F6281 only */ 238 #define MGE_PORT_SERIAL_CTRL1 0x44c 239 #define MGE_PCS_LOOPBACK (1 << 1) 240 #define MGE_RGMII_EN (1 << 3) 241 #define MGE_PORT_RESET (1 << 4) 242 #define MGE_CLK125_BYPASS (1 << 5) 243 #define MGE_INBAND_AUTONEG (1 << 6) 244 #define MGE_INBAND_AUTONEG_BYPASS (1 << 6) 245 #define MGE_INBAND_AUTONEG_RESTART (1 << 7) 246 #define MGE_1000BASEX (1 << 11) 247 #define MGE_BP_COLLISION_COUNT (1 << 15) 248 #define MGE_COLLISION_LIMIT(val) (((val) & 0x3f) << 16) 249 #define MGE_DROP_ODD_PREAMBLE (1 << 22) 250 251 #if defined(MGE_VER2) 252 #define MGE_MTU 0x4e8 253 #else 254 #define MGE_MTU 0x458 255 #endif 256 #define MGE_MTU_DEFAULT 0x0 257 258 #define MGE_PORT_INT_CAUSE 0x460 259 #define MGE_PORT_INT_MASK 0x468 260 #define MGE_PORT_INT_RX (1 << 0) 261 #define MGE_PORT_INT_EXTEND (1 << 1) 262 #define MGE_PORT_INT_RXQ0 (1 << 2) 263 #define MGE_PORT_INT_RXERR (1 << 10) 264 #define MGE_PORT_INT_RXERRQ0 (1 << 11) 265 #define MGE_PORT_INT_SUM (1 << 31) 266 267 #define MGE_PORT_INT_CAUSE_EXT 0x464 268 #define MGE_PORT_INT_MASK_EXT 0x46C 269 #define MGE_PORT_INT_EXT_TXBUF0 (1 << 0) 270 #define MGE_PORT_INT_EXT_TXERR0 (1 << 8) 271 #define MGE_PORT_INT_EXT_PHYSC (1 << 16) 272 #define MGE_PORT_INT_EXT_RXOR (1 << 18) 273 #define MGE_PORT_INT_EXT_TXUR (1 << 19) 274 #define MGE_PORT_INT_EXT_LC (1 << 20) 275 #define MGE_PORT_INT_EXT_IAR (1 << 23) 276 #define MGE_PORT_INT_EXT_SUM (1 << 31) 277 278 #define MGE_RX_FIFO_URGENT_TRSH 0x470 279 #define MGE_TX_FIFO_URGENT_TRSH 0x474 280 #if defined(MGE_VER2) 281 #define MGE_TX_FIFO_URGENT_TRSH_IPG_MAX 0xFFFF 282 #define MGE_TX_FIFO_URGENT_TRSH_IPG(vl) (((vl) & 0xFFFF) << 4) 283 #else 284 #define MGE_TX_FIFO_URGENT_TRSH_IPG_MAX 0x3FFF 285 #define MGE_TX_FIFO_URGENT_TRSH_IPG(vl) (((vl) & 0x3FFF) << 4) 286 #endif 287 288 #define MGE_FIXED_PRIO_CONF 0x4dc 289 #define MGE_FIXED_PRIO_EN(q) (1 << (q)) 290 291 #define MGE_RX_CUR_DESC_PTR(q) (0x60c + ((q)<<4)) 292 293 #define MGE_RX_QUEUE_CMD 0x680 294 #define MGE_ENABLE_RXQ(q) (1 << ((q) & 0x7)) 295 #define MGE_ENABLE_RXQ_ALL (0xff) 296 #define MGE_DISABLE_RXQ(q) (1 << (((q) & 0x7) + 8)) 297 #define MGE_DISABLE_RXQ_ALL (0xff00) 298 299 #define MGE_TX_CUR_DESC_PTR 0x6c0 300 301 #define MGE_TX_TOKEN_COUNT(q) (0x700 + ((q)<<4)) 302 #define MGE_TX_TOKEN_CONF(q) (0x704 + ((q)<<4)) 303 #define MGE_TX_TOKEN_Q0_DFLT 0x3fffffff 304 #define MGE_TX_TOKEN_Q1_7_DFLT 0x0 305 306 #define MGE_TX_ARBITER_CONF(q) (0x704 + ((q)<<4)) 307 #define MGE_TX_ARB_Q0_DFLT 0xff 308 #define MGE_TX_ARB_Q1_7_DFLT 0x0 309 310 #define MGE_MCAST_REG_NUMBER 64 311 #define MGE_DA_FILTER_SPEC_MCAST(i) (0x1400 + ((i) << 2)) 312 #define MGE_DA_FILTER_OTH_MCAST(i) (0x1500 + ((i) << 2)) 313 314 #define MGE_UCAST_REG_NUMBER 4 315 #define MGE_DA_FILTER_UCAST(i) (0x1600 + ((i) << 2)) 316 317 318 /* TX descriptor bits */ 319 #define MGE_TX_LLC_SNAP (1 << 9) 320 #define MGE_TX_NOT_FRAGMENT (1 << 10) 321 #define MGE_TX_VLAN_TAGGED (1 << 15) 322 #define MGE_TX_UDP (1 << 16) 323 #define MGE_TX_GEN_L4_CSUM (1 << 17) 324 #define MGE_TX_GEN_IP_CSUM (1 << 18) 325 #define MGE_TX_PADDING (1 << 19) 326 #define MGE_TX_LAST (1 << 20) 327 #define MGE_TX_FIRST (1 << 21) 328 #define MGE_TX_ETH_CRC (1 << 22) 329 #define MGE_TX_EN_INT (1 << 23) 330 331 #define MGE_TX_IP_HDR_SIZE(size) ((size << 11) & 0xFFFF) 332 333 /* RX descriptor bits */ 334 #define MGE_ERR_SUMMARY (1 << 0) 335 #define MGE_ERR_MASK (3 << 1) 336 #define MGE_RX_L4_PROTO_MASK (3 << 21) 337 #define MGE_RX_L4_PROTO_TCP (0 << 21) 338 #define MGE_RX_L4_PROTO_UDP (1 << 21) 339 #define MGE_RX_L3_IS_IP (1 << 24) 340 #define MGE_RX_IP_OK (1 << 25) 341 #define MGE_RX_DESC_LAST (1 << 26) 342 #define MGE_RX_DESC_FIRST (1 << 27) 343 #define MGE_RX_ENABLE_INT (1 << 29) 344 #define MGE_RX_L4_CSUM_OK (1 << 30) 345 #define MGE_DMA_OWNED (1 << 31) 346 347 #define MGE_RX_IP_FRAGMENT (1 << 2) 348 349 #define MGE_RX_L4_IS_TCP(status) ((status & MGE_RX_L4_PROTO_MASK) \ 350 == MGE_RX_L4_PROTO_TCP) 351 352 #define MGE_RX_L4_IS_UDP(status) ((status & MGE_RX_L4_PROTO_MASK) \ 353 == MGE_RX_L4_PROTO_UDP) 354 355 /* TX error codes */ 356 #define MGE_TX_ERROR_LC (0 << 1) /* Late collision */ 357 #define MGE_TX_ERROR_UR (1 << 1) /* Underrun error */ 358 #define MGE_TX_ERROR_RL (2 << 1) /* Excessive collision */ 359 360 /* RX error codes */ 361 #define MGE_RX_ERROR_CE (0 << 1) /* CRC error */ 362 #define MGE_RX_ERROR_OR (1 << 1) /* Overrun error */ 363 #define MGE_RX_ERROR_MF (2 << 1) /* Max frame lenght error */ 364 #define MGE_RX_ERROR_RE (3 << 1) /* Resource error */ 365 366 #endif /* __IF_MGE_H__ */ 367