1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 The FreeBSD Foundation, Inc. 5 * 6 * This driver was written by Gerald ND Aryeetey <gndaryee@uwaterloo.ca> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Microchip LAN7430/LAN7431 PCIe to Gigabit Ethernet Controller driver. 35 * 36 * Product information: 37 * LAN7430 https://www.microchip.com/en-us/product/LAN7430 38 * - Integrated IEEE 802.3 compliant PHY 39 * LAN7431 https://www.microchip.com/en-us/product/LAN7431 40 * - RGMII Interface 41 * 42 * This driver uses the iflib interface and the default 'ukphy' PHY driver. 43 * 44 * UNIMPLEMENTED FEATURES 45 * ---------------------- 46 * A number of features supported by LAN743X device are not yet implemented in 47 * this driver: 48 * 49 * - Multiple (up to 4) RX queues support 50 * - Just needs to remove asserts and malloc multiple `rx_ring_data` 51 * structs based on ncpus. 52 * - RX/TX Checksum Offloading support 53 * - VLAN support 54 * - Receive Packet Filtering (Multicast Perfect/Hash Address) support 55 * - Wake on LAN (WoL) support 56 * - TX LSO support 57 * - Receive Side Scaling (RSS) support 58 * - Debugging Capabilities: 59 * - Could include MAC statistics and 60 * error status registers in sysctl. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kdb.h> 67 #include <sys/kernel.h> 68 #include <sys/module.h> 69 #include <sys/rman.h> 70 #include <sys/socket.h> 71 #include <sys/sockio.h> 72 #include <machine/bus.h> 73 #include <machine/resource.h> 74 75 #include <net/ethernet.h> 76 #include <net/if.h> 77 #include <net/if_var.h> 78 #include <net/if_types.h> 79 #include <net/if_media.h> 80 #include <net/iflib.h> 81 82 #include <dev/mgb/if_mgb.h> 83 #include <dev/mii/mii.h> 84 #include <dev/mii/miivar.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 88 #include "ifdi_if.h" 89 #include "miibus_if.h" 90 91 static pci_vendor_info_t mgb_vendor_info_array[] = { 92 PVID(MGB_MICROCHIP_VENDOR_ID, MGB_LAN7430_DEVICE_ID, 93 "Microchip LAN7430 PCIe Gigabit Ethernet Controller"), 94 PVID(MGB_MICROCHIP_VENDOR_ID, MGB_LAN7431_DEVICE_ID, 95 "Microchip LAN7431 PCIe Gigabit Ethernet Controller"), 96 PVID_END 97 }; 98 99 /* Device methods */ 100 static device_register_t mgb_register; 101 102 /* IFLIB methods */ 103 static ifdi_attach_pre_t mgb_attach_pre; 104 static ifdi_attach_post_t mgb_attach_post; 105 static ifdi_detach_t mgb_detach; 106 107 static ifdi_tx_queues_alloc_t mgb_tx_queues_alloc; 108 static ifdi_rx_queues_alloc_t mgb_rx_queues_alloc; 109 static ifdi_queues_free_t mgb_queues_free; 110 111 static ifdi_init_t mgb_init; 112 static ifdi_stop_t mgb_stop; 113 114 static ifdi_msix_intr_assign_t mgb_msix_intr_assign; 115 static ifdi_tx_queue_intr_enable_t mgb_tx_queue_intr_enable; 116 static ifdi_rx_queue_intr_enable_t mgb_rx_queue_intr_enable; 117 static ifdi_intr_enable_t mgb_intr_enable_all; 118 static ifdi_intr_disable_t mgb_intr_disable_all; 119 120 /* IFLIB_TXRX methods */ 121 static int mgb_isc_txd_encap(void *, 122 if_pkt_info_t); 123 static void mgb_isc_txd_flush(void *, 124 uint16_t, qidx_t); 125 static int mgb_isc_txd_credits_update(void *, 126 uint16_t, bool); 127 static int mgb_isc_rxd_available(void *, 128 uint16_t, qidx_t, qidx_t); 129 static int mgb_isc_rxd_pkt_get(void *, 130 if_rxd_info_t); 131 static void mgb_isc_rxd_refill(void *, 132 if_rxd_update_t); 133 static void mgb_isc_rxd_flush(void *, 134 uint16_t, uint8_t, qidx_t); 135 136 /* Interrupts */ 137 static driver_filter_t mgb_legacy_intr; 138 static driver_filter_t mgb_admin_intr; 139 static driver_filter_t mgb_rxq_intr; 140 static bool mgb_intr_test(struct mgb_softc *); 141 142 /* MII methods */ 143 static miibus_readreg_t mgb_miibus_readreg; 144 static miibus_writereg_t mgb_miibus_writereg; 145 static miibus_linkchg_t mgb_miibus_linkchg; 146 static miibus_statchg_t mgb_miibus_statchg; 147 148 static int mgb_media_change(if_t); 149 static void mgb_media_status(if_t, 150 struct ifmediareq *); 151 152 /* Helper/Test functions */ 153 static int mgb_test_bar(struct mgb_softc *); 154 static int mgb_alloc_regs(struct mgb_softc *); 155 static int mgb_release_regs(struct mgb_softc *); 156 157 static void mgb_get_ethaddr(struct mgb_softc *, 158 struct ether_addr *); 159 160 static int mgb_wait_for_bits(struct mgb_softc *, 161 int, int, int); 162 163 /* H/W init, reset and teardown helpers */ 164 static int mgb_hw_init(struct mgb_softc *); 165 static int mgb_hw_teardown(struct mgb_softc *); 166 static int mgb_hw_reset(struct mgb_softc *); 167 static int mgb_mac_init(struct mgb_softc *); 168 static int mgb_dmac_reset(struct mgb_softc *); 169 static int mgb_phy_reset(struct mgb_softc *); 170 171 static int mgb_dma_init(struct mgb_softc *); 172 static int mgb_dma_tx_ring_init(struct mgb_softc *, 173 int); 174 static int mgb_dma_rx_ring_init(struct mgb_softc *, 175 int); 176 177 static int mgb_dmac_control(struct mgb_softc *, 178 int, int, enum mgb_dmac_cmd); 179 static int mgb_fct_control(struct mgb_softc *, 180 int, int, enum mgb_fct_cmd); 181 182 /********************************************************************* 183 * FreeBSD Device Interface Entry Points 184 *********************************************************************/ 185 186 static device_method_t mgb_methods[] = { 187 /* Device interface */ 188 DEVMETHOD(device_register, mgb_register), 189 DEVMETHOD(device_probe, iflib_device_probe), 190 DEVMETHOD(device_attach, iflib_device_attach), 191 DEVMETHOD(device_detach, iflib_device_detach), 192 DEVMETHOD(device_shutdown, iflib_device_shutdown), 193 DEVMETHOD(device_suspend, iflib_device_suspend), 194 DEVMETHOD(device_resume, iflib_device_resume), 195 196 /* MII Interface */ 197 DEVMETHOD(miibus_readreg, mgb_miibus_readreg), 198 DEVMETHOD(miibus_writereg, mgb_miibus_writereg), 199 DEVMETHOD(miibus_linkchg, mgb_miibus_linkchg), 200 DEVMETHOD(miibus_statchg, mgb_miibus_statchg), 201 202 DEVMETHOD_END 203 }; 204 205 static driver_t mgb_driver = { 206 "mgb", mgb_methods, sizeof(struct mgb_softc) 207 }; 208 209 static devclass_t mgb_devclass; 210 DRIVER_MODULE(mgb, pci, mgb_driver, mgb_devclass, NULL, NULL); 211 IFLIB_PNP_INFO(pci, mgb, mgb_vendor_info_array); 212 MODULE_VERSION(mgb, 1); 213 214 #if 0 /* MIIBUS_DEBUG */ 215 /* If MIIBUS debug stuff is in attach then order matters. Use below instead. */ 216 DRIVER_MODULE_ORDERED(miibus, mgb, miibus_driver, miibus_devclass, NULL, NULL, 217 SI_ORDER_ANY); 218 #endif /* MIIBUS_DEBUG */ 219 DRIVER_MODULE(miibus, mgb, miibus_driver, miibus_devclass, NULL, NULL); 220 221 MODULE_DEPEND(mgb, pci, 1, 1, 1); 222 MODULE_DEPEND(mgb, ether, 1, 1, 1); 223 MODULE_DEPEND(mgb, miibus, 1, 1, 1); 224 MODULE_DEPEND(mgb, iflib, 1, 1, 1); 225 226 static device_method_t mgb_iflib_methods[] = { 227 DEVMETHOD(ifdi_attach_pre, mgb_attach_pre), 228 DEVMETHOD(ifdi_attach_post, mgb_attach_post), 229 DEVMETHOD(ifdi_detach, mgb_detach), 230 231 DEVMETHOD(ifdi_init, mgb_init), 232 DEVMETHOD(ifdi_stop, mgb_stop), 233 234 DEVMETHOD(ifdi_tx_queues_alloc, mgb_tx_queues_alloc), 235 DEVMETHOD(ifdi_rx_queues_alloc, mgb_rx_queues_alloc), 236 DEVMETHOD(ifdi_queues_free, mgb_queues_free), 237 238 DEVMETHOD(ifdi_msix_intr_assign, mgb_msix_intr_assign), 239 DEVMETHOD(ifdi_tx_queue_intr_enable, mgb_tx_queue_intr_enable), 240 DEVMETHOD(ifdi_rx_queue_intr_enable, mgb_rx_queue_intr_enable), 241 DEVMETHOD(ifdi_intr_enable, mgb_intr_enable_all), 242 DEVMETHOD(ifdi_intr_disable, mgb_intr_disable_all), 243 244 #if 0 /* Not yet implemented IFLIB methods */ 245 /* 246 * Set multicast addresses, mtu and promiscuous mode 247 */ 248 DEVMETHOD(ifdi_multi_set, mgb_multi_set), 249 DEVMETHOD(ifdi_mtu_set, mgb_mtu_set), 250 DEVMETHOD(ifdi_promisc_set, mgb_promisc_set), 251 252 /* 253 * Needed for VLAN support 254 */ 255 DEVMETHOD(ifdi_vlan_register, mgb_vlan_register), 256 DEVMETHOD(ifdi_vlan_unregister, mgb_vlan_unregister), 257 258 /* 259 * Needed for WOL support 260 * at the very least. 261 */ 262 DEVMETHOD(ifdi_shutdown, mgb_shutdown), 263 DEVMETHOD(ifdi_suspend, mgb_suspend), 264 DEVMETHOD(ifdi_resume, mgb_resume), 265 #endif /* UNUSED_IFLIB_METHODS */ 266 DEVMETHOD_END 267 }; 268 269 static driver_t mgb_iflib_driver = { 270 "mgb", mgb_iflib_methods, sizeof(struct mgb_softc) 271 }; 272 273 static struct if_txrx mgb_txrx = { 274 .ift_txd_encap = mgb_isc_txd_encap, 275 .ift_txd_flush = mgb_isc_txd_flush, 276 .ift_txd_credits_update = mgb_isc_txd_credits_update, 277 .ift_rxd_available = mgb_isc_rxd_available, 278 .ift_rxd_pkt_get = mgb_isc_rxd_pkt_get, 279 .ift_rxd_refill = mgb_isc_rxd_refill, 280 .ift_rxd_flush = mgb_isc_rxd_flush, 281 282 .ift_legacy_intr = mgb_legacy_intr 283 }; 284 285 static struct if_shared_ctx mgb_sctx_init = { 286 .isc_magic = IFLIB_MAGIC, 287 288 .isc_q_align = PAGE_SIZE, 289 .isc_admin_intrcnt = 1, 290 .isc_flags = IFLIB_DRIVER_MEDIA /* | IFLIB_HAS_RXCQ | IFLIB_HAS_TXCQ*/, 291 292 .isc_vendor_info = mgb_vendor_info_array, 293 .isc_driver_version = "1", 294 .isc_driver = &mgb_iflib_driver, 295 /* 2 queues per set for TX and RX (ring queue, head writeback queue) */ 296 .isc_ntxqs = 2, 297 298 .isc_tx_maxsize = MGB_DMA_MAXSEGS * MCLBYTES, 299 /* .isc_tx_nsegments = MGB_DMA_MAXSEGS, */ 300 .isc_tx_maxsegsize = MCLBYTES, 301 302 .isc_ntxd_min = {1, 1}, /* Will want to make this bigger */ 303 .isc_ntxd_max = {MGB_DMA_RING_SIZE, 1}, 304 .isc_ntxd_default = {MGB_DMA_RING_SIZE, 1}, 305 306 .isc_nrxqs = 2, 307 308 .isc_rx_maxsize = MCLBYTES, 309 .isc_rx_nsegments = 1, 310 .isc_rx_maxsegsize = MCLBYTES, 311 312 .isc_nrxd_min = {1, 1}, /* Will want to make this bigger */ 313 .isc_nrxd_max = {MGB_DMA_RING_SIZE, 1}, 314 .isc_nrxd_default = {MGB_DMA_RING_SIZE, 1}, 315 316 .isc_nfl = 1, /*one free list since there is only one queue */ 317 #if 0 /* UNUSED_CTX */ 318 319 .isc_tso_maxsize = MGB_TSO_MAXSIZE + sizeof(struct ether_vlan_header), 320 .isc_tso_maxsegsize = MGB_TX_MAXSEGSIZE, 321 #endif /* UNUSED_CTX */ 322 }; 323 324 /*********************************************************************/ 325 326 static void * 327 mgb_register(device_t dev) 328 { 329 330 return (&mgb_sctx_init); 331 } 332 333 static int 334 mgb_attach_pre(if_ctx_t ctx) 335 { 336 struct mgb_softc *sc; 337 if_softc_ctx_t scctx; 338 int error, phyaddr, rid; 339 struct ether_addr hwaddr; 340 struct mii_data *miid; 341 342 sc = iflib_get_softc(ctx); 343 sc->ctx = ctx; 344 sc->dev = iflib_get_dev(ctx); 345 scctx = iflib_get_softc_ctx(ctx); 346 347 /* IFLIB required setup */ 348 scctx->isc_txrx = &mgb_txrx; 349 scctx->isc_tx_nsegments = MGB_DMA_MAXSEGS; 350 /* Ring desc queues */ 351 scctx->isc_txqsizes[0] = sizeof(struct mgb_ring_desc) * 352 scctx->isc_ntxd[0]; 353 scctx->isc_rxqsizes[0] = sizeof(struct mgb_ring_desc) * 354 scctx->isc_nrxd[0]; 355 356 /* Head WB queues */ 357 scctx->isc_txqsizes[1] = sizeof(uint32_t) * scctx->isc_ntxd[1]; 358 scctx->isc_rxqsizes[1] = sizeof(uint32_t) * scctx->isc_nrxd[1]; 359 360 /* XXX: Must have 1 txqset, but can have up to 4 rxqsets */ 361 scctx->isc_nrxqsets = 1; 362 scctx->isc_ntxqsets = 1; 363 364 /* scctx->isc_tx_csum_flags = (CSUM_TCP | CSUM_UDP) | 365 (CSUM_TCP_IPV6 | CSUM_UDP_IPV6) | CSUM_TSO */ 366 scctx->isc_tx_csum_flags = 0; 367 scctx->isc_capabilities = scctx->isc_capenable = 0; 368 #if 0 369 /* 370 * CSUM, TSO and VLAN support are TBD 371 */ 372 IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6 | 373 IFCAP_TSO4 | IFCAP_TSO6 | 374 IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 | 375 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 376 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | 377 IFCAP_JUMBO_MTU; 378 scctx->isc_capabilities |= IFCAP_LRO | IFCAP_VLAN_HWFILTER; 379 #endif 380 381 /* get the BAR */ 382 error = mgb_alloc_regs(sc); 383 if (error != 0) { 384 device_printf(sc->dev, 385 "Unable to allocate bus resource: registers.\n"); 386 goto fail; 387 } 388 389 error = mgb_test_bar(sc); 390 if (error != 0) 391 goto fail; 392 393 error = mgb_hw_init(sc); 394 if (error != 0) { 395 device_printf(sc->dev, 396 "MGB device init failed. (err: %d)\n", error); 397 goto fail; 398 } 399 400 switch (pci_get_device(sc->dev)) { 401 case MGB_LAN7430_DEVICE_ID: 402 phyaddr = 1; 403 break; 404 case MGB_LAN7431_DEVICE_ID: 405 default: 406 phyaddr = MII_PHY_ANY; 407 break; 408 } 409 410 /* XXX: Would be nice(r) if locked methods were here */ 411 error = mii_attach(sc->dev, &sc->miibus, iflib_get_ifp(ctx), 412 mgb_media_change, mgb_media_status, 413 BMSR_DEFCAPMASK, phyaddr, MII_OFFSET_ANY, MIIF_DOPAUSE); 414 if (error != 0) { 415 device_printf(sc->dev, "Failed to attach MII interface\n"); 416 goto fail; 417 } 418 419 miid = device_get_softc(sc->miibus); 420 scctx->isc_media = &miid->mii_media; 421 422 scctx->isc_msix_bar = pci_msix_table_bar(sc->dev); 423 /** Setup PBA BAR **/ 424 rid = pci_msix_pba_bar(sc->dev); 425 if (rid != scctx->isc_msix_bar) { 426 sc->pba = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 427 &rid, RF_ACTIVE); 428 if (sc->pba == NULL) { 429 error = ENXIO; 430 device_printf(sc->dev, "Failed to setup PBA BAR\n"); 431 goto fail; 432 } 433 } 434 435 mgb_get_ethaddr(sc, &hwaddr); 436 if (ETHER_IS_BROADCAST(hwaddr.octet) || 437 ETHER_IS_MULTICAST(hwaddr.octet) || 438 ETHER_IS_ZERO(hwaddr.octet)) 439 ether_gen_addr(iflib_get_ifp(ctx), &hwaddr); 440 441 /* 442 * XXX: if the MAC address was generated the linux driver 443 * writes it back to the device. 444 */ 445 iflib_set_mac(ctx, hwaddr.octet); 446 447 /* Map all vectors to vector 0 (admin interrupts) by default. */ 448 CSR_WRITE_REG(sc, MGB_INTR_VEC_RX_MAP, 0); 449 CSR_WRITE_REG(sc, MGB_INTR_VEC_TX_MAP, 0); 450 CSR_WRITE_REG(sc, MGB_INTR_VEC_OTHER_MAP, 0); 451 452 return (0); 453 454 fail: 455 mgb_detach(ctx); 456 return (error); 457 } 458 459 static int 460 mgb_attach_post(if_ctx_t ctx) 461 { 462 struct mgb_softc *sc; 463 464 sc = iflib_get_softc(ctx); 465 466 device_printf(sc->dev, "Interrupt test: %s\n", 467 (mgb_intr_test(sc) ? "PASS" : "FAIL")); 468 469 return (0); 470 } 471 472 static int 473 mgb_detach(if_ctx_t ctx) 474 { 475 struct mgb_softc *sc; 476 int error; 477 478 sc = iflib_get_softc(ctx); 479 480 /* XXX: Should report errors but still detach everything. */ 481 error = mgb_hw_teardown(sc); 482 483 /* Release IRQs */ 484 iflib_irq_free(ctx, &sc->rx_irq); 485 iflib_irq_free(ctx, &sc->admin_irq); 486 487 if (sc->miibus != NULL) 488 device_delete_child(sc->dev, sc->miibus); 489 490 if (sc->pba != NULL) 491 error = bus_release_resource(sc->dev, SYS_RES_MEMORY, 492 rman_get_rid(sc->pba), sc->pba); 493 sc->pba = NULL; 494 495 error = mgb_release_regs(sc); 496 497 return (error); 498 } 499 500 static int 501 mgb_media_change(if_t ifp) 502 { 503 struct mii_data *miid; 504 struct mii_softc *miisc; 505 struct mgb_softc *sc; 506 if_ctx_t ctx; 507 int needs_reset; 508 509 ctx = if_getsoftc(ifp); 510 sc = iflib_get_softc(ctx); 511 miid = device_get_softc(sc->miibus); 512 LIST_FOREACH(miisc, &miid->mii_phys, mii_list) 513 PHY_RESET(miisc); 514 515 needs_reset = mii_mediachg(miid); 516 if (needs_reset != 0) 517 ifp->if_init(ctx); 518 return (needs_reset); 519 } 520 521 static void 522 mgb_media_status(if_t ifp, struct ifmediareq *ifmr) 523 { 524 struct mgb_softc *sc; 525 struct mii_data *miid; 526 527 sc = iflib_get_softc(if_getsoftc(ifp)); 528 miid = device_get_softc(sc->miibus); 529 if ((if_getflags(ifp) & IFF_UP) == 0) 530 return; 531 532 mii_pollstat(miid); 533 ifmr->ifm_active = miid->mii_media_active; 534 ifmr->ifm_status = miid->mii_media_status; 535 } 536 537 static int 538 mgb_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, 539 int ntxqsets) 540 { 541 struct mgb_softc *sc; 542 struct mgb_ring_data *rdata; 543 int q; 544 545 sc = iflib_get_softc(ctx); 546 KASSERT(ntxqsets == 1, ("ntxqsets = %d", ntxqsets)); 547 rdata = &sc->tx_ring_data; 548 for (q = 0; q < ntxqsets; q++) { 549 KASSERT(ntxqs == 2, ("ntxqs = %d", ntxqs)); 550 /* Ring */ 551 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * ntxqs + 0]; 552 rdata->ring_bus_addr = paddrs[q * ntxqs + 0]; 553 554 /* Head WB */ 555 rdata->head_wb = (uint32_t *) vaddrs[q * ntxqs + 1]; 556 rdata->head_wb_bus_addr = paddrs[q * ntxqs + 1]; 557 } 558 return (0); 559 } 560 561 static int 562 mgb_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, 563 int nrxqsets) 564 { 565 struct mgb_softc *sc; 566 struct mgb_ring_data *rdata; 567 int q; 568 569 sc = iflib_get_softc(ctx); 570 KASSERT(nrxqsets == 1, ("nrxqsets = %d", nrxqsets)); 571 rdata = &sc->rx_ring_data; 572 for (q = 0; q < nrxqsets; q++) { 573 KASSERT(nrxqs == 2, ("nrxqs = %d", nrxqs)); 574 /* Ring */ 575 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * nrxqs + 0]; 576 rdata->ring_bus_addr = paddrs[q * nrxqs + 0]; 577 578 /* Head WB */ 579 rdata->head_wb = (uint32_t *) vaddrs[q * nrxqs + 1]; 580 rdata->head_wb_bus_addr = paddrs[q * nrxqs + 1]; 581 } 582 return (0); 583 } 584 585 static void 586 mgb_queues_free(if_ctx_t ctx) 587 { 588 struct mgb_softc *sc; 589 590 sc = iflib_get_softc(ctx); 591 592 memset(&sc->rx_ring_data, 0, sizeof(struct mgb_ring_data)); 593 memset(&sc->tx_ring_data, 0, sizeof(struct mgb_ring_data)); 594 } 595 596 static void 597 mgb_init(if_ctx_t ctx) 598 { 599 struct mgb_softc *sc; 600 struct mii_data *miid; 601 int error; 602 603 sc = iflib_get_softc(ctx); 604 miid = device_get_softc(sc->miibus); 605 device_printf(sc->dev, "running init ...\n"); 606 607 mgb_dma_init(sc); 608 609 /* XXX: Turn off perfect filtering, turn on (broad|multi|uni)cast rx */ 610 CSR_CLEAR_REG(sc, MGB_RFE_CTL, MGB_RFE_ALLOW_PERFECT_FILTER); 611 CSR_UPDATE_REG(sc, MGB_RFE_CTL, 612 MGB_RFE_ALLOW_BROADCAST | 613 MGB_RFE_ALLOW_MULTICAST | 614 MGB_RFE_ALLOW_UNICAST); 615 616 error = mii_mediachg(miid); 617 /* Not much we can do if this fails. */ 618 if (error) 619 device_printf(sc->dev, "%s: mii_mediachg returned %d", __func__, 620 error); 621 } 622 623 #ifdef DEBUG 624 static void 625 mgb_dump_some_stats(struct mgb_softc *sc) 626 { 627 int i; 628 int first_stat = 0x1200; 629 int last_stat = 0x12FC; 630 631 for (i = first_stat; i <= last_stat; i += 4) 632 if (CSR_READ_REG(sc, i) != 0) 633 device_printf(sc->dev, "0x%04x: 0x%08x\n", i, 634 CSR_READ_REG(sc, i)); 635 char *stat_names[] = { 636 "MAC_ERR_STS ", 637 "FCT_INT_STS ", 638 "DMAC_CFG ", 639 "DMAC_CMD ", 640 "DMAC_INT_STS ", 641 "DMAC_INT_EN ", 642 "DMAC_RX_ERR_STS0 ", 643 "DMAC_RX_ERR_STS1 ", 644 "DMAC_RX_ERR_STS2 ", 645 "DMAC_RX_ERR_STS3 ", 646 "INT_STS ", 647 "INT_EN ", 648 "INT_VEC_EN ", 649 "INT_VEC_MAP0 ", 650 "INT_VEC_MAP1 ", 651 "INT_VEC_MAP2 ", 652 "TX_HEAD0", 653 "TX_TAIL0", 654 "DMAC_TX_ERR_STS0 ", 655 NULL 656 }; 657 int stats[] = { 658 0x114, 659 0xA0, 660 0xC00, 661 0xC0C, 662 0xC10, 663 0xC14, 664 0xC60, 665 0xCA0, 666 0xCE0, 667 0xD20, 668 0x780, 669 0x788, 670 0x794, 671 0x7A0, 672 0x7A4, 673 0x780, 674 0xD58, 675 0xD5C, 676 0xD60, 677 0x0 678 }; 679 i = 0; 680 printf("==============================\n"); 681 while (stats[i++]) 682 device_printf(sc->dev, "%s at offset 0x%04x = 0x%08x\n", 683 stat_names[i - 1], stats[i - 1], 684 CSR_READ_REG(sc, stats[i - 1])); 685 printf("==== TX RING DESCS ====\n"); 686 for (i = 0; i < MGB_DMA_RING_SIZE; i++) 687 device_printf(sc->dev, "ring[%d].data0=0x%08x\n" 688 "ring[%d].data1=0x%08x\n" 689 "ring[%d].data2=0x%08x\n" 690 "ring[%d].data3=0x%08x\n", 691 i, sc->tx_ring_data.ring[i].ctl, 692 i, sc->tx_ring_data.ring[i].addr.low, 693 i, sc->tx_ring_data.ring[i].addr.high, 694 i, sc->tx_ring_data.ring[i].sts); 695 device_printf(sc->dev, "==== DUMP_TX_DMA_RAM ====\n"); 696 CSR_WRITE_REG(sc, 0x24, 0xF); // DP_SEL & TX_RAM_0 697 for (i = 0; i < 128; i++) { 698 CSR_WRITE_REG(sc, 0x2C, i); // DP_ADDR 699 700 CSR_WRITE_REG(sc, 0x28, 0); // DP_CMD 701 702 while ((CSR_READ_REG(sc, 0x24) & 0x80000000) == 0) // DP_SEL & READY 703 DELAY(1000); 704 705 device_printf(sc->dev, "DMAC_TX_RAM_0[%u]=%08x\n", i, 706 CSR_READ_REG(sc, 0x30)); // DP_DATA 707 } 708 } 709 #endif 710 711 static void 712 mgb_stop(if_ctx_t ctx) 713 { 714 struct mgb_softc *sc ; 715 if_softc_ctx_t scctx; 716 int i; 717 718 sc = iflib_get_softc(ctx); 719 scctx = iflib_get_softc_ctx(ctx); 720 721 /* XXX: Could potentially timeout */ 722 for (i = 0; i < scctx->isc_nrxqsets; i++) { 723 mgb_dmac_control(sc, MGB_DMAC_RX_START, 0, DMAC_STOP); 724 mgb_fct_control(sc, MGB_FCT_RX_CTL, 0, FCT_DISABLE); 725 } 726 for (i = 0; i < scctx->isc_ntxqsets; i++) { 727 mgb_dmac_control(sc, MGB_DMAC_TX_START, 0, DMAC_STOP); 728 mgb_fct_control(sc, MGB_FCT_TX_CTL, 0, FCT_DISABLE); 729 } 730 } 731 732 static int 733 mgb_legacy_intr(void *xsc) 734 { 735 struct mgb_softc *sc; 736 737 sc = xsc; 738 iflib_admin_intr_deferred(sc->ctx); 739 return (FILTER_HANDLED); 740 } 741 742 static int 743 mgb_rxq_intr(void *xsc) 744 { 745 struct mgb_softc *sc; 746 if_softc_ctx_t scctx; 747 uint32_t intr_sts, intr_en; 748 int qidx; 749 750 sc = xsc; 751 scctx = iflib_get_softc_ctx(sc->ctx); 752 753 intr_sts = CSR_READ_REG(sc, MGB_INTR_STS); 754 intr_en = CSR_READ_REG(sc, MGB_INTR_ENBL_SET); 755 intr_sts &= intr_en; 756 757 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) { 758 if ((intr_sts & MGB_INTR_STS_RX(qidx))){ 759 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, 760 MGB_INTR_STS_RX(qidx)); 761 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_RX(qidx)); 762 } 763 } 764 return (FILTER_SCHEDULE_THREAD); 765 } 766 767 static int 768 mgb_admin_intr(void *xsc) 769 { 770 struct mgb_softc *sc; 771 if_softc_ctx_t scctx; 772 uint32_t intr_sts, intr_en; 773 int qidx; 774 775 sc = xsc; 776 scctx = iflib_get_softc_ctx(sc->ctx); 777 778 intr_sts = CSR_READ_REG(sc, MGB_INTR_STS); 779 intr_en = CSR_READ_REG(sc, MGB_INTR_ENBL_SET); 780 intr_sts &= intr_en; 781 782 /* 783 * NOTE: Debugging printfs here 784 * will likely cause interrupt test failure. 785 */ 786 787 /* TODO: shouldn't continue if suspended */ 788 if ((intr_sts & MGB_INTR_STS_ANY) == 0) { 789 device_printf(sc->dev, "non-mgb interrupt triggered.\n"); 790 return (FILTER_SCHEDULE_THREAD); 791 } 792 if ((intr_sts & MGB_INTR_STS_TEST) != 0) { 793 sc->isr_test_flag = true; 794 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST); 795 return (FILTER_HANDLED); 796 } 797 if ((intr_sts & MGB_INTR_STS_RX_ANY) != 0) { 798 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) { 799 if ((intr_sts & MGB_INTR_STS_RX(qidx))){ 800 iflib_rx_intr_deferred(sc->ctx, qidx); 801 } 802 } 803 return (FILTER_HANDLED); 804 } 805 /* XXX: TX interrupts should not occur */ 806 if ((intr_sts & MGB_INTR_STS_TX_ANY) != 0) { 807 for (qidx = 0; qidx < scctx->isc_ntxqsets; qidx++) { 808 if ((intr_sts & MGB_INTR_STS_RX(qidx))) { 809 /* clear the interrupt sts and run handler */ 810 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, 811 MGB_INTR_STS_TX(qidx)); 812 CSR_WRITE_REG(sc, MGB_INTR_STS, 813 MGB_INTR_STS_TX(qidx)); 814 iflib_tx_intr_deferred(sc->ctx, qidx); 815 } 816 } 817 return (FILTER_HANDLED); 818 } 819 820 return (FILTER_SCHEDULE_THREAD); 821 } 822 823 static int 824 mgb_msix_intr_assign(if_ctx_t ctx, int msix) 825 { 826 struct mgb_softc *sc; 827 if_softc_ctx_t scctx; 828 int error, i, vectorid; 829 char irq_name[16]; 830 831 sc = iflib_get_softc(ctx); 832 scctx = iflib_get_softc_ctx(ctx); 833 834 KASSERT(scctx->isc_nrxqsets == 1 && scctx->isc_ntxqsets == 1, 835 ("num rxqsets/txqsets != 1 ")); 836 837 /* 838 * First vector should be admin interrupts, others vectors are TX/RX 839 * 840 * RIDs start at 1, and vector ids start at 0. 841 */ 842 vectorid = 0; 843 error = iflib_irq_alloc_generic(ctx, &sc->admin_irq, vectorid + 1, 844 IFLIB_INTR_ADMIN, mgb_admin_intr, sc, 0, "admin"); 845 if (error) { 846 device_printf(sc->dev, 847 "Failed to register admin interrupt handler\n"); 848 return (error); 849 } 850 851 for (i = 0; i < scctx->isc_nrxqsets; i++) { 852 vectorid++; 853 snprintf(irq_name, sizeof(irq_name), "rxq%d", i); 854 error = iflib_irq_alloc_generic(ctx, &sc->rx_irq, vectorid + 1, 855 IFLIB_INTR_RXTX, mgb_rxq_intr, sc, i, irq_name); 856 if (error) { 857 device_printf(sc->dev, 858 "Failed to register rxq %d interrupt handler\n", i); 859 return (error); 860 } 861 CSR_UPDATE_REG(sc, MGB_INTR_VEC_RX_MAP, 862 MGB_INTR_VEC_MAP(vectorid, i)); 863 } 864 865 /* Not actually mapping hw TX interrupts ... */ 866 for (i = 0; i < scctx->isc_ntxqsets; i++) { 867 snprintf(irq_name, sizeof(irq_name), "txq%d", i); 868 iflib_softirq_alloc_generic(ctx, NULL, IFLIB_INTR_TX, NULL, i, 869 irq_name); 870 } 871 872 return (0); 873 } 874 875 static void 876 mgb_intr_enable_all(if_ctx_t ctx) 877 { 878 struct mgb_softc *sc; 879 if_softc_ctx_t scctx; 880 int i, dmac_enable = 0, intr_sts = 0, vec_en = 0; 881 882 sc = iflib_get_softc(ctx); 883 scctx = iflib_get_softc_ctx(ctx); 884 intr_sts |= MGB_INTR_STS_ANY; 885 vec_en |= MGB_INTR_STS_ANY; 886 887 for (i = 0; i < scctx->isc_nrxqsets; i++) { 888 intr_sts |= MGB_INTR_STS_RX(i); 889 dmac_enable |= MGB_DMAC_RX_INTR_ENBL(i); 890 vec_en |= MGB_INTR_RX_VEC_STS(i); 891 } 892 893 /* TX interrupts aren't needed ... */ 894 895 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, intr_sts); 896 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, vec_en); 897 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, dmac_enable); 898 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, dmac_enable); 899 } 900 901 static void 902 mgb_intr_disable_all(if_ctx_t ctx) 903 { 904 struct mgb_softc *sc; 905 906 sc = iflib_get_softc(ctx); 907 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, UINT32_MAX); 908 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_CLR, UINT32_MAX); 909 CSR_WRITE_REG(sc, MGB_INTR_STS, UINT32_MAX); 910 911 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_CLR, UINT32_MAX); 912 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, UINT32_MAX); 913 } 914 915 static int 916 mgb_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 917 { 918 /* called after successful rx isr */ 919 struct mgb_softc *sc; 920 921 sc = iflib_get_softc(ctx); 922 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, MGB_INTR_RX_VEC_STS(qid)); 923 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, MGB_INTR_STS_RX(qid)); 924 925 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, MGB_DMAC_RX_INTR_ENBL(qid)); 926 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, MGB_DMAC_RX_INTR_ENBL(qid)); 927 return (0); 928 } 929 930 static int 931 mgb_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 932 { 933 /* XXX: not called (since tx interrupts not used) */ 934 struct mgb_softc *sc; 935 936 sc = iflib_get_softc(ctx); 937 938 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, MGB_INTR_STS_TX(qid)); 939 940 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, MGB_DMAC_TX_INTR_ENBL(qid)); 941 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, MGB_DMAC_TX_INTR_ENBL(qid)); 942 return (0); 943 } 944 945 static bool 946 mgb_intr_test(struct mgb_softc *sc) 947 { 948 int i; 949 950 sc->isr_test_flag = false; 951 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST); 952 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, MGB_INTR_STS_ANY); 953 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, 954 MGB_INTR_STS_ANY | MGB_INTR_STS_TEST); 955 CSR_WRITE_REG(sc, MGB_INTR_SET, MGB_INTR_STS_TEST); 956 if (sc->isr_test_flag) 957 return (true); 958 for (i = 0; i < MGB_TIMEOUT; i++) { 959 DELAY(10); 960 if (sc->isr_test_flag) 961 break; 962 } 963 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, MGB_INTR_STS_TEST); 964 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST); 965 return (sc->isr_test_flag); 966 } 967 968 static int 969 mgb_isc_txd_encap(void *xsc , if_pkt_info_t ipi) 970 { 971 struct mgb_softc *sc; 972 if_softc_ctx_t scctx; 973 struct mgb_ring_data *rdata; 974 struct mgb_ring_desc *txd; 975 bus_dma_segment_t *segs; 976 qidx_t pidx, nsegs; 977 int i; 978 979 KASSERT(ipi->ipi_qsidx == 0, 980 ("tried to refill TX Channel %d.\n", ipi->ipi_qsidx)); 981 sc = xsc; 982 scctx = iflib_get_softc_ctx(sc->ctx); 983 rdata = &sc->tx_ring_data; 984 985 pidx = ipi->ipi_pidx; 986 segs = ipi->ipi_segs; 987 nsegs = ipi->ipi_nsegs; 988 989 /* For each seg, create a descriptor */ 990 for (i = 0; i < nsegs; ++i) { 991 KASSERT(nsegs == 1, ("Multisegment packet !!!!!\n")); 992 txd = &rdata->ring[pidx]; 993 txd->ctl = htole32( 994 (segs[i].ds_len & MGB_DESC_CTL_BUFLEN_MASK ) | 995 /* 996 * XXX: This will be wrong in the multipacket case 997 * I suspect FS should be for the first packet and 998 * LS should be for the last packet 999 */ 1000 MGB_TX_DESC_CTL_FS | MGB_TX_DESC_CTL_LS | 1001 MGB_DESC_CTL_FCS); 1002 txd->addr.low = htole32(CSR_TRANSLATE_ADDR_LOW32( 1003 segs[i].ds_addr)); 1004 txd->addr.high = htole32(CSR_TRANSLATE_ADDR_HIGH32( 1005 segs[i].ds_addr)); 1006 txd->sts = htole32( 1007 (segs[i].ds_len << 16) & MGB_DESC_FRAME_LEN_MASK); 1008 pidx = MGB_NEXT_RING_IDX(pidx); 1009 } 1010 ipi->ipi_new_pidx = pidx; 1011 return (0); 1012 } 1013 1014 static void 1015 mgb_isc_txd_flush(void *xsc, uint16_t txqid, qidx_t pidx) 1016 { 1017 struct mgb_softc *sc; 1018 struct mgb_ring_data *rdata; 1019 1020 KASSERT(txqid == 0, ("tried to flush TX Channel %d.\n", txqid)); 1021 sc = xsc; 1022 rdata = &sc->tx_ring_data; 1023 1024 if (rdata->last_tail != pidx) { 1025 rdata->last_tail = pidx; 1026 CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(txqid), rdata->last_tail); 1027 } 1028 } 1029 1030 static int 1031 mgb_isc_txd_credits_update(void *xsc, uint16_t txqid, bool clear) 1032 { 1033 struct mgb_softc *sc; 1034 struct mgb_ring_desc *txd; 1035 struct mgb_ring_data *rdata; 1036 int processed = 0; 1037 1038 /* 1039 * > If clear is true, we need to report the number of TX command ring 1040 * > descriptors that have been processed by the device. If clear is 1041 * > false, we just need to report whether or not at least one TX 1042 * > command ring descriptor has been processed by the device. 1043 * - vmx driver 1044 */ 1045 KASSERT(txqid == 0, ("tried to credits_update TX Channel %d.\n", 1046 txqid)); 1047 sc = xsc; 1048 rdata = &sc->tx_ring_data; 1049 1050 while (*(rdata->head_wb) != rdata->last_head) { 1051 if (!clear) 1052 return (1); 1053 1054 txd = &rdata->ring[rdata->last_head]; 1055 memset(txd, 0, sizeof(struct mgb_ring_desc)); 1056 rdata->last_head = MGB_NEXT_RING_IDX(rdata->last_head); 1057 processed++; 1058 } 1059 1060 return (processed); 1061 } 1062 1063 static int 1064 mgb_isc_rxd_available(void *xsc, uint16_t rxqid, qidx_t idx, qidx_t budget) 1065 { 1066 struct mgb_softc *sc; 1067 if_softc_ctx_t scctx; 1068 struct mgb_ring_data *rdata; 1069 int avail = 0; 1070 1071 sc = xsc; 1072 KASSERT(rxqid == 0, ("tried to check availability in RX Channel %d.\n", 1073 rxqid)); 1074 1075 rdata = &sc->rx_ring_data; 1076 scctx = iflib_get_softc_ctx(sc->ctx); 1077 for (; idx != *(rdata->head_wb); idx = MGB_NEXT_RING_IDX(idx)) { 1078 avail++; 1079 /* XXX: Could verify desc is device owned here */ 1080 if (avail == budget) 1081 break; 1082 } 1083 return (avail); 1084 } 1085 1086 static int 1087 mgb_isc_rxd_pkt_get(void *xsc, if_rxd_info_t ri) 1088 { 1089 struct mgb_softc *sc; 1090 struct mgb_ring_data *rdata; 1091 struct mgb_ring_desc rxd; 1092 int total_len; 1093 1094 KASSERT(ri->iri_qsidx == 0, 1095 ("tried to check availability in RX Channel %d\n", ri->iri_qsidx)); 1096 sc = xsc; 1097 total_len = 0; 1098 rdata = &sc->rx_ring_data; 1099 1100 while (*(rdata->head_wb) != rdata->last_head) { 1101 /* copy ring desc and do swapping */ 1102 rxd = rdata->ring[rdata->last_head]; 1103 rxd.ctl = le32toh(rxd.ctl); 1104 rxd.addr.low = le32toh(rxd.ctl); 1105 rxd.addr.high = le32toh(rxd.ctl); 1106 rxd.sts = le32toh(rxd.ctl); 1107 1108 if ((rxd.ctl & MGB_DESC_CTL_OWN) != 0) { 1109 device_printf(sc->dev, 1110 "Tried to read descriptor ... " 1111 "found that it's owned by the driver\n"); 1112 return (EINVAL); 1113 } 1114 if ((rxd.ctl & MGB_RX_DESC_CTL_FS) == 0) { 1115 device_printf(sc->dev, 1116 "Tried to read descriptor ... " 1117 "found that FS is not set.\n"); 1118 device_printf(sc->dev, "Tried to read descriptor ... that it FS is not set.\n"); 1119 return (EINVAL); 1120 } 1121 /* XXX: Multi-packet support */ 1122 if ((rxd.ctl & MGB_RX_DESC_CTL_LS) == 0) { 1123 device_printf(sc->dev, 1124 "Tried to read descriptor ... " 1125 "found that LS is not set. (Multi-buffer packets not yet supported)\n"); 1126 return (EINVAL); 1127 } 1128 ri->iri_frags[0].irf_flid = 0; 1129 ri->iri_frags[0].irf_idx = rdata->last_head; 1130 ri->iri_frags[0].irf_len = MGB_DESC_GET_FRAME_LEN(&rxd); 1131 total_len += ri->iri_frags[0].irf_len; 1132 1133 rdata->last_head = MGB_NEXT_RING_IDX(rdata->last_head); 1134 break; 1135 } 1136 ri->iri_nfrags = 1; 1137 ri->iri_len = total_len; 1138 1139 return (0); 1140 } 1141 1142 static void 1143 mgb_isc_rxd_refill(void *xsc, if_rxd_update_t iru) 1144 { 1145 if_softc_ctx_t scctx; 1146 struct mgb_softc *sc; 1147 struct mgb_ring_data *rdata; 1148 struct mgb_ring_desc *rxd; 1149 uint64_t *paddrs; 1150 qidx_t *idxs; 1151 qidx_t idx; 1152 int count, len; 1153 1154 count = iru->iru_count; 1155 len = iru->iru_buf_size; 1156 idxs = iru->iru_idxs; 1157 paddrs = iru->iru_paddrs; 1158 KASSERT(iru->iru_qsidx == 0, 1159 ("tried to refill RX Channel %d.\n", iru->iru_qsidx)); 1160 1161 sc = xsc; 1162 scctx = iflib_get_softc_ctx(sc->ctx); 1163 rdata = &sc->rx_ring_data; 1164 1165 while (count > 0) { 1166 idx = idxs[--count]; 1167 rxd = &rdata->ring[idx]; 1168 1169 rxd->sts = 0; 1170 rxd->addr.low = 1171 htole32(CSR_TRANSLATE_ADDR_LOW32(paddrs[count])); 1172 rxd->addr.high = 1173 htole32(CSR_TRANSLATE_ADDR_HIGH32(paddrs[count])); 1174 rxd->ctl = htole32(MGB_DESC_CTL_OWN | 1175 (len & MGB_DESC_CTL_BUFLEN_MASK)); 1176 } 1177 return; 1178 } 1179 1180 static void 1181 mgb_isc_rxd_flush(void *xsc, uint16_t rxqid, uint8_t flid, qidx_t pidx) 1182 { 1183 struct mgb_softc *sc; 1184 1185 sc = xsc; 1186 1187 KASSERT(rxqid == 0, ("tried to flush RX Channel %d.\n", rxqid)); 1188 /* 1189 * According to the programming guide, last_tail must be set to 1190 * the last valid RX descriptor, rather than to the one past that. 1191 * Note that this is not true for the TX ring! 1192 */ 1193 sc->rx_ring_data.last_tail = MGB_PREV_RING_IDX(pidx); 1194 CSR_WRITE_REG(sc, MGB_DMA_RX_TAIL(rxqid), sc->rx_ring_data.last_tail); 1195 return; 1196 } 1197 1198 static int 1199 mgb_test_bar(struct mgb_softc *sc) 1200 { 1201 uint32_t id_rev, dev_id, rev; 1202 1203 id_rev = CSR_READ_REG(sc, 0); 1204 dev_id = id_rev >> 16; 1205 rev = id_rev & 0xFFFF; 1206 if (dev_id == MGB_LAN7430_DEVICE_ID || 1207 dev_id == MGB_LAN7431_DEVICE_ID) { 1208 return (0); 1209 } else { 1210 device_printf(sc->dev, "ID check failed.\n"); 1211 return (ENXIO); 1212 } 1213 } 1214 1215 static int 1216 mgb_alloc_regs(struct mgb_softc *sc) 1217 { 1218 int rid; 1219 1220 rid = PCIR_BAR(MGB_BAR); 1221 pci_enable_busmaster(sc->dev); 1222 sc->regs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1223 &rid, RF_ACTIVE); 1224 if (sc->regs == NULL) 1225 return (ENXIO); 1226 1227 return (0); 1228 } 1229 1230 static int 1231 mgb_release_regs(struct mgb_softc *sc) 1232 { 1233 int error = 0; 1234 1235 if (sc->regs != NULL) 1236 error = bus_release_resource(sc->dev, SYS_RES_MEMORY, 1237 rman_get_rid(sc->regs), sc->regs); 1238 sc->regs = NULL; 1239 pci_disable_busmaster(sc->dev); 1240 return (error); 1241 } 1242 1243 static int 1244 mgb_dma_init(struct mgb_softc *sc) 1245 { 1246 if_softc_ctx_t scctx; 1247 int ch, error = 0; 1248 1249 scctx = iflib_get_softc_ctx(sc->ctx); 1250 1251 for (ch = 0; ch < scctx->isc_nrxqsets; ch++) 1252 if ((error = mgb_dma_rx_ring_init(sc, ch))) 1253 goto fail; 1254 1255 for (ch = 0; ch < scctx->isc_nrxqsets; ch++) 1256 if ((error = mgb_dma_tx_ring_init(sc, ch))) 1257 goto fail; 1258 1259 fail: 1260 return (error); 1261 } 1262 1263 static int 1264 mgb_dma_rx_ring_init(struct mgb_softc *sc, int channel) 1265 { 1266 struct mgb_ring_data *rdata; 1267 int ring_config, error = 0; 1268 1269 rdata = &sc->rx_ring_data; 1270 mgb_dmac_control(sc, MGB_DMAC_RX_START, 0, DMAC_RESET); 1271 KASSERT(MGB_DMAC_STATE_IS_INITIAL(sc, MGB_DMAC_RX_START, channel), 1272 ("Trying to init channels when not in init state\n")); 1273 1274 /* write ring address */ 1275 if (rdata->ring_bus_addr == 0) { 1276 device_printf(sc->dev, "Invalid ring bus addr.\n"); 1277 goto fail; 1278 } 1279 1280 CSR_WRITE_REG(sc, MGB_DMA_RX_BASE_H(channel), 1281 CSR_TRANSLATE_ADDR_HIGH32(rdata->ring_bus_addr)); 1282 CSR_WRITE_REG(sc, MGB_DMA_RX_BASE_L(channel), 1283 CSR_TRANSLATE_ADDR_LOW32(rdata->ring_bus_addr)); 1284 1285 /* write head pointer writeback address */ 1286 if (rdata->head_wb_bus_addr == 0) { 1287 device_printf(sc->dev, "Invalid head wb bus addr.\n"); 1288 goto fail; 1289 } 1290 CSR_WRITE_REG(sc, MGB_DMA_RX_HEAD_WB_H(channel), 1291 CSR_TRANSLATE_ADDR_HIGH32(rdata->head_wb_bus_addr)); 1292 CSR_WRITE_REG(sc, MGB_DMA_RX_HEAD_WB_L(channel), 1293 CSR_TRANSLATE_ADDR_LOW32(rdata->head_wb_bus_addr)); 1294 1295 /* Enable head pointer writeback */ 1296 CSR_WRITE_REG(sc, MGB_DMA_RX_CONFIG0(channel), MGB_DMA_HEAD_WB_ENBL); 1297 1298 ring_config = CSR_READ_REG(sc, MGB_DMA_RX_CONFIG1(channel)); 1299 /* ring size */ 1300 ring_config &= ~MGB_DMA_RING_LEN_MASK; 1301 ring_config |= (MGB_DMA_RING_SIZE & MGB_DMA_RING_LEN_MASK); 1302 /* packet padding (PAD_2 is better for IP header alignment ...) */ 1303 ring_config &= ~MGB_DMA_RING_PAD_MASK; 1304 ring_config |= (MGB_DMA_RING_PAD_0 & MGB_DMA_RING_PAD_MASK); 1305 1306 CSR_WRITE_REG(sc, MGB_DMA_RX_CONFIG1(channel), ring_config); 1307 1308 rdata->last_head = CSR_READ_REG(sc, MGB_DMA_RX_HEAD(channel)); 1309 1310 mgb_fct_control(sc, MGB_FCT_RX_CTL, channel, FCT_RESET); 1311 if (error != 0) { 1312 device_printf(sc->dev, "Failed to reset RX FCT.\n"); 1313 goto fail; 1314 } 1315 mgb_fct_control(sc, MGB_FCT_RX_CTL, channel, FCT_ENABLE); 1316 if (error != 0) { 1317 device_printf(sc->dev, "Failed to enable RX FCT.\n"); 1318 goto fail; 1319 } 1320 mgb_dmac_control(sc, MGB_DMAC_RX_START, channel, DMAC_START); 1321 if (error != 0) 1322 device_printf(sc->dev, "Failed to start RX DMAC.\n"); 1323 fail: 1324 return (error); 1325 } 1326 1327 static int 1328 mgb_dma_tx_ring_init(struct mgb_softc *sc, int channel) 1329 { 1330 struct mgb_ring_data *rdata; 1331 int ring_config, error = 0; 1332 1333 rdata = &sc->tx_ring_data; 1334 if ((error = mgb_fct_control(sc, MGB_FCT_TX_CTL, channel, FCT_RESET))) { 1335 device_printf(sc->dev, "Failed to reset TX FCT.\n"); 1336 goto fail; 1337 } 1338 if ((error = mgb_fct_control(sc, MGB_FCT_TX_CTL, channel, 1339 FCT_ENABLE))) { 1340 device_printf(sc->dev, "Failed to enable TX FCT.\n"); 1341 goto fail; 1342 } 1343 if ((error = mgb_dmac_control(sc, MGB_DMAC_TX_START, channel, 1344 DMAC_RESET))) { 1345 device_printf(sc->dev, "Failed to reset TX DMAC.\n"); 1346 goto fail; 1347 } 1348 KASSERT(MGB_DMAC_STATE_IS_INITIAL(sc, MGB_DMAC_TX_START, channel), 1349 ("Trying to init channels in not init state\n")); 1350 1351 /* write ring address */ 1352 if (rdata->ring_bus_addr == 0) { 1353 device_printf(sc->dev, "Invalid ring bus addr.\n"); 1354 goto fail; 1355 } 1356 CSR_WRITE_REG(sc, MGB_DMA_TX_BASE_H(channel), 1357 CSR_TRANSLATE_ADDR_HIGH32(rdata->ring_bus_addr)); 1358 CSR_WRITE_REG(sc, MGB_DMA_TX_BASE_L(channel), 1359 CSR_TRANSLATE_ADDR_LOW32(rdata->ring_bus_addr)); 1360 1361 /* write ring size */ 1362 ring_config = CSR_READ_REG(sc, MGB_DMA_TX_CONFIG1(channel)); 1363 ring_config &= ~MGB_DMA_RING_LEN_MASK; 1364 ring_config |= (MGB_DMA_RING_SIZE & MGB_DMA_RING_LEN_MASK); 1365 CSR_WRITE_REG(sc, MGB_DMA_TX_CONFIG1(channel), ring_config); 1366 1367 /* Enable interrupt on completion and head pointer writeback */ 1368 ring_config = (MGB_DMA_HEAD_WB_LS_ENBL | MGB_DMA_HEAD_WB_ENBL); 1369 CSR_WRITE_REG(sc, MGB_DMA_TX_CONFIG0(channel), ring_config); 1370 1371 /* write head pointer writeback address */ 1372 if (rdata->head_wb_bus_addr == 0) { 1373 device_printf(sc->dev, "Invalid head wb bus addr.\n"); 1374 goto fail; 1375 } 1376 CSR_WRITE_REG(sc, MGB_DMA_TX_HEAD_WB_H(channel), 1377 CSR_TRANSLATE_ADDR_HIGH32(rdata->head_wb_bus_addr)); 1378 CSR_WRITE_REG(sc, MGB_DMA_TX_HEAD_WB_L(channel), 1379 CSR_TRANSLATE_ADDR_LOW32(rdata->head_wb_bus_addr)); 1380 1381 rdata->last_head = CSR_READ_REG(sc, MGB_DMA_TX_HEAD(channel)); 1382 KASSERT(rdata->last_head == 0, ("MGB_DMA_TX_HEAD was not reset.\n")); 1383 rdata->last_tail = 0; 1384 CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(channel), rdata->last_tail); 1385 1386 if ((error = mgb_dmac_control(sc, MGB_DMAC_TX_START, channel, 1387 DMAC_START))) 1388 device_printf(sc->dev, "Failed to start TX DMAC.\n"); 1389 fail: 1390 return (error); 1391 } 1392 1393 static int 1394 mgb_dmac_control(struct mgb_softc *sc, int start, int channel, 1395 enum mgb_dmac_cmd cmd) 1396 { 1397 int error = 0; 1398 1399 switch (cmd) { 1400 case DMAC_RESET: 1401 CSR_WRITE_REG(sc, MGB_DMAC_CMD, 1402 MGB_DMAC_CMD_RESET(start, channel)); 1403 error = mgb_wait_for_bits(sc, MGB_DMAC_CMD, 0, 1404 MGB_DMAC_CMD_RESET(start, channel)); 1405 break; 1406 1407 case DMAC_START: 1408 /* 1409 * NOTE: this simplifies the logic, since it will never 1410 * try to start in STOP_PENDING, but it also increases work. 1411 */ 1412 error = mgb_dmac_control(sc, start, channel, DMAC_STOP); 1413 if (error != 0) 1414 return (error); 1415 CSR_WRITE_REG(sc, MGB_DMAC_CMD, 1416 MGB_DMAC_CMD_START(start, channel)); 1417 break; 1418 1419 case DMAC_STOP: 1420 CSR_WRITE_REG(sc, MGB_DMAC_CMD, 1421 MGB_DMAC_CMD_STOP(start, channel)); 1422 error = mgb_wait_for_bits(sc, MGB_DMAC_CMD, 1423 MGB_DMAC_CMD_STOP(start, channel), 1424 MGB_DMAC_CMD_START(start, channel)); 1425 break; 1426 } 1427 return (error); 1428 } 1429 1430 static int 1431 mgb_fct_control(struct mgb_softc *sc, int reg, int channel, 1432 enum mgb_fct_cmd cmd) 1433 { 1434 1435 switch (cmd) { 1436 case FCT_RESET: 1437 CSR_WRITE_REG(sc, reg, MGB_FCT_RESET(channel)); 1438 return (mgb_wait_for_bits(sc, reg, 0, MGB_FCT_RESET(channel))); 1439 case FCT_ENABLE: 1440 CSR_WRITE_REG(sc, reg, MGB_FCT_ENBL(channel)); 1441 return (0); 1442 case FCT_DISABLE: 1443 CSR_WRITE_REG(sc, reg, MGB_FCT_DSBL(channel)); 1444 return (mgb_wait_for_bits(sc, reg, 0, MGB_FCT_ENBL(channel))); 1445 } 1446 } 1447 1448 static int 1449 mgb_hw_teardown(struct mgb_softc *sc) 1450 { 1451 int err = 0; 1452 1453 /* Stop MAC */ 1454 CSR_CLEAR_REG(sc, MGB_MAC_RX, MGB_MAC_ENBL); 1455 CSR_WRITE_REG(sc, MGB_MAC_TX, MGB_MAC_ENBL); 1456 if ((err = mgb_wait_for_bits(sc, MGB_MAC_RX, MGB_MAC_DSBL, 0))) 1457 return (err); 1458 if ((err = mgb_wait_for_bits(sc, MGB_MAC_TX, MGB_MAC_DSBL, 0))) 1459 return (err); 1460 return (err); 1461 } 1462 1463 static int 1464 mgb_hw_init(struct mgb_softc *sc) 1465 { 1466 int error = 0; 1467 1468 error = mgb_hw_reset(sc); 1469 if (error != 0) 1470 goto fail; 1471 1472 mgb_mac_init(sc); 1473 1474 error = mgb_phy_reset(sc); 1475 if (error != 0) 1476 goto fail; 1477 1478 error = mgb_dmac_reset(sc); 1479 if (error != 0) 1480 goto fail; 1481 1482 fail: 1483 return (error); 1484 } 1485 1486 static int 1487 mgb_hw_reset(struct mgb_softc *sc) 1488 { 1489 1490 CSR_UPDATE_REG(sc, MGB_HW_CFG, MGB_LITE_RESET); 1491 return (mgb_wait_for_bits(sc, MGB_HW_CFG, 0, MGB_LITE_RESET)); 1492 } 1493 1494 static int 1495 mgb_mac_init(struct mgb_softc *sc) 1496 { 1497 1498 /** 1499 * enable automatic duplex detection and 1500 * automatic speed detection 1501 */ 1502 CSR_UPDATE_REG(sc, MGB_MAC_CR, MGB_MAC_ADD_ENBL | MGB_MAC_ASD_ENBL); 1503 CSR_UPDATE_REG(sc, MGB_MAC_TX, MGB_MAC_ENBL); 1504 CSR_UPDATE_REG(sc, MGB_MAC_RX, MGB_MAC_ENBL); 1505 1506 return (MGB_STS_OK); 1507 } 1508 1509 static int 1510 mgb_phy_reset(struct mgb_softc *sc) 1511 { 1512 1513 CSR_UPDATE_BYTE(sc, MGB_PMT_CTL, MGB_PHY_RESET); 1514 if (mgb_wait_for_bits(sc, MGB_PMT_CTL, 0, MGB_PHY_RESET) == 1515 MGB_STS_TIMEOUT) 1516 return (MGB_STS_TIMEOUT); 1517 return (mgb_wait_for_bits(sc, MGB_PMT_CTL, MGB_PHY_READY, 0)); 1518 } 1519 1520 static int 1521 mgb_dmac_reset(struct mgb_softc *sc) 1522 { 1523 1524 CSR_WRITE_REG(sc, MGB_DMAC_CMD, MGB_DMAC_RESET); 1525 return (mgb_wait_for_bits(sc, MGB_DMAC_CMD, 0, MGB_DMAC_RESET)); 1526 } 1527 1528 static int 1529 mgb_wait_for_bits(struct mgb_softc *sc, int reg, int set_bits, int clear_bits) 1530 { 1531 int i, val; 1532 1533 i = 0; 1534 do { 1535 /* 1536 * XXX: Datasheets states delay should be > 5 microseconds 1537 * for device reset. 1538 */ 1539 DELAY(100); 1540 val = CSR_READ_REG(sc, reg); 1541 if ((val & set_bits) == set_bits && (val & clear_bits) == 0) 1542 return (MGB_STS_OK); 1543 } while (i++ < MGB_TIMEOUT); 1544 1545 return (MGB_STS_TIMEOUT); 1546 } 1547 1548 static void 1549 mgb_get_ethaddr(struct mgb_softc *sc, struct ether_addr *dest) 1550 { 1551 1552 CSR_READ_REG_BYTES(sc, MGB_MAC_ADDR_BASE_L, &dest->octet[0], 4); 1553 CSR_READ_REG_BYTES(sc, MGB_MAC_ADDR_BASE_H, &dest->octet[4], 2); 1554 } 1555 1556 static int 1557 mgb_miibus_readreg(device_t dev, int phy, int reg) 1558 { 1559 struct mgb_softc *sc; 1560 int mii_access; 1561 1562 sc = iflib_get_softc(device_get_softc(dev)); 1563 1564 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == 1565 MGB_STS_TIMEOUT) 1566 return (EIO); 1567 mii_access = (phy & MGB_MII_PHY_ADDR_MASK) << MGB_MII_PHY_ADDR_SHIFT; 1568 mii_access |= (reg & MGB_MII_REG_ADDR_MASK) << MGB_MII_REG_ADDR_SHIFT; 1569 mii_access |= MGB_MII_BUSY | MGB_MII_READ; 1570 CSR_WRITE_REG(sc, MGB_MII_ACCESS, mii_access); 1571 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == 1572 MGB_STS_TIMEOUT) 1573 return (EIO); 1574 return (CSR_READ_2_BYTES(sc, MGB_MII_DATA)); 1575 } 1576 1577 static int 1578 mgb_miibus_writereg(device_t dev, int phy, int reg, int data) 1579 { 1580 struct mgb_softc *sc; 1581 int mii_access; 1582 1583 sc = iflib_get_softc(device_get_softc(dev)); 1584 1585 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == 1586 MGB_STS_TIMEOUT) 1587 return (EIO); 1588 mii_access = (phy & MGB_MII_PHY_ADDR_MASK) << MGB_MII_PHY_ADDR_SHIFT; 1589 mii_access |= (reg & MGB_MII_REG_ADDR_MASK) << MGB_MII_REG_ADDR_SHIFT; 1590 mii_access |= MGB_MII_BUSY | MGB_MII_WRITE; 1591 CSR_WRITE_REG(sc, MGB_MII_DATA, data); 1592 CSR_WRITE_REG(sc, MGB_MII_ACCESS, mii_access); 1593 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == 1594 MGB_STS_TIMEOUT) 1595 return (EIO); 1596 return (0); 1597 } 1598 1599 /* XXX: May need to lock these up */ 1600 static void 1601 mgb_miibus_statchg(device_t dev) 1602 { 1603 struct mgb_softc *sc; 1604 struct mii_data *miid; 1605 1606 sc = iflib_get_softc(device_get_softc(dev)); 1607 miid = device_get_softc(sc->miibus); 1608 /* Update baudrate in iflib */ 1609 sc->baudrate = ifmedia_baudrate(miid->mii_media_active); 1610 iflib_link_state_change(sc->ctx, sc->link_state, sc->baudrate); 1611 } 1612 1613 static void 1614 mgb_miibus_linkchg(device_t dev) 1615 { 1616 struct mgb_softc *sc; 1617 struct mii_data *miid; 1618 int link_state; 1619 1620 sc = iflib_get_softc(device_get_softc(dev)); 1621 miid = device_get_softc(sc->miibus); 1622 /* XXX: copied from miibus_linkchg **/ 1623 if (miid->mii_media_status & IFM_AVALID) { 1624 if (miid->mii_media_status & IFM_ACTIVE) 1625 link_state = LINK_STATE_UP; 1626 else 1627 link_state = LINK_STATE_DOWN; 1628 } else 1629 link_state = LINK_STATE_UNKNOWN; 1630 sc->link_state = link_state; 1631 iflib_link_state_change(sc->ctx, sc->link_state, sc->baudrate); 1632 } 1633