1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 The FreeBSD Foundation, Inc. 5 * 6 * This driver was written by Gerald ND Aryeetey <gndaryee@uwaterloo.ca> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Microchip LAN7430/LAN7431 PCIe to Gigabit Ethernet Controller driver. 35 * 36 * Product information: 37 * LAN7430 https://www.microchip.com/wwwproducts/en/LAN7430 38 * - Integrated IEEE 802.3 compliant PHY 39 * LAN7431 https://www.microchip.com/wwwproducts/en/LAN7431 40 * - RGMII Interface 41 * 42 * This driver uses the iflib interface and the default 'ukphy' PHY driver. 43 * 44 * UNIMPLEMENTED FEATURES 45 * ---------------------- 46 * A number of features supported by LAN743X device are not yet implemented in 47 * this driver: 48 * 49 * - Multiple (up to 4) RX queues support 50 * - Just needs to remove asserts and malloc multiple `rx_ring_data` 51 * structs based on ncpus. 52 * - RX/TX Checksum Offloading support 53 * - VLAN support 54 * - Receive Packet Filtering (Multicast Perfect/Hash Address) support 55 * - Wake on LAN (WoL) support 56 * - TX LSO support 57 * - Receive Side Scaling (RSS) support 58 * - Debugging Capabilities: 59 * - Could include MAC statistics and 60 * error status registers in sysctl. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kdb.h> 67 #include <sys/kernel.h> 68 #include <sys/module.h> 69 #include <sys/rman.h> 70 #include <sys/socket.h> 71 #include <sys/sockio.h> 72 #include <machine/bus.h> 73 #include <machine/resource.h> 74 75 #include <net/ethernet.h> 76 #include <net/if.h> 77 #include <net/if_var.h> 78 #include <net/if_types.h> 79 #include <net/if_media.h> 80 #include <net/iflib.h> 81 82 #include <dev/mgb/if_mgb.h> 83 #include <dev/mii/mii.h> 84 #include <dev/mii/miivar.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 88 #include "ifdi_if.h" 89 #include "miibus_if.h" 90 91 static pci_vendor_info_t mgb_vendor_info_array[] = { 92 PVID(MGB_MICROCHIP_VENDOR_ID, MGB_LAN7430_DEVICE_ID, 93 "Microchip LAN7430 PCIe Gigabit Ethernet Controller"), 94 PVID(MGB_MICROCHIP_VENDOR_ID, MGB_LAN7431_DEVICE_ID, 95 "Microchip LAN7431 PCIe Gigabit Ethernet Controller"), 96 PVID_END 97 }; 98 99 /* Device methods */ 100 static device_register_t mgb_register; 101 102 /* IFLIB methods */ 103 static ifdi_attach_pre_t mgb_attach_pre; 104 static ifdi_attach_post_t mgb_attach_post; 105 static ifdi_detach_t mgb_detach; 106 107 static ifdi_tx_queues_alloc_t mgb_tx_queues_alloc; 108 static ifdi_rx_queues_alloc_t mgb_rx_queues_alloc; 109 static ifdi_queues_free_t mgb_queues_free; 110 111 static ifdi_init_t mgb_init; 112 static ifdi_stop_t mgb_stop; 113 114 static ifdi_msix_intr_assign_t mgb_msix_intr_assign; 115 static ifdi_tx_queue_intr_enable_t mgb_tx_queue_intr_enable; 116 static ifdi_rx_queue_intr_enable_t mgb_rx_queue_intr_enable; 117 static ifdi_intr_enable_t mgb_intr_enable_all; 118 static ifdi_intr_disable_t mgb_intr_disable_all; 119 120 /* IFLIB_TXRX methods */ 121 static int mgb_isc_txd_encap(void *, 122 if_pkt_info_t); 123 static void mgb_isc_txd_flush(void *, 124 uint16_t, qidx_t); 125 static int mgb_isc_txd_credits_update(void *, 126 uint16_t, bool); 127 static int mgb_isc_rxd_available(void *, 128 uint16_t, qidx_t, qidx_t); 129 static int mgb_isc_rxd_pkt_get(void *, 130 if_rxd_info_t); 131 static void mgb_isc_rxd_refill(void *, 132 if_rxd_update_t); 133 static void mgb_isc_rxd_flush(void *, 134 uint16_t, uint8_t, qidx_t); 135 136 /* Interrupts */ 137 static driver_filter_t mgb_legacy_intr; 138 static driver_filter_t mgb_admin_intr; 139 static driver_filter_t mgb_rxq_intr; 140 static bool mgb_intr_test(struct mgb_softc *); 141 142 /* MII methods */ 143 static miibus_readreg_t mgb_miibus_readreg; 144 static miibus_writereg_t mgb_miibus_writereg; 145 static miibus_linkchg_t mgb_miibus_linkchg; 146 static miibus_statchg_t mgb_miibus_statchg; 147 148 static int mgb_media_change(if_t); 149 static void mgb_media_status(if_t, 150 struct ifmediareq *); 151 152 /* Helper/Test functions */ 153 static int mgb_test_bar(struct mgb_softc *); 154 static int mgb_alloc_regs(struct mgb_softc *); 155 static int mgb_release_regs(struct mgb_softc *); 156 157 static void mgb_get_ethaddr(struct mgb_softc *, 158 struct ether_addr *); 159 160 static int mgb_wait_for_bits(struct mgb_softc *, 161 int, int, int); 162 163 /* H/W init, reset and teardown helpers */ 164 static int mgb_hw_init(struct mgb_softc *); 165 static int mgb_hw_teardown(struct mgb_softc *); 166 static int mgb_hw_reset(struct mgb_softc *); 167 static int mgb_mac_init(struct mgb_softc *); 168 static int mgb_dmac_reset(struct mgb_softc *); 169 static int mgb_phy_reset(struct mgb_softc *); 170 171 static int mgb_dma_init(struct mgb_softc *); 172 static int mgb_dma_tx_ring_init(struct mgb_softc *, 173 int); 174 static int mgb_dma_rx_ring_init(struct mgb_softc *, 175 int); 176 177 static int mgb_dmac_control(struct mgb_softc *, 178 int, int, enum mgb_dmac_cmd); 179 static int mgb_fct_control(struct mgb_softc *, 180 int, int, enum mgb_fct_cmd); 181 182 /********************************************************************* 183 * FreeBSD Device Interface Entry Points 184 *********************************************************************/ 185 186 static device_method_t mgb_methods[] = { 187 /* Device interface */ 188 DEVMETHOD(device_register, mgb_register), 189 DEVMETHOD(device_probe, iflib_device_probe), 190 DEVMETHOD(device_attach, iflib_device_attach), 191 DEVMETHOD(device_detach, iflib_device_detach), 192 DEVMETHOD(device_shutdown, iflib_device_shutdown), 193 DEVMETHOD(device_suspend, iflib_device_suspend), 194 DEVMETHOD(device_resume, iflib_device_resume), 195 196 /* MII Interface */ 197 DEVMETHOD(miibus_readreg, mgb_miibus_readreg), 198 DEVMETHOD(miibus_writereg, mgb_miibus_writereg), 199 DEVMETHOD(miibus_linkchg, mgb_miibus_linkchg), 200 DEVMETHOD(miibus_statchg, mgb_miibus_statchg), 201 202 DEVMETHOD_END 203 }; 204 205 static driver_t mgb_driver = { 206 "mgb", mgb_methods, sizeof(struct mgb_softc) 207 }; 208 209 devclass_t mgb_devclass; 210 DRIVER_MODULE(mgb, pci, mgb_driver, mgb_devclass, NULL, NULL); 211 IFLIB_PNP_INFO(pci, mgb, mgb_vendor_info_array); 212 MODULE_VERSION(mgb, 1); 213 214 #if 0 /* MIIBUS_DEBUG */ 215 /* If MIIBUS debug stuff is in attach then order matters. Use below instead. */ 216 DRIVER_MODULE_ORDERED(miibus, mgb, miibus_driver, miibus_devclass, NULL, NULL, 217 SI_ORDER_ANY); 218 #endif /* MIIBUS_DEBUG */ 219 DRIVER_MODULE(miibus, mgb, miibus_driver, miibus_devclass, NULL, NULL); 220 221 MODULE_DEPEND(mgb, pci, 1, 1, 1); 222 MODULE_DEPEND(mgb, ether, 1, 1, 1); 223 MODULE_DEPEND(mgb, miibus, 1, 1, 1); 224 MODULE_DEPEND(mgb, iflib, 1, 1, 1); 225 226 static device_method_t mgb_iflib_methods[] = { 227 DEVMETHOD(ifdi_attach_pre, mgb_attach_pre), 228 DEVMETHOD(ifdi_attach_post, mgb_attach_post), 229 DEVMETHOD(ifdi_detach, mgb_detach), 230 231 DEVMETHOD(ifdi_init, mgb_init), 232 DEVMETHOD(ifdi_stop, mgb_stop), 233 234 DEVMETHOD(ifdi_tx_queues_alloc, mgb_tx_queues_alloc), 235 DEVMETHOD(ifdi_rx_queues_alloc, mgb_rx_queues_alloc), 236 DEVMETHOD(ifdi_queues_free, mgb_queues_free), 237 238 DEVMETHOD(ifdi_msix_intr_assign, mgb_msix_intr_assign), 239 DEVMETHOD(ifdi_tx_queue_intr_enable, mgb_tx_queue_intr_enable), 240 DEVMETHOD(ifdi_rx_queue_intr_enable, mgb_rx_queue_intr_enable), 241 DEVMETHOD(ifdi_intr_enable, mgb_intr_enable_all), 242 DEVMETHOD(ifdi_intr_disable, mgb_intr_disable_all), 243 244 245 #if 0 /* Not yet implemented IFLIB methods */ 246 /* 247 * Set multicast addresses, mtu and promiscuous mode 248 */ 249 DEVMETHOD(ifdi_multi_set, mgb_multi_set), 250 DEVMETHOD(ifdi_mtu_set, mgb_mtu_set), 251 DEVMETHOD(ifdi_promisc_set, mgb_promisc_set), 252 253 /* 254 * Needed for VLAN support 255 */ 256 DEVMETHOD(ifdi_vlan_register, mgb_vlan_register), 257 DEVMETHOD(ifdi_vlan_unregister, mgb_vlan_unregister), 258 259 /* 260 * Needed for WOL support 261 * at the very least. 262 */ 263 DEVMETHOD(ifdi_shutdown, mgb_shutdown), 264 DEVMETHOD(ifdi_suspend, mgb_suspend), 265 DEVMETHOD(ifdi_resume, mgb_resume), 266 #endif /* UNUSED_IFLIB_METHODS */ 267 DEVMETHOD_END 268 }; 269 270 static driver_t mgb_iflib_driver = { 271 "mgb", mgb_iflib_methods, sizeof(struct mgb_softc) 272 }; 273 274 struct if_txrx mgb_txrx = { 275 .ift_txd_encap = mgb_isc_txd_encap, 276 .ift_txd_flush = mgb_isc_txd_flush, 277 .ift_txd_credits_update = mgb_isc_txd_credits_update, 278 .ift_rxd_available = mgb_isc_rxd_available, 279 .ift_rxd_pkt_get = mgb_isc_rxd_pkt_get, 280 .ift_rxd_refill = mgb_isc_rxd_refill, 281 .ift_rxd_flush = mgb_isc_rxd_flush, 282 283 .ift_legacy_intr = mgb_legacy_intr 284 }; 285 286 struct if_shared_ctx mgb_sctx_init = { 287 .isc_magic = IFLIB_MAGIC, 288 289 .isc_q_align = PAGE_SIZE, 290 .isc_admin_intrcnt = 1, 291 .isc_flags = IFLIB_DRIVER_MEDIA /* | IFLIB_HAS_RXCQ | IFLIB_HAS_TXCQ*/, 292 293 .isc_vendor_info = mgb_vendor_info_array, 294 .isc_driver_version = "1", 295 .isc_driver = &mgb_iflib_driver, 296 /* 2 queues per set for TX and RX (ring queue, head writeback queue) */ 297 .isc_ntxqs = 2, 298 299 .isc_tx_maxsize = MGB_DMA_MAXSEGS * MCLBYTES, 300 /* .isc_tx_nsegments = MGB_DMA_MAXSEGS, */ 301 .isc_tx_maxsegsize = MCLBYTES, 302 303 .isc_ntxd_min = {1, 1}, /* Will want to make this bigger */ 304 .isc_ntxd_max = {MGB_DMA_RING_SIZE, 1}, 305 .isc_ntxd_default = {MGB_DMA_RING_SIZE, 1}, 306 307 .isc_nrxqs = 2, 308 309 .isc_rx_maxsize = MCLBYTES, 310 .isc_rx_nsegments = 1, 311 .isc_rx_maxsegsize = MCLBYTES, 312 313 .isc_nrxd_min = {1, 1}, /* Will want to make this bigger */ 314 .isc_nrxd_max = {MGB_DMA_RING_SIZE, 1}, 315 .isc_nrxd_default = {MGB_DMA_RING_SIZE, 1}, 316 317 .isc_nfl = 1, /*one free list since there is only one queue */ 318 #if 0 /* UNUSED_CTX */ 319 320 .isc_tso_maxsize = MGB_TSO_MAXSIZE + sizeof(struct ether_vlan_header), 321 .isc_tso_maxsegsize = MGB_TX_MAXSEGSIZE, 322 #endif /* UNUSED_CTX */ 323 }; 324 325 /*********************************************************************/ 326 327 328 static void * 329 mgb_register(device_t dev) 330 { 331 332 return (&mgb_sctx_init); 333 } 334 335 static int 336 mgb_attach_pre(if_ctx_t ctx) 337 { 338 struct mgb_softc *sc; 339 if_softc_ctx_t scctx; 340 int error, phyaddr, rid; 341 struct ether_addr hwaddr; 342 struct mii_data *miid; 343 344 sc = iflib_get_softc(ctx); 345 sc->ctx = ctx; 346 sc->dev = iflib_get_dev(ctx); 347 scctx = iflib_get_softc_ctx(ctx); 348 349 /* IFLIB required setup */ 350 scctx->isc_txrx = &mgb_txrx; 351 scctx->isc_tx_nsegments = MGB_DMA_MAXSEGS; 352 /* Ring desc queues */ 353 scctx->isc_txqsizes[0] = sizeof(struct mgb_ring_desc) * 354 scctx->isc_ntxd[0]; 355 scctx->isc_rxqsizes[0] = sizeof(struct mgb_ring_desc) * 356 scctx->isc_nrxd[0]; 357 358 /* Head WB queues */ 359 scctx->isc_txqsizes[1] = sizeof(uint32_t) * scctx->isc_ntxd[1]; 360 scctx->isc_rxqsizes[1] = sizeof(uint32_t) * scctx->isc_nrxd[1]; 361 362 /* XXX: Must have 1 txqset, but can have up to 4 rxqsets */ 363 scctx->isc_nrxqsets = 1; 364 scctx->isc_ntxqsets = 1; 365 366 /* scctx->isc_tx_csum_flags = (CSUM_TCP | CSUM_UDP) | 367 (CSUM_TCP_IPV6 | CSUM_UDP_IPV6) | CSUM_TSO */ 368 scctx->isc_tx_csum_flags = 0; 369 scctx->isc_capabilities = scctx->isc_capenable = 0; 370 #if 0 371 /* 372 * CSUM, TSO and VLAN support are TBD 373 */ 374 IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6 | 375 IFCAP_TSO4 | IFCAP_TSO6 | 376 IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 | 377 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 378 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | 379 IFCAP_JUMBO_MTU; 380 scctx->isc_capabilities |= IFCAP_LRO | IFCAP_VLAN_HWFILTER; 381 #endif 382 383 /* get the BAR */ 384 error = mgb_alloc_regs(sc); 385 if (error != 0) { 386 device_printf(sc->dev, 387 "Unable to allocate bus resource: registers.\n"); 388 goto fail; 389 } 390 391 error = mgb_test_bar(sc); 392 if (error != 0) 393 goto fail; 394 395 error = mgb_hw_init(sc); 396 if (error != 0) { 397 device_printf(sc->dev, 398 "MGB device init failed. (err: %d)\n", error); 399 goto fail; 400 } 401 402 switch (pci_get_device(sc->dev)) 403 { 404 case MGB_LAN7430_DEVICE_ID: 405 phyaddr = 1; 406 break; 407 case MGB_LAN7431_DEVICE_ID: 408 default: 409 phyaddr = MII_PHY_ANY; 410 break; 411 } 412 413 /* XXX: Would be nice(r) if locked methods were here */ 414 error = mii_attach(sc->dev, &sc->miibus, iflib_get_ifp(ctx), 415 mgb_media_change, mgb_media_status, 416 BMSR_DEFCAPMASK, phyaddr, MII_OFFSET_ANY, MIIF_DOPAUSE); 417 if (error != 0) { 418 device_printf(sc->dev, "Failed to attach MII interface\n"); 419 goto fail; 420 } 421 422 miid = device_get_softc(sc->miibus); 423 scctx->isc_media = &miid->mii_media; 424 425 scctx->isc_msix_bar = pci_msix_table_bar(sc->dev); 426 /** Setup PBA BAR **/ 427 rid = pci_msix_pba_bar(sc->dev); 428 if (rid != scctx->isc_msix_bar) { 429 sc->pba = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 430 &rid, RF_ACTIVE); 431 if (sc->pba == NULL) { 432 error = ENXIO; 433 device_printf(sc->dev, "Failed to setup PBA BAR\n"); 434 goto fail; 435 } 436 } 437 438 mgb_get_ethaddr(sc, &hwaddr); 439 if (ETHER_IS_BROADCAST(hwaddr.octet) || 440 ETHER_IS_MULTICAST(hwaddr.octet) || 441 ETHER_IS_ZERO(hwaddr.octet)) 442 ether_gen_addr(iflib_get_ifp(ctx), &hwaddr); 443 444 /* 445 * XXX: if the MAC address was generated the linux driver 446 * writes it back to the device. 447 */ 448 iflib_set_mac(ctx, hwaddr.octet); 449 450 /* Map all vectors to vector 0 (admin interrupts) by default. */ 451 CSR_WRITE_REG(sc, MGB_INTR_VEC_RX_MAP, 0); 452 CSR_WRITE_REG(sc, MGB_INTR_VEC_TX_MAP, 0); 453 CSR_WRITE_REG(sc, MGB_INTR_VEC_OTHER_MAP, 0); 454 455 return (0); 456 457 fail: 458 mgb_detach(ctx); 459 return (error); 460 } 461 462 static int 463 mgb_attach_post(if_ctx_t ctx) 464 { 465 struct mgb_softc *sc; 466 467 sc = iflib_get_softc(ctx); 468 469 device_printf(sc->dev, "Interrupt test: %s\n", 470 (mgb_intr_test(sc) ? "PASS" : "FAIL")); 471 472 return (0); 473 } 474 475 static int 476 mgb_detach(if_ctx_t ctx) 477 { 478 struct mgb_softc *sc; 479 int error; 480 481 sc = iflib_get_softc(ctx); 482 483 /* XXX: Should report errors but still detach everything. */ 484 error = mgb_hw_teardown(sc); 485 486 /* Release IRQs */ 487 iflib_irq_free(ctx, &sc->rx_irq); 488 iflib_irq_free(ctx, &sc->admin_irq); 489 490 if (sc->miibus != NULL) 491 device_delete_child(sc->dev, sc->miibus); 492 493 if (sc->pba != NULL) 494 error = bus_release_resource(sc->dev, SYS_RES_MEMORY, 495 rman_get_rid(sc->pba), sc->pba); 496 sc->pba = NULL; 497 498 error = mgb_release_regs(sc); 499 500 return (error); 501 } 502 503 static int 504 mgb_media_change(if_t ifp) 505 { 506 struct mii_data *miid; 507 struct mii_softc *miisc; 508 struct mgb_softc *sc; 509 if_ctx_t ctx; 510 int needs_reset; 511 512 ctx = if_getsoftc(ifp); 513 sc = iflib_get_softc(ctx); 514 miid = device_get_softc(sc->miibus); 515 LIST_FOREACH(miisc, &miid->mii_phys, mii_list) 516 PHY_RESET(miisc); 517 518 needs_reset = mii_mediachg(miid); 519 if (needs_reset != 0) 520 ifp->if_init(ctx); 521 return (needs_reset); 522 } 523 524 static void 525 mgb_media_status(if_t ifp, struct ifmediareq *ifmr) 526 { 527 struct mgb_softc *sc; 528 struct mii_data *miid; 529 530 sc = iflib_get_softc(if_getsoftc(ifp)); 531 miid = device_get_softc(sc->miibus); 532 if ((if_getflags(ifp) & IFF_UP) == 0) 533 return; 534 535 mii_pollstat(miid); 536 ifmr->ifm_active = miid->mii_media_active; 537 ifmr->ifm_status = miid->mii_media_status; 538 } 539 540 static int 541 mgb_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, 542 int ntxqsets) 543 { 544 struct mgb_softc *sc; 545 struct mgb_ring_data *rdata; 546 int q; 547 548 sc = iflib_get_softc(ctx); 549 KASSERT(ntxqsets == 1, ("ntxqsets = %d", ntxqsets)); 550 rdata = &sc->tx_ring_data; 551 for (q = 0; q < ntxqsets; q++) { 552 KASSERT(ntxqs == 2, ("ntxqs = %d", ntxqs)); 553 /* Ring */ 554 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * ntxqs + 0]; 555 rdata->ring_bus_addr = paddrs[q * ntxqs + 0]; 556 557 /* Head WB */ 558 rdata->head_wb = (uint32_t *) vaddrs[q * ntxqs + 1]; 559 rdata->head_wb_bus_addr = paddrs[q * ntxqs + 1]; 560 } 561 return 0; 562 } 563 564 static int 565 mgb_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, 566 int nrxqsets) 567 { 568 struct mgb_softc *sc; 569 struct mgb_ring_data *rdata; 570 int q; 571 572 sc = iflib_get_softc(ctx); 573 KASSERT(nrxqsets == 1, ("nrxqsets = %d", nrxqsets)); 574 rdata = &sc->rx_ring_data; 575 for (q = 0; q < nrxqsets; q++) { 576 KASSERT(nrxqs == 2, ("nrxqs = %d", nrxqs)); 577 /* Ring */ 578 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * nrxqs + 0]; 579 rdata->ring_bus_addr = paddrs[q * nrxqs + 0]; 580 581 /* Head WB */ 582 rdata->head_wb = (uint32_t *) vaddrs[q * nrxqs + 1]; 583 rdata->head_wb_bus_addr = paddrs[q * nrxqs + 1]; 584 } 585 return 0; 586 } 587 588 static void 589 mgb_queues_free(if_ctx_t ctx) 590 { 591 struct mgb_softc *sc; 592 593 sc = iflib_get_softc(ctx); 594 595 memset(&sc->rx_ring_data, 0, sizeof(struct mgb_ring_data)); 596 memset(&sc->tx_ring_data, 0, sizeof(struct mgb_ring_data)); 597 } 598 599 static void 600 mgb_init(if_ctx_t ctx) 601 { 602 struct mgb_softc *sc; 603 struct mii_data *miid; 604 int error; 605 606 sc = iflib_get_softc(ctx); 607 miid = device_get_softc(sc->miibus); 608 device_printf(sc->dev, "running init ...\n"); 609 610 mgb_dma_init(sc); 611 612 /* XXX: Turn off perfect filtering, turn on (broad|multi|uni)cast rx */ 613 CSR_CLEAR_REG(sc, MGB_RFE_CTL, MGB_RFE_ALLOW_PERFECT_FILTER); 614 CSR_UPDATE_REG(sc, MGB_RFE_CTL, 615 MGB_RFE_ALLOW_BROADCAST | 616 MGB_RFE_ALLOW_UNICAST | 617 MGB_RFE_ALLOW_UNICAST); 618 619 error = mii_mediachg(miid); 620 KASSERT(!error, ("mii_mediachg returned: %d", error)); 621 } 622 623 #ifdef DEBUG 624 static void 625 mgb_dump_some_stats(struct mgb_softc *sc) 626 { 627 int i; 628 int first_stat = 0x1200; 629 int last_stat = 0x12FC; 630 631 for (i = first_stat; i <= last_stat; i += 4) 632 if (CSR_READ_REG(sc, i) != 0) 633 device_printf(sc->dev, "0x%04x: 0x%08x\n", i, 634 CSR_READ_REG(sc, i)); 635 char *stat_names[] = { 636 "MAC_ERR_STS ", 637 "FCT_INT_STS ", 638 "DMAC_CFG ", 639 "DMAC_CMD ", 640 "DMAC_INT_STS ", 641 "DMAC_INT_EN ", 642 "DMAC_RX_ERR_STS0 ", 643 "DMAC_RX_ERR_STS1 ", 644 "DMAC_RX_ERR_STS2 ", 645 "DMAC_RX_ERR_STS3 ", 646 "INT_STS ", 647 "INT_EN ", 648 "INT_VEC_EN ", 649 "INT_VEC_MAP0 ", 650 "INT_VEC_MAP1 ", 651 "INT_VEC_MAP2 ", 652 "TX_HEAD0", 653 "TX_TAIL0", 654 "DMAC_TX_ERR_STS0 ", 655 NULL 656 }; 657 int stats[] = { 658 0x114, 659 0xA0, 660 0xC00, 661 0xC0C, 662 0xC10, 663 0xC14, 664 0xC60, 665 0xCA0, 666 0xCE0, 667 0xD20, 668 0x780, 669 0x788, 670 0x794, 671 0x7A0, 672 0x7A4, 673 0x780, 674 0xD58, 675 0xD5C, 676 0xD60, 677 0x0 678 }; 679 i = 0; 680 printf("==============================\n"); 681 while (stats[i++]) 682 device_printf(sc->dev, "%s at offset 0x%04x = 0x%08x\n", 683 stat_names[i - 1], stats[i - 1], 684 CSR_READ_REG(sc, stats[i - 1])); 685 printf("==== TX RING DESCS ====\n"); 686 for (i = 0; i < MGB_DMA_RING_SIZE; i++) 687 device_printf(sc->dev, "ring[%d].data0=0x%08x\n" 688 "ring[%d].data1=0x%08x\n" 689 "ring[%d].data2=0x%08x\n" 690 "ring[%d].data3=0x%08x\n", 691 i, sc->tx_ring_data.ring[i].ctl, 692 i, sc->tx_ring_data.ring[i].addr.low, 693 i, sc->tx_ring_data.ring[i].addr.high, 694 i, sc->tx_ring_data.ring[i].sts); 695 device_printf(sc->dev, "==== DUMP_TX_DMA_RAM ====\n"); 696 int i; 697 CSR_WRITE_REG(sc, 0x24, 0xF); // DP_SEL & TX_RAM_0 698 for (i = 0; i < 128; i++) { 699 CSR_WRITE_REG(sc, 0x2C, i); // DP_ADDR 700 701 CSR_WRITE_REG(sc, 0x28, 0); // DP_CMD 702 703 while ((CSR_READ_REG(sc, 0x24) & 0x80000000) == 0) // DP_SEL & READY 704 DELAY(1000); 705 706 device_printf(sc->dev, "DMAC_TX_RAM_0[%u]=%08x\n", i, 707 CSR_READ_REG(sc, 0x30)); // DP_DATA 708 } 709 } 710 #endif 711 712 static void 713 mgb_stop(if_ctx_t ctx) 714 { 715 struct mgb_softc *sc ; 716 if_softc_ctx_t scctx; 717 int i; 718 719 sc = iflib_get_softc(ctx); 720 scctx = iflib_get_softc_ctx(ctx); 721 722 /* XXX: Could potentially timeout */ 723 for (i = 0; i < scctx->isc_nrxqsets; i++) { 724 mgb_dmac_control(sc, MGB_DMAC_RX_START, 0, DMAC_STOP); 725 mgb_fct_control(sc, MGB_FCT_RX_CTL, 0, FCT_DISABLE); 726 } 727 for (i = 0; i < scctx->isc_ntxqsets; i++) { 728 mgb_dmac_control(sc, MGB_DMAC_TX_START, 0, DMAC_STOP); 729 mgb_fct_control(sc, MGB_FCT_TX_CTL, 0, FCT_DISABLE); 730 } 731 } 732 733 static int 734 mgb_legacy_intr(void *xsc) 735 { 736 struct mgb_softc *sc; 737 738 sc = xsc; 739 iflib_admin_intr_deferred(sc->ctx); 740 return (FILTER_HANDLED); 741 } 742 743 static int 744 mgb_rxq_intr(void *xsc) 745 { 746 struct mgb_softc *sc; 747 if_softc_ctx_t scctx; 748 uint32_t intr_sts, intr_en; 749 int qidx; 750 751 sc = xsc; 752 scctx = iflib_get_softc_ctx(sc->ctx); 753 754 intr_sts = CSR_READ_REG(sc, MGB_INTR_STS); 755 intr_en = CSR_READ_REG(sc, MGB_INTR_ENBL_SET); 756 intr_sts &= intr_en; 757 758 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) { 759 if ((intr_sts & MGB_INTR_STS_RX(qidx))){ 760 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, 761 MGB_INTR_STS_RX(qidx)); 762 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_RX(qidx)); 763 } 764 } 765 return (FILTER_SCHEDULE_THREAD); 766 } 767 768 static int 769 mgb_admin_intr(void *xsc) 770 { 771 struct mgb_softc *sc; 772 if_softc_ctx_t scctx; 773 uint32_t intr_sts, intr_en; 774 int qidx; 775 776 sc = xsc; 777 scctx = iflib_get_softc_ctx(sc->ctx); 778 779 intr_sts = CSR_READ_REG(sc, MGB_INTR_STS); 780 intr_en = CSR_READ_REG(sc, MGB_INTR_ENBL_SET); 781 intr_sts &= intr_en; 782 783 /* 784 * NOTE: Debugging printfs here 785 * will likely cause interrupt test failure. 786 */ 787 788 /* TODO: shouldn't continue if suspended */ 789 if ((intr_sts & MGB_INTR_STS_ANY) == 0) 790 { 791 device_printf(sc->dev, "non-mgb interrupt triggered.\n"); 792 return (FILTER_SCHEDULE_THREAD); 793 } 794 if ((intr_sts & MGB_INTR_STS_TEST) != 0) 795 { 796 sc->isr_test_flag = true; 797 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST); 798 return (FILTER_HANDLED); 799 } 800 if ((intr_sts & MGB_INTR_STS_RX_ANY) != 0) 801 { 802 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) { 803 if ((intr_sts & MGB_INTR_STS_RX(qidx))){ 804 iflib_rx_intr_deferred(sc->ctx, qidx); 805 } 806 } 807 return (FILTER_HANDLED); 808 } 809 /* XXX: TX interrupts should not occur */ 810 if ((intr_sts & MGB_INTR_STS_TX_ANY) != 0) 811 { 812 for (qidx = 0; qidx < scctx->isc_ntxqsets; qidx++) { 813 if ((intr_sts & MGB_INTR_STS_RX(qidx))) { 814 /* clear the interrupt sts and run handler */ 815 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, 816 MGB_INTR_STS_TX(qidx)); 817 CSR_WRITE_REG(sc, MGB_INTR_STS, 818 MGB_INTR_STS_TX(qidx)); 819 iflib_tx_intr_deferred(sc->ctx, qidx); 820 } 821 } 822 return (FILTER_HANDLED); 823 } 824 825 return (FILTER_SCHEDULE_THREAD); 826 } 827 828 static int 829 mgb_msix_intr_assign(if_ctx_t ctx, int msix) 830 { 831 struct mgb_softc *sc; 832 if_softc_ctx_t scctx; 833 int error, i, vectorid; 834 char irq_name[16]; 835 836 sc = iflib_get_softc(ctx); 837 scctx = iflib_get_softc_ctx(ctx); 838 839 KASSERT(scctx->isc_nrxqsets == 1 && scctx->isc_ntxqsets == 1, 840 ("num rxqsets/txqsets != 1 ")); 841 842 /* 843 * First vector should be admin interrupts, others vectors are TX/RX 844 * 845 * RIDs start at 1, and vector ids start at 0. 846 */ 847 vectorid = 0; 848 error = iflib_irq_alloc_generic(ctx, &sc->admin_irq, vectorid + 1, 849 IFLIB_INTR_ADMIN, mgb_admin_intr, sc, 0, "admin"); 850 if (error) { 851 device_printf(sc->dev, 852 "Failed to register admin interrupt handler\n"); 853 return (error); 854 } 855 856 for (i = 0; i < scctx->isc_nrxqsets; i++) { 857 vectorid++; 858 snprintf(irq_name, sizeof(irq_name), "rxq%d", i); 859 error = iflib_irq_alloc_generic(ctx, &sc->rx_irq, vectorid + 1, 860 IFLIB_INTR_RX, mgb_rxq_intr, sc, i, irq_name); 861 if (error) { 862 device_printf(sc->dev, 863 "Failed to register rxq %d interrupt handler\n", i); 864 return (error); 865 } 866 CSR_UPDATE_REG(sc, MGB_INTR_VEC_RX_MAP, 867 MGB_INTR_VEC_MAP(vectorid, i)); 868 } 869 870 /* Not actually mapping hw TX interrupts ... */ 871 for (i = 0; i < scctx->isc_ntxqsets; i++) { 872 snprintf(irq_name, sizeof(irq_name), "txq%d", i); 873 iflib_softirq_alloc_generic(ctx, NULL, IFLIB_INTR_TX, NULL, i, 874 irq_name); 875 } 876 877 return (0); 878 } 879 880 static void 881 mgb_intr_enable_all(if_ctx_t ctx) 882 { 883 struct mgb_softc *sc; 884 if_softc_ctx_t scctx; 885 int i, dmac_enable = 0, intr_sts = 0, vec_en = 0; 886 887 sc = iflib_get_softc(ctx); 888 scctx = iflib_get_softc_ctx(ctx); 889 intr_sts |= MGB_INTR_STS_ANY; 890 vec_en |= MGB_INTR_STS_ANY; 891 892 for (i = 0; i < scctx->isc_nrxqsets; i++) { 893 intr_sts |= MGB_INTR_STS_RX(i); 894 dmac_enable |= MGB_DMAC_RX_INTR_ENBL(i); 895 vec_en |= MGB_INTR_RX_VEC_STS(i); 896 } 897 898 /* TX interrupts aren't needed ... */ 899 900 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, intr_sts); 901 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, vec_en); 902 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, dmac_enable); 903 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, dmac_enable); 904 } 905 906 static void 907 mgb_intr_disable_all(if_ctx_t ctx) 908 { 909 struct mgb_softc *sc; 910 911 sc = iflib_get_softc(ctx); 912 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, UINT32_MAX); 913 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_CLR, UINT32_MAX); 914 CSR_WRITE_REG(sc, MGB_INTR_STS, UINT32_MAX); 915 916 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_CLR, UINT32_MAX); 917 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, UINT32_MAX); 918 } 919 920 static int 921 mgb_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 922 { 923 /* called after successful rx isr */ 924 struct mgb_softc *sc; 925 926 sc = iflib_get_softc(ctx); 927 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, MGB_INTR_RX_VEC_STS(qid)); 928 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, MGB_INTR_STS_RX(qid)); 929 930 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, MGB_DMAC_RX_INTR_ENBL(qid)); 931 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, MGB_DMAC_RX_INTR_ENBL(qid)); 932 return (0); 933 } 934 935 static int 936 mgb_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 937 { 938 /* XXX: not called (since tx interrupts not used) */ 939 struct mgb_softc *sc; 940 941 sc = iflib_get_softc(ctx); 942 943 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, MGB_INTR_STS_TX(qid)); 944 945 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, MGB_DMAC_TX_INTR_ENBL(qid)); 946 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, MGB_DMAC_TX_INTR_ENBL(qid)); 947 return (0); 948 } 949 950 static bool 951 mgb_intr_test(struct mgb_softc *sc) 952 { 953 int i; 954 955 sc->isr_test_flag = false; 956 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST); 957 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, MGB_INTR_STS_ANY); 958 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, 959 MGB_INTR_STS_ANY | MGB_INTR_STS_TEST); 960 CSR_WRITE_REG(sc, MGB_INTR_SET, MGB_INTR_STS_TEST); 961 if (sc->isr_test_flag) 962 return true; 963 for (i = 0; i < MGB_TIMEOUT; i++) { 964 DELAY(10); 965 if (sc->isr_test_flag) 966 break; 967 } 968 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, MGB_INTR_STS_TEST); 969 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST); 970 return sc->isr_test_flag; 971 } 972 973 static int 974 mgb_isc_txd_encap(void *xsc , if_pkt_info_t ipi) 975 { 976 struct mgb_softc *sc; 977 if_softc_ctx_t scctx; 978 struct mgb_ring_data *rdata; 979 struct mgb_ring_desc *txd; 980 bus_dma_segment_t *segs; 981 qidx_t pidx, nsegs; 982 int i; 983 984 KASSERT(ipi->ipi_qsidx == 0, 985 ("tried to refill TX Channel %d.\n", ipi->ipi_qsidx)); 986 sc = xsc; 987 scctx = iflib_get_softc_ctx(sc->ctx); 988 rdata = &sc->tx_ring_data; 989 990 pidx = ipi->ipi_pidx; 991 segs = ipi->ipi_segs; 992 nsegs = ipi->ipi_nsegs; 993 994 /* For each seg, create a descriptor */ 995 for (i = 0; i < nsegs; ++i) { 996 KASSERT(nsegs == 1, ("Multisegment packet !!!!!\n")); 997 txd = &rdata->ring[pidx]; 998 txd->ctl = htole32( 999 (segs[i].ds_len & MGB_DESC_CTL_BUFLEN_MASK ) | 1000 /* 1001 * XXX: This will be wrong in the multipacket case 1002 * I suspect FS should be for the first packet and 1003 * LS should be for the last packet 1004 */ 1005 MGB_TX_DESC_CTL_FS | MGB_TX_DESC_CTL_LS | 1006 MGB_DESC_CTL_FCS); 1007 txd->addr.low = htole32(CSR_TRANSLATE_ADDR_LOW32( 1008 segs[i].ds_addr)); 1009 txd->addr.high = htole32(CSR_TRANSLATE_ADDR_HIGH32( 1010 segs[i].ds_addr)); 1011 txd->sts = htole32( 1012 (segs[i].ds_len << 16) & MGB_DESC_FRAME_LEN_MASK); 1013 pidx = MGB_NEXT_RING_IDX(pidx); 1014 } 1015 ipi->ipi_new_pidx = pidx; 1016 return (0); 1017 } 1018 1019 static void 1020 mgb_isc_txd_flush(void *xsc, uint16_t txqid, qidx_t pidx) 1021 { 1022 struct mgb_softc *sc; 1023 struct mgb_ring_data *rdata; 1024 1025 KASSERT(txqid == 0, ("tried to flush TX Channel %d.\n", txqid)); 1026 sc = xsc; 1027 rdata = &sc->tx_ring_data; 1028 1029 if (rdata->last_tail != pidx) { 1030 rdata->last_tail = pidx; 1031 CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(txqid), rdata->last_tail); 1032 } 1033 } 1034 1035 static int 1036 mgb_isc_txd_credits_update(void *xsc, uint16_t txqid, bool clear) 1037 { 1038 struct mgb_softc *sc; 1039 struct mgb_ring_desc *txd; 1040 struct mgb_ring_data *rdata; 1041 int processed = 0; 1042 1043 /* 1044 * > If clear is true, we need to report the number of TX command ring 1045 * > descriptors that have been processed by the device. If clear is 1046 * > false, we just need to report whether or not at least one TX 1047 * > command ring descriptor has been processed by the device. 1048 * - vmx driver 1049 */ 1050 KASSERT(txqid == 0, ("tried to credits_update TX Channel %d.\n", 1051 txqid)); 1052 sc = xsc; 1053 rdata = &sc->tx_ring_data; 1054 1055 while (*(rdata->head_wb) != rdata->last_head) { 1056 if (!clear) 1057 return 1; 1058 1059 txd = &rdata->ring[rdata->last_head]; 1060 memset(txd, 0, sizeof(struct mgb_ring_desc)); 1061 rdata->last_head = MGB_NEXT_RING_IDX(rdata->last_head); 1062 processed++; 1063 } 1064 1065 return (processed); 1066 } 1067 1068 static int 1069 mgb_isc_rxd_available(void *xsc, uint16_t rxqid, qidx_t idx, qidx_t budget) 1070 { 1071 struct mgb_softc *sc; 1072 if_softc_ctx_t scctx; 1073 struct mgb_ring_data *rdata; 1074 int avail = 0; 1075 1076 sc = xsc; 1077 KASSERT(rxqid == 0, ("tried to check availability in RX Channel %d.\n", 1078 rxqid)); 1079 1080 rdata = &sc->rx_ring_data; 1081 scctx = iflib_get_softc_ctx(sc->ctx); 1082 for (; idx != *(rdata->head_wb); 1083 idx = MGB_NEXT_RING_IDX(idx)) { 1084 avail++; 1085 /* XXX: Could verify desc is device owned here */ 1086 if (avail == budget) 1087 break; 1088 } 1089 return (avail); 1090 } 1091 1092 static int 1093 mgb_isc_rxd_pkt_get(void *xsc, if_rxd_info_t ri) 1094 { 1095 struct mgb_softc *sc; 1096 struct mgb_ring_data *rdata; 1097 struct mgb_ring_desc rxd; 1098 int total_len; 1099 1100 KASSERT(ri->iri_qsidx == 0, 1101 ("tried to check availability in RX Channel %d\n", ri->iri_qsidx)); 1102 sc = xsc; 1103 total_len = 0; 1104 rdata = &sc->rx_ring_data; 1105 1106 while (*(rdata->head_wb) != rdata->last_head) { 1107 /* copy ring desc and do swapping */ 1108 rxd = rdata->ring[rdata->last_head]; 1109 rxd.ctl = le32toh(rxd.ctl); 1110 rxd.addr.low = le32toh(rxd.ctl); 1111 rxd.addr.high = le32toh(rxd.ctl); 1112 rxd.sts = le32toh(rxd.ctl); 1113 1114 if ((rxd.ctl & MGB_DESC_CTL_OWN) != 0) { 1115 device_printf(sc->dev, 1116 "Tried to read descriptor ... " 1117 "found that it's owned by the driver\n"); 1118 return EINVAL; 1119 } 1120 if ((rxd.ctl & MGB_RX_DESC_CTL_FS) == 0) { 1121 device_printf(sc->dev, 1122 "Tried to read descriptor ... " 1123 "found that FS is not set.\n"); 1124 device_printf(sc->dev, "Tried to read descriptor ... that it FS is not set.\n"); 1125 return EINVAL; 1126 } 1127 /* XXX: Multi-packet support */ 1128 if ((rxd.ctl & MGB_RX_DESC_CTL_LS) == 0) { 1129 device_printf(sc->dev, 1130 "Tried to read descriptor ... " 1131 "found that LS is not set. (Multi-buffer packets not yet supported)\n"); 1132 return EINVAL; 1133 } 1134 ri->iri_frags[0].irf_flid = 0; 1135 ri->iri_frags[0].irf_idx = rdata->last_head; 1136 ri->iri_frags[0].irf_len = MGB_DESC_GET_FRAME_LEN(&rxd); 1137 total_len += ri->iri_frags[0].irf_len; 1138 1139 rdata->last_head = MGB_NEXT_RING_IDX(rdata->last_head); 1140 break; 1141 } 1142 ri->iri_nfrags = 1; 1143 ri->iri_len = total_len; 1144 1145 return (0); 1146 } 1147 1148 static void 1149 mgb_isc_rxd_refill(void *xsc, if_rxd_update_t iru) 1150 { 1151 if_softc_ctx_t scctx; 1152 struct mgb_softc *sc; 1153 struct mgb_ring_data *rdata; 1154 struct mgb_ring_desc *rxd; 1155 uint64_t *paddrs; 1156 qidx_t *idxs; 1157 qidx_t idx; 1158 int count, len; 1159 1160 count = iru->iru_count; 1161 len = iru->iru_buf_size; 1162 idxs = iru->iru_idxs; 1163 paddrs = iru->iru_paddrs; 1164 KASSERT(iru->iru_qsidx == 0, 1165 ("tried to refill RX Channel %d.\n", iru->iru_qsidx)); 1166 1167 sc = xsc; 1168 scctx = iflib_get_softc_ctx(sc->ctx); 1169 rdata = &sc->rx_ring_data; 1170 1171 while (count > 0) { 1172 idx = idxs[--count]; 1173 rxd = &rdata->ring[idx]; 1174 1175 rxd->sts = 0; 1176 rxd->addr.low = 1177 htole32(CSR_TRANSLATE_ADDR_LOW32(paddrs[count])); 1178 rxd->addr.high = 1179 htole32(CSR_TRANSLATE_ADDR_HIGH32(paddrs[count])); 1180 rxd->ctl = htole32(MGB_DESC_CTL_OWN | 1181 (len & MGB_DESC_CTL_BUFLEN_MASK)); 1182 } 1183 return; 1184 } 1185 1186 static void 1187 mgb_isc_rxd_flush(void *xsc, uint16_t rxqid, uint8_t flid, qidx_t pidx) 1188 { 1189 struct mgb_softc *sc; 1190 1191 sc = xsc; 1192 1193 KASSERT(rxqid == 0, ("tried to flush RX Channel %d.\n", rxqid)); 1194 sc->rx_ring_data.last_tail = pidx; 1195 CSR_WRITE_REG(sc, MGB_DMA_RX_TAIL(rxqid), sc->rx_ring_data.last_tail); 1196 return; 1197 } 1198 1199 static int 1200 mgb_test_bar(struct mgb_softc *sc) 1201 { 1202 uint32_t id_rev, dev_id, rev; 1203 1204 id_rev = CSR_READ_REG(sc, 0); 1205 dev_id = id_rev >> 16; 1206 rev = id_rev & 0xFFFF; 1207 if (dev_id == MGB_LAN7430_DEVICE_ID || 1208 dev_id == MGB_LAN7431_DEVICE_ID) { 1209 return 0; 1210 } else { 1211 device_printf(sc->dev, "ID check failed.\n"); 1212 return ENXIO; 1213 } 1214 } 1215 1216 static int 1217 mgb_alloc_regs(struct mgb_softc *sc) 1218 { 1219 int rid; 1220 1221 rid = PCIR_BAR(MGB_BAR); 1222 pci_enable_busmaster(sc->dev); 1223 sc->regs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1224 &rid, RF_ACTIVE); 1225 if (sc->regs == NULL) 1226 return ENXIO; 1227 1228 return (0); 1229 } 1230 1231 static int 1232 mgb_release_regs(struct mgb_softc *sc) 1233 { 1234 int error = 0; 1235 1236 if (sc->regs != NULL) 1237 error = bus_release_resource(sc->dev, SYS_RES_MEMORY, 1238 rman_get_rid(sc->regs), sc->regs); 1239 sc->regs = NULL; 1240 pci_disable_busmaster(sc->dev); 1241 return error; 1242 } 1243 1244 static int 1245 mgb_dma_init(struct mgb_softc *sc) 1246 { 1247 if_softc_ctx_t scctx; 1248 int ch, error = 0; 1249 1250 scctx = iflib_get_softc_ctx(sc->ctx); 1251 1252 for (ch = 0; ch < scctx->isc_nrxqsets; ch++) 1253 if ((error = mgb_dma_rx_ring_init(sc, ch))) 1254 goto fail; 1255 1256 for (ch = 0; ch < scctx->isc_nrxqsets; ch++) 1257 if ((error = mgb_dma_tx_ring_init(sc, ch))) 1258 goto fail; 1259 1260 fail: 1261 return error; 1262 } 1263 1264 static int 1265 mgb_dma_rx_ring_init(struct mgb_softc *sc, int channel) 1266 { 1267 struct mgb_ring_data *rdata; 1268 int ring_config, error = 0; 1269 1270 rdata = &sc->rx_ring_data; 1271 mgb_dmac_control(sc, MGB_DMAC_RX_START, 0, DMAC_RESET); 1272 KASSERT(MGB_DMAC_STATE_IS_INITIAL(sc, MGB_DMAC_RX_START, channel), 1273 ("Trying to init channels when not in init state\n")); 1274 1275 /* write ring address */ 1276 if (rdata->ring_bus_addr == 0) { 1277 device_printf(sc->dev, "Invalid ring bus addr.\n"); 1278 goto fail; 1279 } 1280 1281 CSR_WRITE_REG(sc, MGB_DMA_RX_BASE_H(channel), 1282 CSR_TRANSLATE_ADDR_HIGH32(rdata->ring_bus_addr)); 1283 CSR_WRITE_REG(sc, MGB_DMA_RX_BASE_L(channel), 1284 CSR_TRANSLATE_ADDR_LOW32(rdata->ring_bus_addr)); 1285 1286 /* write head pointer writeback address */ 1287 if (rdata->head_wb_bus_addr == 0) { 1288 device_printf(sc->dev, "Invalid head wb bus addr.\n"); 1289 goto fail; 1290 } 1291 CSR_WRITE_REG(sc, MGB_DMA_RX_HEAD_WB_H(channel), 1292 CSR_TRANSLATE_ADDR_HIGH32(rdata->head_wb_bus_addr)); 1293 CSR_WRITE_REG(sc, MGB_DMA_RX_HEAD_WB_L(channel), 1294 CSR_TRANSLATE_ADDR_LOW32(rdata->head_wb_bus_addr)); 1295 1296 /* Enable head pointer writeback */ 1297 CSR_WRITE_REG(sc, MGB_DMA_RX_CONFIG0(channel), MGB_DMA_HEAD_WB_ENBL); 1298 1299 ring_config = CSR_READ_REG(sc, MGB_DMA_RX_CONFIG1(channel)); 1300 /* ring size */ 1301 ring_config &= ~MGB_DMA_RING_LEN_MASK; 1302 ring_config |= (MGB_DMA_RING_SIZE & MGB_DMA_RING_LEN_MASK); 1303 /* packet padding (PAD_2 is better for IP header alignment ...) */ 1304 ring_config &= ~MGB_DMA_RING_PAD_MASK; 1305 ring_config |= (MGB_DMA_RING_PAD_0 & MGB_DMA_RING_PAD_MASK); 1306 1307 CSR_WRITE_REG(sc, MGB_DMA_RX_CONFIG1(channel), ring_config); 1308 1309 rdata->last_head = CSR_READ_REG(sc, MGB_DMA_RX_HEAD(channel)); 1310 1311 mgb_fct_control(sc, MGB_FCT_RX_CTL, channel, FCT_RESET); 1312 if (error != 0) { 1313 device_printf(sc->dev, "Failed to reset RX FCT.\n"); 1314 goto fail; 1315 } 1316 mgb_fct_control(sc, MGB_FCT_RX_CTL, channel, FCT_ENABLE); 1317 if (error != 0) { 1318 device_printf(sc->dev, "Failed to enable RX FCT.\n"); 1319 goto fail; 1320 } 1321 mgb_dmac_control(sc, MGB_DMAC_RX_START, channel, DMAC_START); 1322 if (error != 0) 1323 device_printf(sc->dev, "Failed to start RX DMAC.\n"); 1324 fail: 1325 return (error); 1326 } 1327 1328 static int 1329 mgb_dma_tx_ring_init(struct mgb_softc *sc, int channel) 1330 { 1331 struct mgb_ring_data *rdata; 1332 int ring_config, error = 0; 1333 1334 rdata = &sc->tx_ring_data; 1335 if ((error = mgb_fct_control(sc, MGB_FCT_TX_CTL, channel, FCT_RESET))) { 1336 device_printf(sc->dev, "Failed to reset TX FCT.\n"); 1337 goto fail; 1338 } 1339 if ((error = mgb_fct_control(sc, MGB_FCT_TX_CTL, channel, 1340 FCT_ENABLE))) { 1341 device_printf(sc->dev, "Failed to enable TX FCT.\n"); 1342 goto fail; 1343 } 1344 if ((error = mgb_dmac_control(sc, MGB_DMAC_TX_START, channel, 1345 DMAC_RESET))) { 1346 device_printf(sc->dev, "Failed to reset TX DMAC.\n"); 1347 goto fail; 1348 } 1349 KASSERT(MGB_DMAC_STATE_IS_INITIAL(sc, MGB_DMAC_TX_START, channel), 1350 ("Trying to init channels in not init state\n")); 1351 1352 /* write ring address */ 1353 if (rdata->ring_bus_addr == 0) { 1354 device_printf(sc->dev, "Invalid ring bus addr.\n"); 1355 goto fail; 1356 } 1357 CSR_WRITE_REG(sc, MGB_DMA_TX_BASE_H(channel), 1358 CSR_TRANSLATE_ADDR_HIGH32(rdata->ring_bus_addr)); 1359 CSR_WRITE_REG(sc, MGB_DMA_TX_BASE_L(channel), 1360 CSR_TRANSLATE_ADDR_LOW32(rdata->ring_bus_addr)); 1361 1362 /* write ring size */ 1363 ring_config = CSR_READ_REG(sc, MGB_DMA_TX_CONFIG1(channel)); 1364 ring_config &= ~MGB_DMA_RING_LEN_MASK; 1365 ring_config |= (MGB_DMA_RING_SIZE & MGB_DMA_RING_LEN_MASK); 1366 CSR_WRITE_REG(sc, MGB_DMA_TX_CONFIG1(channel), ring_config); 1367 1368 /* Enable interrupt on completion and head pointer writeback */ 1369 ring_config = (MGB_DMA_HEAD_WB_LS_ENBL | MGB_DMA_HEAD_WB_ENBL); 1370 CSR_WRITE_REG(sc, MGB_DMA_TX_CONFIG0(channel), ring_config); 1371 1372 /* write head pointer writeback address */ 1373 if (rdata->head_wb_bus_addr == 0) { 1374 device_printf(sc->dev, "Invalid head wb bus addr.\n"); 1375 goto fail; 1376 } 1377 CSR_WRITE_REG(sc, MGB_DMA_TX_HEAD_WB_H(channel), 1378 CSR_TRANSLATE_ADDR_HIGH32(rdata->head_wb_bus_addr)); 1379 CSR_WRITE_REG(sc, MGB_DMA_TX_HEAD_WB_L(channel), 1380 CSR_TRANSLATE_ADDR_LOW32(rdata->head_wb_bus_addr)); 1381 1382 rdata->last_head = CSR_READ_REG(sc, MGB_DMA_TX_HEAD(channel)); 1383 KASSERT(rdata->last_head == 0, ("MGB_DMA_TX_HEAD was not reset.\n")); 1384 rdata->last_tail = 0; 1385 CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(channel), rdata->last_tail); 1386 1387 if ((error = mgb_dmac_control(sc, MGB_DMAC_TX_START, channel, 1388 DMAC_START))) 1389 device_printf(sc->dev, "Failed to start TX DMAC.\n"); 1390 fail: 1391 return error; 1392 } 1393 1394 static int 1395 mgb_dmac_control(struct mgb_softc *sc, int start, int channel, 1396 enum mgb_dmac_cmd cmd) 1397 { 1398 int error = 0; 1399 1400 switch (cmd) { 1401 case DMAC_RESET: 1402 CSR_WRITE_REG(sc, MGB_DMAC_CMD, 1403 MGB_DMAC_CMD_RESET(start, channel)); 1404 error = mgb_wait_for_bits(sc, MGB_DMAC_CMD, 0, 1405 MGB_DMAC_CMD_RESET(start, channel)); 1406 break; 1407 1408 case DMAC_START: 1409 /* 1410 * NOTE: this simplifies the logic, since it will never 1411 * try to start in STOP_PENDING, but it also increases work. 1412 */ 1413 error = mgb_dmac_control(sc, start, channel, DMAC_STOP); 1414 if (error != 0) 1415 return error; 1416 CSR_WRITE_REG(sc, MGB_DMAC_CMD, 1417 MGB_DMAC_CMD_START(start, channel)); 1418 break; 1419 1420 case DMAC_STOP: 1421 CSR_WRITE_REG(sc, MGB_DMAC_CMD, 1422 MGB_DMAC_CMD_STOP(start, channel)); 1423 error = mgb_wait_for_bits(sc, MGB_DMAC_CMD, 1424 MGB_DMAC_CMD_STOP(start, channel), 1425 MGB_DMAC_CMD_START(start, channel)); 1426 break; 1427 } 1428 return error; 1429 } 1430 1431 static int 1432 mgb_fct_control(struct mgb_softc *sc, int reg, int channel, 1433 enum mgb_fct_cmd cmd) 1434 { 1435 1436 switch (cmd) { 1437 case FCT_RESET: 1438 CSR_WRITE_REG(sc, reg, MGB_FCT_RESET(channel)); 1439 return mgb_wait_for_bits(sc, reg, 0, MGB_FCT_RESET(channel)); 1440 case FCT_ENABLE: 1441 CSR_WRITE_REG(sc, reg, MGB_FCT_ENBL(channel)); 1442 return (0); 1443 case FCT_DISABLE: 1444 CSR_WRITE_REG(sc, reg, MGB_FCT_DSBL(channel)); 1445 return mgb_wait_for_bits(sc, reg, 0, MGB_FCT_ENBL(channel)); 1446 } 1447 } 1448 1449 static int 1450 mgb_hw_teardown(struct mgb_softc *sc) 1451 { 1452 int err = 0; 1453 1454 /* Stop MAC */ 1455 CSR_CLEAR_REG(sc, MGB_MAC_RX, MGB_MAC_ENBL); 1456 CSR_WRITE_REG(sc, MGB_MAC_TX, MGB_MAC_ENBL); 1457 if ((err = mgb_wait_for_bits(sc, MGB_MAC_RX, MGB_MAC_DSBL, 0))) 1458 return (err); 1459 if ((err = mgb_wait_for_bits(sc, MGB_MAC_TX, MGB_MAC_DSBL, 0))) 1460 return (err); 1461 return (err); 1462 } 1463 1464 static int 1465 mgb_hw_init(struct mgb_softc *sc) 1466 { 1467 int error = 0; 1468 1469 error = mgb_hw_reset(sc); 1470 if (error != 0) 1471 goto fail; 1472 1473 mgb_mac_init(sc); 1474 1475 error = mgb_phy_reset(sc); 1476 if (error != 0) 1477 goto fail; 1478 1479 error = mgb_dmac_reset(sc); 1480 if (error != 0) 1481 goto fail; 1482 1483 fail: 1484 return error; 1485 } 1486 1487 static int 1488 mgb_hw_reset(struct mgb_softc *sc) 1489 { 1490 1491 CSR_UPDATE_REG(sc, MGB_HW_CFG, MGB_LITE_RESET); 1492 return (mgb_wait_for_bits(sc, MGB_HW_CFG, 0, MGB_LITE_RESET)); 1493 } 1494 1495 static int 1496 mgb_mac_init(struct mgb_softc *sc) 1497 { 1498 1499 /** 1500 * enable automatic duplex detection and 1501 * automatic speed detection 1502 */ 1503 CSR_UPDATE_REG(sc, MGB_MAC_CR, MGB_MAC_ADD_ENBL | MGB_MAC_ASD_ENBL); 1504 CSR_UPDATE_REG(sc, MGB_MAC_TX, MGB_MAC_ENBL); 1505 CSR_UPDATE_REG(sc, MGB_MAC_RX, MGB_MAC_ENBL); 1506 1507 return MGB_STS_OK; 1508 } 1509 1510 static int 1511 mgb_phy_reset(struct mgb_softc *sc) 1512 { 1513 1514 CSR_UPDATE_BYTE(sc, MGB_PMT_CTL, MGB_PHY_RESET); 1515 if (mgb_wait_for_bits(sc, MGB_PMT_CTL, 0, MGB_PHY_RESET) == 1516 MGB_STS_TIMEOUT) 1517 return MGB_STS_TIMEOUT; 1518 return (mgb_wait_for_bits(sc, MGB_PMT_CTL, MGB_PHY_READY, 0)); 1519 } 1520 1521 static int 1522 mgb_dmac_reset(struct mgb_softc *sc) 1523 { 1524 1525 CSR_WRITE_REG(sc, MGB_DMAC_CMD, MGB_DMAC_RESET); 1526 return (mgb_wait_for_bits(sc, MGB_DMAC_CMD, 0, MGB_DMAC_RESET)); 1527 } 1528 1529 static int 1530 mgb_wait_for_bits(struct mgb_softc *sc, int reg, int set_bits, int clear_bits) 1531 { 1532 int i, val; 1533 1534 i = 0; 1535 do { 1536 /* 1537 * XXX: Datasheets states delay should be > 5 microseconds 1538 * for device reset. 1539 */ 1540 DELAY(100); 1541 val = CSR_READ_REG(sc, reg); 1542 if ((val & set_bits) == set_bits && 1543 (val & clear_bits) == 0) 1544 return MGB_STS_OK; 1545 } while (i++ < MGB_TIMEOUT); 1546 1547 return MGB_STS_TIMEOUT; 1548 } 1549 1550 static void 1551 mgb_get_ethaddr(struct mgb_softc *sc, struct ether_addr *dest) 1552 { 1553 1554 CSR_READ_REG_BYTES(sc, MGB_MAC_ADDR_BASE_L, &dest->octet[0], 4); 1555 CSR_READ_REG_BYTES(sc, MGB_MAC_ADDR_BASE_H, &dest->octet[4], 2); 1556 } 1557 1558 static int 1559 mgb_miibus_readreg(device_t dev, int phy, int reg) 1560 { 1561 struct mgb_softc *sc; 1562 int mii_access; 1563 1564 sc = iflib_get_softc(device_get_softc(dev)); 1565 1566 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == 1567 MGB_STS_TIMEOUT) 1568 return EIO; 1569 mii_access = (phy & MGB_MII_PHY_ADDR_MASK) << MGB_MII_PHY_ADDR_SHIFT; 1570 mii_access |= (reg & MGB_MII_REG_ADDR_MASK) << MGB_MII_REG_ADDR_SHIFT; 1571 mii_access |= MGB_MII_BUSY | MGB_MII_READ; 1572 CSR_WRITE_REG(sc, MGB_MII_ACCESS, mii_access); 1573 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == 1574 MGB_STS_TIMEOUT) 1575 return EIO; 1576 return (CSR_READ_2_BYTES(sc, MGB_MII_DATA)); 1577 } 1578 1579 static int 1580 mgb_miibus_writereg(device_t dev, int phy, int reg, int data) 1581 { 1582 struct mgb_softc *sc; 1583 int mii_access; 1584 1585 sc = iflib_get_softc(device_get_softc(dev)); 1586 1587 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 1588 0, MGB_MII_BUSY) == MGB_STS_TIMEOUT) 1589 return EIO; 1590 mii_access = (phy & MGB_MII_PHY_ADDR_MASK) << MGB_MII_PHY_ADDR_SHIFT; 1591 mii_access |= (reg & MGB_MII_REG_ADDR_MASK) << MGB_MII_REG_ADDR_SHIFT; 1592 mii_access |= MGB_MII_BUSY | MGB_MII_WRITE; 1593 CSR_WRITE_REG(sc, MGB_MII_DATA, data); 1594 CSR_WRITE_REG(sc, MGB_MII_ACCESS, mii_access); 1595 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) == 1596 MGB_STS_TIMEOUT) 1597 return EIO; 1598 return 0; 1599 } 1600 1601 /* XXX: May need to lock these up */ 1602 static void 1603 mgb_miibus_statchg(device_t dev) 1604 { 1605 struct mgb_softc *sc; 1606 struct mii_data *miid; 1607 1608 sc = iflib_get_softc(device_get_softc(dev)); 1609 miid = device_get_softc(sc->miibus); 1610 /* Update baudrate in iflib */ 1611 sc->baudrate = ifmedia_baudrate(miid->mii_media_active); 1612 iflib_link_state_change(sc->ctx, sc->link_state, sc->baudrate); 1613 } 1614 1615 static void 1616 mgb_miibus_linkchg(device_t dev) 1617 { 1618 struct mgb_softc *sc; 1619 struct mii_data *miid; 1620 int link_state; 1621 1622 sc = iflib_get_softc(device_get_softc(dev)); 1623 miid = device_get_softc(sc->miibus); 1624 /* XXX: copied from miibus_linkchg **/ 1625 if (miid->mii_media_status & IFM_AVALID) { 1626 if (miid->mii_media_status & IFM_ACTIVE) 1627 link_state = LINK_STATE_UP; 1628 else 1629 link_state = LINK_STATE_DOWN; 1630 } else 1631 link_state = LINK_STATE_UNKNOWN; 1632 sc->link_state = link_state; 1633 iflib_link_state_change(sc->ctx, sc->link_state, sc->baudrate); 1634 } 1635