1 /*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _MFIREG_H 28 #define _MFIREG_H 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * MegaRAID SAS MFI firmware definitions 35 * 36 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 37 * new firmware interface from the old AMI MegaRAID one, and there is no 38 * reason why this interface should be limited to just SAS. In any case, LSI 39 * seems to also call this interface 'MFI', so that will be used here. 40 */ 41 42 /* 43 * Start with the register set. All registers are 32 bits wide. 44 * The usual Intel IOP style setup. 45 */ 46 #define MFI_IMSG0 0x10 /* Inbound message 0 */ 47 #define MFI_IMSG1 0x14 /* Inbound message 1 */ 48 #define MFI_OMSG0 0x18 /* Outbound message 0 */ 49 #define MFI_OMSG1 0x1c /* Outbound message 1 */ 50 #define MFI_IDB 0x20 /* Inbound doorbell */ 51 #define MFI_ISTS 0x24 /* Inbound interrupt status */ 52 #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 53 #define MFI_ODB 0x2c /* Outbound doorbell */ 54 #define MFI_OSTS 0x30 /* Outbound interrupt status */ 55 #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 56 #define MFI_IQP 0x40 /* Inbound queue port */ 57 #define MFI_OQP 0x44 /* Outbound queue port */ 58 59 /* Bits for MFI_OSTS */ 60 #define MFI_OSTS_INTR_VALID 0x00000002 61 62 /* 63 * Firmware state values. Found in OMSG0 during initialization. 64 */ 65 #define MFI_FWSTATE_MASK 0xf0000000 66 #define MFI_FWSTATE_UNDEFINED 0x00000000 67 #define MFI_FWSTATE_BB_INIT 0x10000000 68 #define MFI_FWSTATE_FW_INIT 0x40000000 69 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 70 #define MFI_FWSTATE_FW_INIT_2 0x70000000 71 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 72 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 73 #define MFI_FWSTATE_READY 0xb0000000 74 #define MFI_FWSTATE_OPERATIONAL 0xc0000000 75 #define MFI_FWSTATE_FAULT 0xf0000000 76 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 77 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 78 79 /* 80 * Control bits to drive the card to ready state. These go into the IDB 81 * register. 82 */ 83 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 84 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 85 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 86 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 87 88 /* MFI Commands */ 89 typedef enum { 90 MFI_CMD_INIT = 0x00, 91 MFI_CMD_LD_READ, 92 MFI_CMD_LD_WRITE, 93 MFI_CMD_LD_SCSI_IO, 94 MFI_CMD_PD_SCSI_IO, 95 MFI_CMD_DCMD, 96 MFI_CMD_ABORT, 97 MFI_CMD_SMP, 98 MFI_CMD_STP 99 } mfi_cmd_t; 100 101 /* Direct commands */ 102 typedef enum { 103 MFI_DCMD_CTRL_GETINFO = 0x01010000, 104 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 105 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 106 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 107 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 108 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 109 MFI_DCMD_LD_GET_LIST = 0x03010000, 110 MFI_DCMD_LD_GET_INFO = 0x03020000, 111 MFI_DCMD_LD_GET_PROP = 0x03030000, 112 MFI_DCMD_LD_SET_PROP = 0x03040000, 113 MFI_DCMD_CLUSTER = 0x08000000, 114 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 115 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 116 } mfi_dcmd_t; 117 118 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 119 #define MFI_FLUSHCACHE_CTRL 0x01 120 #define MFI_FLUSHCACHE_DISK 0x02 121 122 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 123 #define MFI_SHUTDOWN_SPINDOWN 0x01 124 125 /* 126 * MFI Frame flags 127 */ 128 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 129 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 130 #define MFI_FRAME_SGL32 0x0000 131 #define MFI_FRAME_SGL64 0x0002 132 #define MFI_FRAME_SENSE32 0x0000 133 #define MFI_FRAME_SENSE64 0x0004 134 #define MFI_FRAME_DIR_NONE 0x0000 135 #define MFI_FRAME_DIR_WRITE 0x0008 136 #define MFI_FRAME_DIR_READ 0x0010 137 #define MFI_FRAME_DIR_BOTH 0x0018 138 139 /* MFI Status codes */ 140 typedef enum { 141 MFI_STAT_OK = 0x00, 142 MFI_STAT_INVALID_CMD, 143 MFI_STAT_INVALID_DCMD, 144 MFI_STAT_INVALID_PARAMETER, 145 MFI_STAT_INVALID_SEQUENCE_NUMBER, 146 MFI_STAT_ABORT_NOT_POSSIBLE, 147 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 148 MFI_STAT_APP_IN_USE, 149 MFI_STAT_APP_NOT_INITIALIZED, 150 MFI_STAT_ARRAY_INDEX_INVALID, 151 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 152 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 153 MFI_STAT_DEVICE_NOT_FOUND, 154 MFI_STAT_DRIVE_TOO_SMALL, 155 MFI_STAT_FLASH_ALLOC_FAIL, 156 MFI_STAT_FLASH_BUSY, 157 MFI_STAT_FLASH_ERROR = 0x10, 158 MFI_STAT_FLASH_IMAGE_BAD, 159 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 160 MFI_STAT_FLASH_NOT_OPEN, 161 MFI_STAT_FLASH_NOT_STARTED, 162 MFI_STAT_FLUSH_FAILED, 163 MFI_STAT_HOST_CODE_NOT_FOUNT, 164 MFI_STAT_LD_CC_IN_PROGRESS, 165 MFI_STAT_LD_INIT_IN_PROGRESS, 166 MFI_STAT_LD_LBA_OUT_OF_RANGE, 167 MFI_STAT_LD_MAX_CONFIGURED, 168 MFI_STAT_LD_NOT_OPTIMAL, 169 MFI_STAT_LD_RBLD_IN_PROGRESS, 170 MFI_STAT_LD_RECON_IN_PROGRESS, 171 MFI_STAT_LD_WRONG_RAID_LEVEL, 172 MFI_STAT_MAX_SPARES_EXCEEDED, 173 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 174 MFI_STAT_MFC_HW_ERROR, 175 MFI_STAT_NO_HW_PRESENT, 176 MFI_STAT_NOT_FOUND, 177 MFI_STAT_NOT_IN_ENCL, 178 MFI_STAT_PD_CLEAR_IN_PROGRESS, 179 MFI_STAT_PD_TYPE_WRONG, 180 MFI_STAT_PR_DISABLED, 181 MFI_STAT_ROW_INDEX_INVALID, 182 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 183 MFI_STAT_SAS_CONFIG_INVALID_DATA, 184 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 185 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 186 MFI_STAT_SCSI_DONE_WITH_ERROR, 187 MFI_STAT_SCSI_IO_FAILED, 188 MFI_STAT_SCSI_RESERVATION_CONFLICT, 189 MFI_STAT_SHUTDOWN_FAILED = 0x30, 190 MFI_STAT_TIME_NOT_SET, 191 MFI_STAT_WRONG_STATE, 192 MFI_STAT_LD_OFFLINE, 193 MFI_STAT_PEER_NOTIFICATION_REJECTED, 194 MFI_STAT_PEER_NOTIFICATION_FAILED, 195 MFI_STAT_RESERVATION_IN_PROGRESS, 196 MFI_STAT_I2C_ERRORS_DETECTED, 197 MFI_STAT_PCI_ERRORS_DETECTED, 198 MFI_STAT_INVALID_STATUS = 0xFF 199 } mfi_status_t; 200 201 typedef enum { 202 MFI_EVT_CLASS_DEBUG = -2, 203 MFI_EVT_CLASS_PROGRESS = -1, 204 MFI_EVT_CLASS_INFO = 0, 205 MFI_EVT_CLASS_WARNING = 1, 206 MFI_EVT_CLASS_CRITICAL = 2, 207 MFI_EVT_CLASS_FATAL = 3, 208 MFI_EVT_CLASS_DEAD = 4 209 } mfi_evt_class_t; 210 211 typedef enum { 212 MFI_EVT_LOCALE_LD = 0x0001, 213 MFI_EVT_LOCALE_PD = 0x0002, 214 MFI_EVT_LOCALE_ENCL = 0x0004, 215 MFI_EVT_LOCALE_BBU = 0x0008, 216 MFI_EVT_LOCALE_SAS = 0x0010, 217 MFI_EVT_LOCALE_CTRL = 0x0020, 218 MFI_EVT_LOCALE_CONFIG = 0x0040, 219 MFI_EVT_LOCALE_CLUSTER = 0x0080, 220 MFI_EVT_LOCALE_ALL = 0xffff 221 } mfi_evt_locale_t; 222 223 typedef enum { 224 MR_EVT_ARGS_NONE = 0x00, 225 MR_EVT_ARGS_CDB_SENSE, 226 MR_EVT_ARGS_LD, 227 MR_EVT_ARGS_LD_COUNT, 228 MR_EVT_ARGS_LD_LBA, 229 MR_EVT_ARGS_LD_OWNER, 230 MR_EVT_ARGS_LD_LBA_PD_LBA, 231 MR_EVT_ARGS_LD_PROG, 232 MR_EVT_ARGS_LD_STATE, 233 MR_EVT_ARGS_LD_STRIP, 234 MR_EVT_ARGS_PD, 235 MR_EVT_ARGS_PD_ERR, 236 MR_EVT_ARGS_PD_LBA, 237 MR_EVT_ARGS_PD_LBA_LD, 238 MR_EVT_ARGS_PD_PROG, 239 MR_EVT_ARGS_PD_STATE, 240 MR_EVT_ARGS_PCI, 241 MR_EVT_ARGS_RATE, 242 MR_EVT_ARGS_STR, 243 MR_EVT_ARGS_TIME, 244 MR_EVT_ARGS_ECC 245 } mfi_evt_args; 246 247 /* 248 * Other propertities and definitions 249 */ 250 #define MFI_MAX_PD_CHANNELS 2 251 #define MFI_MAX_LD_CHANNELS 2 252 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 253 #define MFI_MAX_CHANNEL_DEVS 128 254 #define MFI_DEFAULT_ID -1 255 #define MFI_MAX_LUN 8 256 #define MFI_MAX_LD 64 257 258 #define MFI_FRAME_SIZE 64 259 #define MFI_MBOX_SIZE 12 260 261 #define MFI_POLL_TIMEOUT_SECS 10 262 263 /* Allow for speedier math calculations */ 264 #define MFI_SECTOR_LEN 512 265 266 /* Scatter Gather elements */ 267 struct mfi_sg32 { 268 uint32_t addr; 269 uint32_t len; 270 } __packed; 271 272 struct mfi_sg64 { 273 uint64_t addr; 274 uint32_t len; 275 } __packed; 276 277 union mfi_sgl { 278 struct mfi_sg32 sg32[1]; 279 struct mfi_sg64 sg64[1]; 280 } __packed; 281 282 /* Message frames. All messages have a common header */ 283 struct mfi_frame_header { 284 uint8_t cmd; 285 uint8_t sense_len; 286 uint8_t cmd_status; 287 uint8_t scsi_status; 288 uint8_t target_id; 289 uint8_t lun_id; 290 uint8_t cdb_len; 291 uint8_t sg_count; 292 uint32_t context; 293 uint32_t pad0; 294 uint16_t flags; 295 uint16_t timeout; 296 uint32_t data_len; 297 } __packed; 298 299 struct mfi_init_frame { 300 struct mfi_frame_header header; 301 uint32_t qinfo_new_addr_lo; 302 uint32_t qinfo_new_addr_hi; 303 uint32_t qinfo_old_addr_lo; 304 uint32_t qinfo_old_addr_hi; 305 uint32_t reserved[6]; 306 } __packed; 307 308 #define MFI_IO_FRAME_SIZE 40 309 struct mfi_io_frame { 310 struct mfi_frame_header header; 311 uint32_t sense_addr_lo; 312 uint32_t sense_addr_hi; 313 uint32_t lba_lo; 314 uint32_t lba_hi; 315 union mfi_sgl sgl; 316 } __packed; 317 318 #define MFI_PASS_FRAME_SIZE 48 319 struct mfi_pass_frame { 320 struct mfi_frame_header header; 321 uint32_t sense_addr_lo; 322 uint32_t sense_addr_hi; 323 uint8_t cdb[16]; 324 union mfi_sgl sgl; 325 } __packed; 326 327 #define MFI_DCMD_FRAME_SIZE 40 328 struct mfi_dcmd_frame { 329 struct mfi_frame_header header; 330 uint32_t opcode; 331 uint8_t mbox[MFI_MBOX_SIZE]; 332 union mfi_sgl sgl; 333 } __packed; 334 335 struct mfi_abort_frame { 336 struct mfi_frame_header header; 337 uint32_t abort_context; 338 uint32_t pad; 339 uint32_t abort_mfi_addr_lo; 340 uint32_t abort_mfi_addr_hi; 341 uint32_t reserved[6]; 342 } __packed; 343 344 struct mfi_smp_frame { 345 struct mfi_frame_header header; 346 uint64_t sas_addr; 347 union { 348 struct mfi_sg32 sg32[2]; 349 struct mfi_sg64 sg64[2]; 350 } sgl; 351 } __packed; 352 353 struct mfi_stp_frame { 354 struct mfi_frame_header header; 355 uint16_t fis[10]; 356 uint32_t stp_flags; 357 union { 358 struct mfi_sg32 sg32[2]; 359 struct mfi_sg64 sg64[2]; 360 } sgl; 361 } __packed; 362 363 union mfi_frame { 364 struct mfi_frame_header header; 365 struct mfi_init_frame init; 366 struct mfi_io_frame io; 367 struct mfi_pass_frame pass; 368 struct mfi_dcmd_frame dcmd; 369 struct mfi_abort_frame abort; 370 struct mfi_smp_frame smp; 371 struct mfi_stp_frame stp; 372 uint8_t bytes[MFI_FRAME_SIZE]; 373 }; 374 375 #define MFI_SENSE_LEN 128 376 struct mfi_sense { 377 uint8_t data[MFI_SENSE_LEN]; 378 }; 379 380 /* The queue init structure that is passed with the init message */ 381 struct mfi_init_qinfo { 382 uint32_t flags; 383 uint32_t rq_entries; 384 uint32_t rq_addr_lo; 385 uint32_t rq_addr_hi; 386 uint32_t pi_addr_lo; 387 uint32_t pi_addr_hi; 388 uint32_t ci_addr_lo; 389 uint32_t ci_addr_hi; 390 } __packed; 391 392 /* SAS (?) controller properties, part of mfi_ctrl_info */ 393 struct mfi_ctrl_props { 394 uint16_t seq_num; 395 uint16_t pred_fail_poll_interval; 396 uint16_t intr_throttle_cnt; 397 uint16_t intr_throttle_timeout; 398 uint8_t rebuild_rate; 399 uint8_t patrol_read_rate; 400 uint8_t bgi_rate; 401 uint8_t cc_rate; 402 uint8_t recon_rate; 403 uint8_t cache_flush_interval; 404 uint8_t spinup_drv_cnt; 405 uint8_t spinup_delay; 406 uint8_t cluster_enable; 407 uint8_t coercion_mode; 408 uint8_t alarm_enable; 409 uint8_t disable_auto_rebuild; 410 uint8_t disable_battery_warn; 411 uint8_t ecc_bucket_size; 412 uint16_t ecc_bucket_leak_rate; 413 uint8_t restore_hotspare_on_insertion; 414 uint8_t expose_encl_devices; 415 uint8_t reserved[38]; 416 } __packed; 417 418 /* PCI information about the card. */ 419 struct mfi_info_pci { 420 uint16_t vendor; 421 uint16_t device; 422 uint16_t subvendor; 423 uint16_t subdevice; 424 uint8_t reserved[24]; 425 } __packed; 426 427 /* Host (front end) interface information */ 428 struct mfi_info_host { 429 uint8_t type; 430 #define MFI_INFO_HOST_PCIX 0x01 431 #define MFI_INFO_HOST_PCIE 0x02 432 #define MFI_INFO_HOST_ISCSI 0x04 433 #define MFI_INFO_HOST_SAS3G 0x08 434 uint8_t reserved[6]; 435 uint8_t port_count; 436 uint64_t port_addr[8]; 437 } __packed; 438 439 /* Device (back end) interface information */ 440 struct mfi_info_device { 441 uint8_t type; 442 #define MFI_INFO_DEV_SPI 0x01 443 #define MFI_INFO_DEV_SAS3G 0x02 444 #define MFI_INFO_DEV_SATA1 0x04 445 #define MFI_INFO_DEV_SATA3G 0x08 446 uint8_t reserved[6]; 447 uint8_t port_count; 448 uint64_t port_addr[8]; 449 } __packed; 450 451 /* Firmware component information */ 452 struct mfi_info_component { 453 char name[8]; 454 char version[32]; 455 char build_date[16]; 456 char build_time[16]; 457 } __packed; 458 459 460 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 461 struct mfi_ctrl_info { 462 struct mfi_info_pci pci; 463 struct mfi_info_host host; 464 struct mfi_info_device device; 465 466 /* Firmware components that are present and active. */ 467 uint32_t image_check_word; 468 uint32_t image_component_count; 469 struct mfi_info_component image_component[8]; 470 471 /* Firmware components that have been flashed but are inactive */ 472 uint32_t pending_image_component_count; 473 struct mfi_info_component pending_image_component[8]; 474 475 uint8_t max_arms; 476 uint8_t max_spans; 477 uint8_t max_arrays; 478 uint8_t max_lds; 479 char product_name[80]; 480 char serial_number[32]; 481 uint32_t hw_present; 482 #define MFI_INFO_HW_BBU 0x01 483 #define MFI_INFO_HW_ALARM 0x02 484 #define MFI_INFO_HW_NVRAM 0x04 485 #define MFI_INFO_HW_UART 0x08 486 uint32_t current_fw_time; 487 uint16_t max_cmds; 488 uint16_t max_sg_elements; 489 uint32_t max_request_size; 490 uint16_t lds_present; 491 uint16_t lds_degraded; 492 uint16_t lds_offline; 493 uint16_t pd_present; 494 uint16_t pd_disks_present; 495 uint16_t pd_disks_pred_failure; 496 uint16_t pd_disks_failed; 497 uint16_t nvram_size; 498 uint16_t memory_size; 499 uint16_t flash_size; 500 uint16_t ram_correctable_errors; 501 uint16_t ram_uncorrectable_errors; 502 uint8_t cluster_allowed; 503 uint8_t cluster_active; 504 uint16_t max_strips_per_io; 505 506 uint32_t raid_levels; 507 #define MFI_INFO_RAID_0 0x01 508 #define MFI_INFO_RAID_1 0x02 509 #define MFI_INFO_RAID_5 0x04 510 #define MFI_INFO_RAID_1E 0x08 511 #define MFI_INFO_RAID_6 0x10 512 513 uint32_t adapter_ops; 514 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 515 #define MFI_INFO_AOPS_CC_RATE 0x0002 516 #define MFI_INFO_AOPS_BGI_RATE 0x0004 517 #define MFI_INFO_AOPS_RECON_RATE 0x0008 518 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 519 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 520 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 521 #define MFI_INFO_AOPS_BBU 0x0080 522 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 523 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 524 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 525 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 526 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 527 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 528 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 529 530 uint32_t ld_ops; 531 #define MFI_INFO_LDOPS_READ_POLICY 0x01 532 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 533 #define MFI_INFO_LDOPS_IO_POLICY 0x04 534 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 535 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 536 537 struct { 538 uint8_t min; 539 uint8_t max; 540 uint8_t reserved[2]; 541 } __packed stripe_sz_ops; 542 543 uint32_t pd_ops; 544 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 545 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 546 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 547 548 uint32_t pd_mix_support; 549 #define MFI_INFO_PDMIX_SAS 0x01 550 #define MFI_INFO_PDMIX_SATA 0x02 551 #define MFI_INFO_PDMIX_ENCL 0x04 552 #define MFI_INFO_PDMIX_LD 0x08 553 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 554 555 uint8_t ecc_bucket_count; 556 uint8_t reserved2[11]; 557 struct mfi_ctrl_props properties; 558 char package_version[0x60]; 559 uint8_t pad[0x800 - 0x6a0]; 560 } __packed; 561 562 /* keep track of an event. */ 563 union mfi_evt { 564 struct { 565 uint16_t locale; 566 uint8_t reserved; 567 uint8_t class; 568 } members; 569 uint32_t word; 570 } __packed; 571 572 /* event log state. */ 573 struct mfi_evt_log_state { 574 uint32_t newest_seq_num; 575 uint32_t oldest_seq_num; 576 uint32_t clear_seq_num; 577 uint32_t shutdown_seq_num; 578 uint32_t boot_seq_num; 579 } __packed; 580 581 struct mfi_progress { 582 uint16_t progress; 583 uint16_t elapsed_seconds; 584 } __packed; 585 586 struct mfi_evt_ld { 587 uint16_t target_id; 588 uint8_t ld_index; 589 uint8_t reserved; 590 } __packed; 591 592 struct mfi_evt_pd { 593 uint16_t device_id; 594 uint8_t enclosure_index; 595 uint8_t slot_number; 596 } __packed; 597 598 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 599 struct mfi_evt_detail { 600 uint32_t seq; 601 uint32_t time; 602 uint32_t code; 603 union mfi_evt class; 604 uint8_t arg_type; 605 uint8_t reserved1[15]; 606 607 union { 608 struct { 609 struct mfi_evt_pd pd; 610 uint8_t cdb_len; 611 uint8_t sense_len; 612 uint8_t reserved[2]; 613 uint8_t cdb[16]; 614 uint8_t sense[64]; 615 } cdb_sense; 616 617 struct mfi_evt_ld ld; 618 619 struct { 620 struct mfi_evt_ld ld; 621 uint64_t count; 622 } ld_count; 623 624 struct { 625 uint64_t lba; 626 struct mfi_evt_ld ld; 627 } ld_lba; 628 629 struct { 630 struct mfi_evt_ld ld; 631 uint32_t pre_owner; 632 uint32_t new_owner; 633 } ld_owner; 634 635 struct { 636 uint64_t ld_lba; 637 uint64_t pd_lba; 638 struct mfi_evt_ld ld; 639 struct mfi_evt_pd pd; 640 } ld_lba_pd_lba; 641 642 struct { 643 struct mfi_evt_ld ld; 644 struct mfi_progress prog; 645 } ld_prog; 646 647 struct { 648 struct mfi_evt_ld ld; 649 uint32_t prev_state; 650 uint32_t new_state; 651 } ld_state; 652 653 struct { 654 uint64_t strip; 655 struct mfi_evt_ld ld; 656 } ld_strip; 657 658 struct mfi_evt_pd pd; 659 660 struct { 661 struct mfi_evt_pd pd; 662 uint32_t err; 663 } pd_err; 664 665 struct { 666 uint64_t lba; 667 struct mfi_evt_pd pd; 668 } pd_lba; 669 670 struct { 671 uint64_t lba; 672 struct mfi_evt_pd pd; 673 struct mfi_evt_ld ld; 674 } pd_lba_ld; 675 676 struct { 677 struct mfi_evt_pd pd; 678 struct mfi_progress prog; 679 } pd_prog; 680 681 struct { 682 struct mfi_evt_pd ld; 683 uint32_t prev_state; 684 uint32_t new_state; 685 } pd_state; 686 687 struct { 688 uint16_t venderId; 689 uint16_t deviceId; 690 uint16_t subVenderId; 691 uint16_t subDeviceId; 692 } pci; 693 694 uint32_t rate; 695 696 char str[96]; 697 698 struct { 699 uint32_t rtc; 700 uint16_t elapsedSeconds; 701 } time; 702 703 struct { 704 uint32_t ecar; 705 uint32_t elog; 706 char str[64]; 707 } ecc; 708 709 uint8_t b[96]; 710 uint16_t s[48]; 711 uint32_t w[24]; 712 uint64_t d[12]; 713 } args; 714 715 char description[128]; 716 } __packed; 717 718 /* SAS log detail guessed at */ 719 struct mfi_log_detail { 720 uint32_t something1; 721 uint32_t something2; 722 uint32_t seq; 723 uint32_t something3; 724 uint32_t arg_type; 725 uint8_t reserved1[15]; 726 727 union { 728 uint8_t b[96]; 729 } args; 730 char description[128]; 731 } __packed; 732 733 struct mfi_ldref { 734 uint8_t target_id; 735 uint8_t reserved; 736 uint16_t seq; 737 } __packed; 738 739 struct mfi_ld_list { 740 uint32_t ld_count; 741 uint32_t reserved1; 742 struct { 743 struct mfi_ldref ld; 744 uint8_t state; 745 uint8_t reserved2[3]; 746 uint64_t size; 747 } ld_list[MFI_MAX_LD]; 748 } __packed; 749 750 enum mfi_ld_access { 751 MFI_LD_ACCESS_RW = 0, 752 MFI_LD_ACCSSS_RO = 2, 753 MFI_LD_ACCESS_BLOCKED = 3, 754 }; 755 #define MFI_LD_ACCESS_MASK 3 756 757 enum mfi_ld_state { 758 MFI_LD_STATE_OFFLINE = 0, 759 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 760 MFI_LD_STATE_DEGRADED = 2, 761 MFI_LD_STATE_OPTIMAL = 3 762 }; 763 764 struct mfi_ld_props { 765 struct mfi_ldref ld; 766 char name[16]; 767 uint8_t default_cache_policy; 768 uint8_t access_policy; 769 uint8_t disk_cache_policy; 770 uint8_t current_cache_policy; 771 uint8_t no_bgi; 772 uint8_t reserved[7]; 773 } __packed; 774 775 struct mfi_ld_params { 776 uint8_t primary_raid_level; 777 uint8_t raid_level_qualifier; 778 uint8_t secondary_raid_level; 779 uint8_t stripe_size; 780 uint8_t num_drives; 781 uint8_t span_depth; 782 uint8_t state; 783 uint8_t init_state; 784 uint8_t is_consistent; 785 uint8_t reserved[23]; 786 } __packed; 787 788 struct mfi_ld_progress { 789 uint32_t active; 790 #define MFI_LD_PROGRESS_CC (1<<0) 791 #define MFI_LD_PROGRESS_BGI (1<<1) 792 #define MFI_LD_PROGRESS_FGI (1<<2) 793 #define MFI_LD_PORGRESS_RECON (1<<3) 794 struct mfi_progress cc; 795 struct mfi_progress bgi; 796 struct mfi_progress fgi; 797 struct mfi_progress recon; 798 struct mfi_progress reserved[4]; 799 } __packed; 800 801 struct mfi_span { 802 uint64_t start_block; 803 uint64_t num_blocks; 804 uint16_t array_ref; 805 uint8_t reserved[6]; 806 } __packed; 807 808 #define MFI_MAX_SPAN_DEPTH 8 809 struct mfi_ld_config { 810 struct mfi_ld_props properties; 811 struct mfi_ld_params params; 812 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 813 } __packed; 814 815 struct mfi_ld_info { 816 struct mfi_ld_config ld_config; 817 uint64_t size; 818 struct mfi_ld_progress progress; 819 uint16_t cluster_owner; 820 uint8_t reconstruct_active; 821 uint8_t reserved1[1]; 822 uint8_t vpd_page83[64]; 823 uint8_t reserved2[16]; 824 } __packed; 825 826 #endif /* _MFIREG_H */ 827