1 /*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /*- 27 * Copyright (c) 2007 LSI Corp. 28 * Copyright (c) 2007 Rajesh Prabhakaran. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53 #ifndef _MFIREG_H 54 #define _MFIREG_H 55 56 #include <sys/cdefs.h> 57 __FBSDID("$FreeBSD$"); 58 59 /* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. 66 */ 67 #define MEGAMFI_FRAME_SIZE 64 68 /* 69 * Start with the register set. All registers are 32 bits wide. 70 * The usual Intel IOP style setup. 71 */ 72 #define MFI_IMSG0 0x10 /* Inbound message 0 */ 73 #define MFI_IMSG1 0x14 /* Inbound message 1 */ 74 #define MFI_OMSG0 0x18 /* Outbound message 0 */ 75 #define MFI_OMSG1 0x1c /* Outbound message 1 */ 76 #define MFI_IDB 0x20 /* Inbound doorbell */ 77 #define MFI_ISTS 0x24 /* Inbound interrupt status */ 78 #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 79 #define MFI_ODB 0x2c /* Outbound doorbell */ 80 #define MFI_OSTS 0x30 /* Outbound interrupt status */ 81 #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 82 #define MFI_IQP 0x40 /* Inbound queue port */ 83 #define MFI_OQP 0x44 /* Outbound queue port */ 84 85 /* 86 * ThunderBolt specific Register 87 */ 88 89 #define MFI_RFPI 0x48 /* reply_free_post_host_index */ 90 #define MFI_RPI 0x6c /* reply_post_host_index */ 91 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 92 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 93 94 /* 95 * 1078 specific related register 96 */ 97 #define MFI_ODR0 0x9c /* outbound doorbell register0 */ 98 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 99 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 100 #define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 101 #define MFI_RMI 0x2 /* reply message interrupt */ 102 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 103 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 104 105 /* OCR registers */ 106 #define MFI_WSR 0x004 /* write sequence register */ 107 #define MFI_HDR 0x008 /* host diagnostic register */ 108 #define MFI_RSR 0x3c3 /* Reset Status Register */ 109 110 /* 111 * GEN2 specific changes 112 */ 113 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 114 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 115 116 /* 117 * skinny specific changes 118 */ 119 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 120 #define MFI_IQPL 0x000000c0 121 #define MFI_IQPH 0x000000c4 122 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 123 124 /* Bits for MFI_OSTS */ 125 #define MFI_OSTS_INTR_VALID 0x00000002 126 127 /* OCR specific flags */ 128 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 129 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 130 131 /* 132 * Firmware state values. Found in OMSG0 during initialization. 133 */ 134 #define MFI_FWSTATE_MASK 0xf0000000 135 #define MFI_FWSTATE_UNDEFINED 0x00000000 136 #define MFI_FWSTATE_BB_INIT 0x10000000 137 #define MFI_FWSTATE_FW_INIT 0x40000000 138 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 139 #define MFI_FWSTATE_FW_INIT_2 0x70000000 140 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 141 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 142 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 143 #define MFI_FWSTATE_READY 0xb0000000 144 #define MFI_FWSTATE_OPERATIONAL 0xc0000000 145 #define MFI_FWSTATE_FAULT 0xf0000000 146 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 147 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 148 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 149 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 150 #define MFI_RESET_REQUIRED 0x00000001 151 152 /* ThunderBolt Support */ 153 #define MFI_FWSTATE_TB_MASK 0xf0000000 154 #define MFI_FWSTATE_TB_RESET 0x00000000 155 #define MFI_FWSTATE_TB_READY 0x10000000 156 #define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 157 #define MFI_FWSTATE_TB_FAULT 0x40000000 158 159 /* 160 * Control bits to drive the card to ready state. These go into the IDB 161 * register. 162 */ 163 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 164 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 165 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 166 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 167 #define MFI_FWINIT_HOTPLUG 0x00000010 168 169 /* ADP reset flags */ 170 #define MFI_STOP_ADP 0x00000020 171 #define MFI_ADP_RESET 0x00000040 172 #define DIAG_WRITE_ENABLE 0x00000080 173 #define DIAG_RESET_ADAPTER 0x00000004 174 175 /* MFI Commands */ 176 typedef enum { 177 MFI_CMD_INIT = 0x00, 178 MFI_CMD_LD_READ, 179 MFI_CMD_LD_WRITE, 180 MFI_CMD_LD_SCSI_IO, 181 MFI_CMD_PD_SCSI_IO, 182 MFI_CMD_DCMD, 183 MFI_CMD_ABORT, 184 MFI_CMD_SMP, 185 MFI_CMD_STP 186 } mfi_cmd_t; 187 188 /* Direct commands */ 189 typedef enum { 190 MFI_DCMD_CTRL_GETINFO = 0x01010000, 191 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 192 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 193 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 194 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 195 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 196 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 197 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 198 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 199 MFI_DCMD_PR_GET_STATUS = 0x01070100, 200 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 201 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 202 MFI_DCMD_PR_START = 0x01070400, 203 MFI_DCMD_PR_STOP = 0x01070500, 204 MFI_DCMD_TIME_SECS_GET = 0x01080201, 205 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 206 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 207 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 208 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 209 MFI_DCMD_PD_GET_LIST = 0x02010000, 210 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 211 MFI_DCMD_PD_GET_INFO = 0x02020000, 212 MFI_DCMD_PD_STATE_SET = 0x02030100, 213 MFI_DCMD_PD_REBUILD_START = 0x02040100, 214 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 215 MFI_DCMD_PD_CLEAR_START = 0x02050100, 216 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 217 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 218 MFI_DCMD_PD_LOCATE_START = 0x02070100, 219 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 220 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 221 MFI_DCMD_LD_SYNC = 0x0300e102, 222 MFI_DCMD_LD_GET_LIST = 0x03010000, 223 MFI_DCMD_LD_GET_INFO = 0x03020000, 224 MFI_DCMD_LD_GET_PROP = 0x03030000, 225 MFI_DCMD_LD_SET_PROP = 0x03040000, 226 MFI_DCMD_LD_INIT_START = 0x03060100, 227 MFI_DCMD_LD_DELETE = 0x03090000, 228 MFI_DCMD_CFG_READ = 0x04010000, 229 MFI_DCMD_CFG_ADD = 0x04020000, 230 MFI_DCMD_CFG_CLEAR = 0x04030000, 231 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 232 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 233 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 234 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 235 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 236 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 237 MFI_DCMD_CLUSTER = 0x08000000, 238 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 239 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 240 } mfi_dcmd_t; 241 242 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 243 #define MFI_FLUSHCACHE_CTRL 0x01 244 #define MFI_FLUSHCACHE_DISK 0x02 245 246 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 247 #define MFI_SHUTDOWN_SPINDOWN 0x01 248 249 /* 250 * MFI Frame flags 251 */ 252 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 253 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 254 #define MFI_FRAME_SGL32 0x0000 255 #define MFI_FRAME_SGL64 0x0002 256 #define MFI_FRAME_SENSE32 0x0000 257 #define MFI_FRAME_SENSE64 0x0004 258 #define MFI_FRAME_DIR_NONE 0x0000 259 #define MFI_FRAME_DIR_WRITE 0x0008 260 #define MFI_FRAME_DIR_READ 0x0010 261 #define MFI_FRAME_DIR_BOTH 0x0018 262 #define MFI_FRAME_IEEE_SGL 0x0020 263 #define MFI_FRAME_FMT "\20" \ 264 "\1NOPOST" \ 265 "\2SGL64" \ 266 "\3SENSE64" \ 267 "\4WRITE" \ 268 "\5READ" \ 269 "\6IEEESGL" 270 271 /* ThunderBolt Specific */ 272 273 /* 274 * Pre-TB command size and TB command size. 275 * We will be checking it at the load time for the time being 276 */ 277 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 278 279 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 280 /* 281 * We are defining only 128 byte message to reduce memory move over head 282 * and also it will reduce the SRB extension size by 128byte compared with 283 * 256 message size 284 */ 285 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 286 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 287 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 288 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 289 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 290 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 291 292 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 293 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 294 295 #define MR_INTERNAL_MFI_FRAMES_SMID 1 296 #define MR_CTRL_EVENT_WAIT_SMID 2 297 #define MR_INTERNAL_DRIVER_RESET_SMID 3 298 299 300 /* MFI Status codes */ 301 typedef enum { 302 MFI_STAT_OK = 0x00, 303 MFI_STAT_INVALID_CMD, 304 MFI_STAT_INVALID_DCMD, 305 MFI_STAT_INVALID_PARAMETER, 306 MFI_STAT_INVALID_SEQUENCE_NUMBER, 307 MFI_STAT_ABORT_NOT_POSSIBLE, 308 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 309 MFI_STAT_APP_IN_USE, 310 MFI_STAT_APP_NOT_INITIALIZED, 311 MFI_STAT_ARRAY_INDEX_INVALID, 312 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 313 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 314 MFI_STAT_DEVICE_NOT_FOUND, 315 MFI_STAT_DRIVE_TOO_SMALL, 316 MFI_STAT_FLASH_ALLOC_FAIL, 317 MFI_STAT_FLASH_BUSY, 318 MFI_STAT_FLASH_ERROR = 0x10, 319 MFI_STAT_FLASH_IMAGE_BAD, 320 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 321 MFI_STAT_FLASH_NOT_OPEN, 322 MFI_STAT_FLASH_NOT_STARTED, 323 MFI_STAT_FLUSH_FAILED, 324 MFI_STAT_HOST_CODE_NOT_FOUNT, 325 MFI_STAT_LD_CC_IN_PROGRESS, 326 MFI_STAT_LD_INIT_IN_PROGRESS, 327 MFI_STAT_LD_LBA_OUT_OF_RANGE, 328 MFI_STAT_LD_MAX_CONFIGURED, 329 MFI_STAT_LD_NOT_OPTIMAL, 330 MFI_STAT_LD_RBLD_IN_PROGRESS, 331 MFI_STAT_LD_RECON_IN_PROGRESS, 332 MFI_STAT_LD_WRONG_RAID_LEVEL, 333 MFI_STAT_MAX_SPARES_EXCEEDED, 334 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 335 MFI_STAT_MFC_HW_ERROR, 336 MFI_STAT_NO_HW_PRESENT, 337 MFI_STAT_NOT_FOUND, 338 MFI_STAT_NOT_IN_ENCL, 339 MFI_STAT_PD_CLEAR_IN_PROGRESS, 340 MFI_STAT_PD_TYPE_WRONG, 341 MFI_STAT_PR_DISABLED, 342 MFI_STAT_ROW_INDEX_INVALID, 343 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 344 MFI_STAT_SAS_CONFIG_INVALID_DATA, 345 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 346 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 347 MFI_STAT_SCSI_DONE_WITH_ERROR, 348 MFI_STAT_SCSI_IO_FAILED, 349 MFI_STAT_SCSI_RESERVATION_CONFLICT, 350 MFI_STAT_SHUTDOWN_FAILED = 0x30, 351 MFI_STAT_TIME_NOT_SET, 352 MFI_STAT_WRONG_STATE, 353 MFI_STAT_LD_OFFLINE, 354 MFI_STAT_PEER_NOTIFICATION_REJECTED, 355 MFI_STAT_PEER_NOTIFICATION_FAILED, 356 MFI_STAT_RESERVATION_IN_PROGRESS, 357 MFI_STAT_I2C_ERRORS_DETECTED, 358 MFI_STAT_PCI_ERRORS_DETECTED, 359 MFI_STAT_DIAG_FAILED, 360 MFI_STAT_BOOT_MSG_PENDING, 361 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 362 MFI_STAT_INVALID_STATUS = 0xFF 363 } mfi_status_t; 364 365 typedef enum { 366 MFI_EVT_CLASS_DEBUG = -2, 367 MFI_EVT_CLASS_PROGRESS = -1, 368 MFI_EVT_CLASS_INFO = 0, 369 MFI_EVT_CLASS_WARNING = 1, 370 MFI_EVT_CLASS_CRITICAL = 2, 371 MFI_EVT_CLASS_FATAL = 3, 372 MFI_EVT_CLASS_DEAD = 4 373 } mfi_evt_class_t; 374 375 typedef enum { 376 MFI_EVT_LOCALE_LD = 0x0001, 377 MFI_EVT_LOCALE_PD = 0x0002, 378 MFI_EVT_LOCALE_ENCL = 0x0004, 379 MFI_EVT_LOCALE_BBU = 0x0008, 380 MFI_EVT_LOCALE_SAS = 0x0010, 381 MFI_EVT_LOCALE_CTRL = 0x0020, 382 MFI_EVT_LOCALE_CONFIG = 0x0040, 383 MFI_EVT_LOCALE_CLUSTER = 0x0080, 384 MFI_EVT_LOCALE_ALL = 0xffff 385 } mfi_evt_locale_t; 386 387 typedef enum { 388 MR_EVT_ARGS_NONE = 0x00, 389 MR_EVT_ARGS_CDB_SENSE, 390 MR_EVT_ARGS_LD, 391 MR_EVT_ARGS_LD_COUNT, 392 MR_EVT_ARGS_LD_LBA, 393 MR_EVT_ARGS_LD_OWNER, 394 MR_EVT_ARGS_LD_LBA_PD_LBA, 395 MR_EVT_ARGS_LD_PROG, 396 MR_EVT_ARGS_LD_STATE, 397 MR_EVT_ARGS_LD_STRIP, 398 MR_EVT_ARGS_PD, 399 MR_EVT_ARGS_PD_ERR, 400 MR_EVT_ARGS_PD_LBA, 401 MR_EVT_ARGS_PD_LBA_LD, 402 MR_EVT_ARGS_PD_PROG, 403 MR_EVT_ARGS_PD_STATE, 404 MR_EVT_ARGS_PCI, 405 MR_EVT_ARGS_RATE, 406 MR_EVT_ARGS_STR, 407 MR_EVT_ARGS_TIME, 408 MR_EVT_ARGS_ECC 409 } mfi_evt_args; 410 411 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 412 #define MR_EVT_PD_REMOVED 0x0070 413 #define MR_EVT_PD_INSERTED 0x005b 414 #define MR_EVT_LD_CHANGE 0x0051 415 416 typedef enum { 417 MR_LD_CACHE_WRITE_BACK = 0x01, 418 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 419 MR_LD_CACHE_READ_AHEAD = 0x04, 420 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 421 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 422 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 423 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 424 } mfi_ld_cache; 425 #define MR_LD_CACHE_MASK 0x7f 426 427 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 428 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 429 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 430 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 431 #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 432 #define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 433 #define MR_LD_CACHE_POLICY_IO_CACHED \ 434 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 435 #define MR_LD_CACHE_POLICY_IO_DIRECT 0 436 437 typedef enum { 438 MR_PD_CACHE_UNCHANGED = 0, 439 MR_PD_CACHE_ENABLE = 1, 440 MR_PD_CACHE_DISABLE = 2 441 } mfi_pd_cache; 442 443 typedef enum { 444 MR_PD_QUERY_TYPE_ALL = 0, 445 MR_PD_QUERY_TYPE_STATE = 1, 446 MR_PD_QUERY_TYPE_POWER_STATE = 2, 447 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 448 MR_PD_QUERY_TYPE_SPEED = 4, 449 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 450 } mfi_pd_query_type; 451 452 /* 453 * Other propertities and definitions 454 */ 455 #define MFI_MAX_PD_CHANNELS 2 456 #define MFI_MAX_LD_CHANNELS 2 457 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 458 #define MFI_MAX_CHANNEL_DEVS 128 459 #define MFI_DEFAULT_ID -1 460 #define MFI_MAX_LUN 8 461 #define MFI_MAX_LD 64 462 #define MFI_MAX_PD 256 463 464 #define MFI_FRAME_SIZE 64 465 #define MFI_MBOX_SIZE 12 466 467 /* Firmware flashing can take 50+ seconds */ 468 #define MFI_POLL_TIMEOUT_SECS 60 469 470 /* Allow for speedier math calculations */ 471 #define MFI_SECTOR_LEN 512 472 473 /* Scatter Gather elements */ 474 struct mfi_sg32 { 475 uint32_t addr; 476 uint32_t len; 477 } __packed; 478 479 struct mfi_sg64 { 480 uint64_t addr; 481 uint32_t len; 482 } __packed; 483 484 struct mfi_sg_skinny { 485 uint64_t addr; 486 uint32_t len; 487 uint32_t flag; 488 } __packed; 489 490 union mfi_sgl { 491 struct mfi_sg32 sg32[1]; 492 struct mfi_sg64 sg64[1]; 493 struct mfi_sg_skinny sg_skinny[1]; 494 } __packed; 495 496 /* Message frames. All messages have a common header */ 497 struct mfi_frame_header { 498 uint8_t cmd; 499 uint8_t sense_len; 500 uint8_t cmd_status; 501 uint8_t scsi_status; 502 uint8_t target_id; 503 uint8_t lun_id; 504 uint8_t cdb_len; 505 uint8_t sg_count; 506 uint32_t context; 507 /* 508 * pad0 is MSI Specific. Not used by Driver. Zero the value before 509 * sending the command to f/w. 510 */ 511 uint32_t pad0; 512 uint16_t flags; 513 #define MFI_FRAME_DATAOUT 0x08 514 #define MFI_FRAME_DATAIN 0x10 515 uint16_t timeout; 516 uint32_t data_len; 517 } __packed; 518 519 struct mfi_init_frame { 520 struct mfi_frame_header header; 521 uint32_t qinfo_new_addr_lo; 522 uint32_t qinfo_new_addr_hi; 523 uint32_t qinfo_old_addr_lo; 524 uint32_t qinfo_old_addr_hi; 525 // Start LSIP200113393 526 uint32_t driver_ver_lo; /*28h */ 527 uint32_t driver_ver_hi; /*2Ch */ 528 529 uint32_t reserved[4]; 530 // End LSIP200113393 531 } __packed; 532 533 /* 534 * Define MFI Address Context union. 535 */ 536 #ifdef MFI_ADDRESS_IS_uint64_t 537 typedef uint64_t MFI_ADDRESS; 538 #else 539 typedef union _MFI_ADDRESS { 540 struct { 541 uint32_t addressLow; 542 uint32_t addressHigh; 543 } u; 544 uint64_t address; 545 } MFI_ADDRESS, *PMFI_ADDRESS; 546 #endif 547 548 #define MFI_IO_FRAME_SIZE 40 549 struct mfi_io_frame { 550 struct mfi_frame_header header; 551 uint32_t sense_addr_lo; 552 uint32_t sense_addr_hi; 553 uint32_t lba_lo; 554 uint32_t lba_hi; 555 union mfi_sgl sgl; 556 } __packed; 557 558 #define MFI_PASS_FRAME_SIZE 48 559 struct mfi_pass_frame { 560 struct mfi_frame_header header; 561 uint32_t sense_addr_lo; 562 uint32_t sense_addr_hi; 563 uint8_t cdb[16]; 564 union mfi_sgl sgl; 565 } __packed; 566 567 #define MFI_DCMD_FRAME_SIZE 40 568 struct mfi_dcmd_frame { 569 struct mfi_frame_header header; 570 uint32_t opcode; 571 uint8_t mbox[MFI_MBOX_SIZE]; 572 union mfi_sgl sgl; 573 } __packed; 574 575 struct mfi_abort_frame { 576 struct mfi_frame_header header; 577 uint32_t abort_context; 578 /* pad is changed to reserved.*/ 579 uint32_t reserved0; 580 uint32_t abort_mfi_addr_lo; 581 uint32_t abort_mfi_addr_hi; 582 uint32_t reserved1[6]; 583 } __packed; 584 585 struct mfi_smp_frame { 586 struct mfi_frame_header header; 587 uint64_t sas_addr; 588 union { 589 struct mfi_sg32 sg32[2]; 590 struct mfi_sg64 sg64[2]; 591 } sgl; 592 } __packed; 593 594 struct mfi_stp_frame { 595 struct mfi_frame_header header; 596 uint16_t fis[10]; 597 uint32_t stp_flags; 598 union { 599 struct mfi_sg32 sg32[2]; 600 struct mfi_sg64 sg64[2]; 601 } sgl; 602 } __packed; 603 604 union mfi_frame { 605 struct mfi_frame_header header; 606 struct mfi_init_frame init; 607 /* ThunderBolt Initialization */ 608 struct mfi_io_frame io; 609 struct mfi_pass_frame pass; 610 struct mfi_dcmd_frame dcmd; 611 struct mfi_abort_frame abort; 612 struct mfi_smp_frame smp; 613 struct mfi_stp_frame stp; 614 uint8_t bytes[MFI_FRAME_SIZE]; 615 }; 616 617 #define MFI_SENSE_LEN 128 618 struct mfi_sense { 619 uint8_t data[MFI_SENSE_LEN]; 620 }; 621 622 /* The queue init structure that is passed with the init message */ 623 struct mfi_init_qinfo { 624 uint32_t flags; 625 uint32_t rq_entries; 626 uint32_t rq_addr_lo; 627 uint32_t rq_addr_hi; 628 uint32_t pi_addr_lo; 629 uint32_t pi_addr_hi; 630 uint32_t ci_addr_lo; 631 uint32_t ci_addr_hi; 632 } __packed; 633 634 /* SAS (?) controller properties, part of mfi_ctrl_info */ 635 struct mfi_ctrl_props { 636 uint16_t seq_num; 637 uint16_t pred_fail_poll_interval; 638 uint16_t intr_throttle_cnt; 639 uint16_t intr_throttle_timeout; 640 uint8_t rebuild_rate; 641 uint8_t patrol_read_rate; 642 uint8_t bgi_rate; 643 uint8_t cc_rate; 644 uint8_t recon_rate; 645 uint8_t cache_flush_interval; 646 uint8_t spinup_drv_cnt; 647 uint8_t spinup_delay; 648 uint8_t cluster_enable; 649 uint8_t coercion_mode; 650 uint8_t alarm_enable; 651 uint8_t disable_auto_rebuild; 652 uint8_t disable_battery_warn; 653 uint8_t ecc_bucket_size; 654 uint16_t ecc_bucket_leak_rate; 655 uint8_t restore_hotspare_on_insertion; 656 uint8_t expose_encl_devices; 657 uint8_t maintainPdFailHistory; 658 uint8_t disallowHostRequestReordering; 659 /* set TRUE to abort CC on detecting an inconsistency */ 660 uint8_t abortCCOnError; 661 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 662 uint8_t loadBalanceMode; 663 /* 664 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 665 * h/w mechansim like GPIO pins 666 * 1 - disable auto detect SGPIO, 667 * 2 - disable i2c SEP auto detect 668 * 3 - disable both auto detect 669 */ 670 uint8_t disableAutoDetectBackplane; 671 /* 672 * % of source LD to be reserved for a VDs snapshot in snapshot 673 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 674 */ 675 uint8_t snapVDSpace; 676 677 /* 678 * Add properties that can be controlled by a bit in the following 679 * structure. 680 */ 681 struct { 682 /* set TRUE to disable copyBack (0=copback enabled) */ 683 uint32_t copyBackDisabled :1; 684 uint32_t SMARTerEnabled :1; 685 uint32_t prCorrectUnconfiguredAreas :1; 686 uint32_t useFdeOnly :1; 687 uint32_t disableNCQ :1; 688 uint32_t SSDSMARTerEnabled :1; 689 uint32_t SSDPatrolReadEnabled :1; 690 uint32_t enableSpinDownUnconfigured :1; 691 uint32_t autoEnhancedImport :1; 692 uint32_t enableSecretKeyControl :1; 693 uint32_t disableOnlineCtrlReset :1; 694 uint32_t allowBootWithPinnedCache :1; 695 uint32_t disableSpinDownHS :1; 696 uint32_t enableJBOD :1; 697 uint32_t reserved :18; 698 } OnOffProperties; 699 /* 700 * % of source LD to be reserved for auto snapshot in snapshot 701 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 702 */ 703 uint8_t autoSnapVDSpace; 704 /* 705 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 706 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 707 */ 708 uint8_t viewSpace; 709 /* # of idle minutes before device is spun down (0=use FW defaults) */ 710 uint16_t spinDownTime; 711 uint8_t reserved[24]; 712 } __packed; 713 714 /* PCI information about the card. */ 715 struct mfi_info_pci { 716 uint16_t vendor; 717 uint16_t device; 718 uint16_t subvendor; 719 uint16_t subdevice; 720 uint8_t reserved[24]; 721 } __packed; 722 723 /* Host (front end) interface information */ 724 struct mfi_info_host { 725 uint8_t type; 726 #define MFI_INFO_HOST_PCIX 0x01 727 #define MFI_INFO_HOST_PCIE 0x02 728 #define MFI_INFO_HOST_ISCSI 0x04 729 #define MFI_INFO_HOST_SAS3G 0x08 730 uint8_t reserved[6]; 731 uint8_t port_count; 732 uint64_t port_addr[8]; 733 } __packed; 734 735 /* Device (back end) interface information */ 736 struct mfi_info_device { 737 uint8_t type; 738 #define MFI_INFO_DEV_SPI 0x01 739 #define MFI_INFO_DEV_SAS3G 0x02 740 #define MFI_INFO_DEV_SATA1 0x04 741 #define MFI_INFO_DEV_SATA3G 0x08 742 uint8_t reserved[6]; 743 uint8_t port_count; 744 uint64_t port_addr[8]; 745 } __packed; 746 747 /* Firmware component information */ 748 struct mfi_info_component { 749 char name[8]; 750 char version[32]; 751 char build_date[16]; 752 char build_time[16]; 753 } __packed; 754 755 /* Controller default settings */ 756 struct mfi_defaults { 757 uint64_t sas_addr; 758 uint8_t phy_polarity; 759 uint8_t background_rate; 760 uint8_t stripe_size; 761 uint8_t flush_time; 762 uint8_t write_back; 763 uint8_t read_ahead; 764 uint8_t cache_when_bbu_bad; 765 uint8_t cached_io; 766 uint8_t smart_mode; 767 uint8_t alarm_disable; 768 uint8_t coercion; 769 uint8_t zrc_config; 770 uint8_t dirty_led_shows_drive_activity; 771 uint8_t bios_continue_on_error; 772 uint8_t spindown_mode; 773 uint8_t allowed_device_types; 774 uint8_t allow_mix_in_enclosure; 775 uint8_t allow_mix_in_ld; 776 uint8_t allow_sata_in_cluster; 777 uint8_t max_chained_enclosures; 778 uint8_t disable_ctrl_r; 779 uint8_t enabel_web_bios; 780 uint8_t phy_polarity_split; 781 uint8_t direct_pd_mapping; 782 uint8_t bios_enumerate_lds; 783 uint8_t restored_hot_spare_on_insertion; 784 uint8_t expose_enclosure_devices; 785 uint8_t maintain_pd_fail_history; 786 uint8_t resv[28]; 787 } __packed; 788 789 /* Controller default settings */ 790 struct mfi_bios_data { 791 uint16_t boot_target_id; 792 uint8_t do_not_int_13; 793 uint8_t continue_on_error; 794 uint8_t verbose; 795 uint8_t geometry; 796 uint8_t expose_all_drives; 797 uint8_t reserved[56]; 798 uint8_t check_sum; 799 } __packed; 800 801 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 802 struct mfi_ctrl_info { 803 struct mfi_info_pci pci; 804 struct mfi_info_host host; 805 struct mfi_info_device device; 806 807 /* Firmware components that are present and active. */ 808 uint32_t image_check_word; 809 uint32_t image_component_count; 810 struct mfi_info_component image_component[8]; 811 812 /* Firmware components that have been flashed but are inactive */ 813 uint32_t pending_image_component_count; 814 struct mfi_info_component pending_image_component[8]; 815 816 uint8_t max_arms; 817 uint8_t max_spans; 818 uint8_t max_arrays; 819 uint8_t max_lds; 820 char product_name[80]; 821 char serial_number[32]; 822 uint32_t hw_present; 823 #define MFI_INFO_HW_BBU 0x01 824 #define MFI_INFO_HW_ALARM 0x02 825 #define MFI_INFO_HW_NVRAM 0x04 826 #define MFI_INFO_HW_UART 0x08 827 uint32_t current_fw_time; 828 uint16_t max_cmds; 829 uint16_t max_sg_elements; 830 uint32_t max_request_size; 831 uint16_t lds_present; 832 uint16_t lds_degraded; 833 uint16_t lds_offline; 834 uint16_t pd_present; 835 uint16_t pd_disks_present; 836 uint16_t pd_disks_pred_failure; 837 uint16_t pd_disks_failed; 838 uint16_t nvram_size; 839 uint16_t memory_size; 840 uint16_t flash_size; 841 uint16_t ram_correctable_errors; 842 uint16_t ram_uncorrectable_errors; 843 uint8_t cluster_allowed; 844 uint8_t cluster_active; 845 uint16_t max_strips_per_io; 846 847 uint32_t raid_levels; 848 #define MFI_INFO_RAID_0 0x01 849 #define MFI_INFO_RAID_1 0x02 850 #define MFI_INFO_RAID_5 0x04 851 #define MFI_INFO_RAID_1E 0x08 852 #define MFI_INFO_RAID_6 0x10 853 854 uint32_t adapter_ops; 855 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 856 #define MFI_INFO_AOPS_CC_RATE 0x0002 857 #define MFI_INFO_AOPS_BGI_RATE 0x0004 858 #define MFI_INFO_AOPS_RECON_RATE 0x0008 859 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 860 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 861 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 862 #define MFI_INFO_AOPS_BBU 0x0080 863 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 864 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 865 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 866 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 867 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 868 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 869 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 870 871 uint32_t ld_ops; 872 #define MFI_INFO_LDOPS_READ_POLICY 0x01 873 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 874 #define MFI_INFO_LDOPS_IO_POLICY 0x04 875 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 876 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 877 878 struct { 879 uint8_t min; 880 uint8_t max; 881 uint8_t reserved[2]; 882 } __packed stripe_sz_ops; 883 884 uint32_t pd_ops; 885 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 886 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 887 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 888 889 uint32_t pd_mix_support; 890 #define MFI_INFO_PDMIX_SAS 0x01 891 #define MFI_INFO_PDMIX_SATA 0x02 892 #define MFI_INFO_PDMIX_ENCL 0x04 893 #define MFI_INFO_PDMIX_LD 0x08 894 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 895 896 uint8_t ecc_bucket_count; 897 uint8_t reserved2[11]; 898 struct mfi_ctrl_props properties; 899 char package_version[0x60]; 900 uint8_t pad[0x800 - 0x6a0]; 901 } __packed; 902 903 /* keep track of an event. */ 904 union mfi_evt { 905 struct { 906 uint16_t locale; 907 uint8_t reserved; 908 int8_t evt_class; 909 } members; 910 uint32_t word; 911 } __packed; 912 913 /* event log state. */ 914 struct mfi_evt_log_state { 915 uint32_t newest_seq_num; 916 uint32_t oldest_seq_num; 917 uint32_t clear_seq_num; 918 uint32_t shutdown_seq_num; 919 uint32_t boot_seq_num; 920 } __packed; 921 922 struct mfi_progress { 923 uint16_t progress; 924 uint16_t elapsed_seconds; 925 } __packed; 926 927 struct mfi_evt_ld { 928 uint16_t target_id; 929 uint8_t ld_index; 930 uint8_t reserved; 931 } __packed; 932 933 struct mfi_evt_pd { 934 uint16_t device_id; 935 uint8_t enclosure_index; 936 uint8_t slot_number; 937 } __packed; 938 939 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 940 struct mfi_evt_detail { 941 uint32_t seq; 942 uint32_t time; 943 uint32_t code; 944 union mfi_evt evt_class; 945 uint8_t arg_type; 946 uint8_t reserved1[15]; 947 948 union { 949 struct { 950 struct mfi_evt_pd pd; 951 uint8_t cdb_len; 952 uint8_t sense_len; 953 uint8_t reserved[2]; 954 uint8_t cdb[16]; 955 uint8_t sense[64]; 956 } cdb_sense; 957 958 struct mfi_evt_ld ld; 959 960 struct { 961 struct mfi_evt_ld ld; 962 uint64_t count; 963 } ld_count; 964 965 struct { 966 uint64_t lba; 967 struct mfi_evt_ld ld; 968 } ld_lba; 969 970 struct { 971 struct mfi_evt_ld ld; 972 uint32_t pre_owner; 973 uint32_t new_owner; 974 } ld_owner; 975 976 struct { 977 uint64_t ld_lba; 978 uint64_t pd_lba; 979 struct mfi_evt_ld ld; 980 struct mfi_evt_pd pd; 981 } ld_lba_pd_lba; 982 983 struct { 984 struct mfi_evt_ld ld; 985 struct mfi_progress prog; 986 } ld_prog; 987 988 struct { 989 struct mfi_evt_ld ld; 990 uint32_t prev_state; 991 uint32_t new_state; 992 } ld_state; 993 994 struct { 995 uint64_t strip; 996 struct mfi_evt_ld ld; 997 } ld_strip; 998 999 struct mfi_evt_pd pd; 1000 1001 struct { 1002 struct mfi_evt_pd pd; 1003 uint32_t err; 1004 } pd_err; 1005 1006 struct { 1007 uint64_t lba; 1008 struct mfi_evt_pd pd; 1009 } pd_lba; 1010 1011 struct { 1012 uint64_t lba; 1013 struct mfi_evt_pd pd; 1014 struct mfi_evt_ld ld; 1015 } pd_lba_ld; 1016 1017 struct { 1018 struct mfi_evt_pd pd; 1019 struct mfi_progress prog; 1020 } pd_prog; 1021 1022 struct { 1023 struct mfi_evt_pd ld; 1024 uint32_t prev_state; 1025 uint32_t new_state; 1026 } pd_state; 1027 1028 struct { 1029 uint16_t venderId; 1030 uint16_t deviceId; 1031 uint16_t subVenderId; 1032 uint16_t subDeviceId; 1033 } pci; 1034 1035 uint32_t rate; 1036 1037 char str[96]; 1038 1039 struct { 1040 uint32_t rtc; 1041 uint16_t elapsedSeconds; 1042 } time; 1043 1044 struct { 1045 uint32_t ecar; 1046 uint32_t elog; 1047 char str[64]; 1048 } ecc; 1049 1050 uint8_t b[96]; 1051 uint16_t s[48]; 1052 uint32_t w[24]; 1053 uint64_t d[12]; 1054 } args; 1055 1056 char description[128]; 1057 } __packed; 1058 1059 struct mfi_evt_list { 1060 uint32_t count; 1061 uint32_t reserved; 1062 struct mfi_evt_detail event[1]; 1063 } __packed; 1064 1065 union mfi_pd_ref { 1066 struct { 1067 uint16_t device_id; 1068 uint16_t seq_num; 1069 } v; 1070 uint32_t ref; 1071 } __packed; 1072 1073 union mfi_pd_ddf_type { 1074 struct { 1075 union { 1076 struct { 1077 uint16_t forced_pd_guid : 1; 1078 uint16_t in_vd : 1; 1079 uint16_t is_global_spare : 1; 1080 uint16_t is_spare : 1; 1081 uint16_t is_foreign : 1; 1082 uint16_t reserved : 7; 1083 uint16_t intf : 4; 1084 } pd_type; 1085 uint16_t type; 1086 } v; 1087 uint16_t reserved; 1088 } ddf; 1089 struct { 1090 uint32_t reserved; 1091 } non_disk; 1092 uint32_t type; 1093 } __packed; 1094 1095 struct mfi_pd_progress { 1096 uint32_t active; 1097 #define MFI_PD_PROGRESS_REBUILD (1<<0) 1098 #define MFI_PD_PROGRESS_PATROL (1<<1) 1099 #define MFI_PD_PROGRESS_CLEAR (1<<2) 1100 struct mfi_progress rbld; 1101 struct mfi_progress patrol; 1102 struct mfi_progress clear; 1103 struct mfi_progress reserved[4]; 1104 } __packed; 1105 1106 struct mfi_pd_info { 1107 union mfi_pd_ref ref; 1108 uint8_t inquiry_data[96]; 1109 uint8_t vpd_page83[64]; 1110 uint8_t not_supported; 1111 uint8_t scsi_dev_type; 1112 uint8_t connected_port_bitmap; 1113 uint8_t device_speed; 1114 uint32_t media_err_count; 1115 uint32_t other_err_count; 1116 uint32_t pred_fail_count; 1117 uint32_t last_pred_fail_event_seq_num; 1118 uint16_t fw_state; /* MFI_PD_STATE_* */ 1119 uint8_t disabled_for_removal; 1120 uint8_t link_speed; 1121 union mfi_pd_ddf_type state; 1122 struct { 1123 uint8_t count; 1124 uint8_t is_path_broken; 1125 uint8_t reserved[6]; 1126 uint64_t sas_addr[4]; 1127 } path_info; 1128 uint64_t raw_size; 1129 uint64_t non_coerced_size; 1130 uint64_t coerced_size; 1131 uint16_t encl_device_id; 1132 uint8_t encl_index; 1133 uint8_t slot_number; 1134 struct mfi_pd_progress prog_info; 1135 uint8_t bad_block_table_full; 1136 uint8_t unusable_in_current_config; 1137 uint8_t vpd_page83_ext[64]; 1138 uint8_t reserved[512-358]; 1139 } __packed; 1140 1141 struct mfi_pd_address { 1142 uint16_t device_id; 1143 uint16_t encl_device_id; 1144 uint8_t encl_index; 1145 uint8_t slot_number; 1146 uint8_t scsi_dev_type; /* 0 = disk */ 1147 uint8_t connect_port_bitmap; 1148 uint64_t sas_addr[2]; 1149 } __packed; 1150 1151 #define MAX_SYS_PDS 240 1152 struct mfi_pd_list { 1153 uint32_t size; 1154 uint32_t count; 1155 struct mfi_pd_address addr[MAX_SYS_PDS]; 1156 } __packed; 1157 1158 enum mfi_pd_state { 1159 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1160 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1161 MFI_PD_STATE_HOT_SPARE = 0x02, 1162 MFI_PD_STATE_OFFLINE = 0x10, 1163 MFI_PD_STATE_FAILED = 0x11, 1164 MFI_PD_STATE_REBUILD = 0x14, 1165 MFI_PD_STATE_ONLINE = 0x18, 1166 MFI_PD_STATE_COPYBACK = 0x20, 1167 MFI_PD_STATE_SYSTEM = 0x40 1168 }; 1169 1170 /* 1171 * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1172 * Adding a #define to denote this. 1173 */ 1174 #define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1175 1176 union mfi_ld_ref { 1177 struct { 1178 uint8_t target_id; 1179 uint8_t reserved; 1180 uint16_t seq; 1181 } v; 1182 uint32_t ref; 1183 } __packed; 1184 1185 struct mfi_ld_list { 1186 uint32_t ld_count; 1187 uint32_t reserved1; 1188 struct { 1189 union mfi_ld_ref ld; 1190 uint8_t state; 1191 uint8_t reserved2[3]; 1192 uint64_t size; 1193 } ld_list[MFI_MAX_LD]; 1194 } __packed; 1195 1196 enum mfi_ld_access { 1197 MFI_LD_ACCESS_RW = 0, 1198 MFI_LD_ACCSSS_RO = 2, 1199 MFI_LD_ACCESS_BLOCKED = 3, 1200 }; 1201 #define MFI_LD_ACCESS_MASK 3 1202 1203 enum mfi_ld_state { 1204 MFI_LD_STATE_OFFLINE = 0, 1205 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1206 MFI_LD_STATE_DEGRADED = 2, 1207 MFI_LD_STATE_OPTIMAL = 3 1208 }; 1209 1210 struct mfi_ld_props { 1211 union mfi_ld_ref ld; 1212 char name[16]; 1213 uint8_t default_cache_policy; 1214 uint8_t access_policy; 1215 uint8_t disk_cache_policy; 1216 uint8_t current_cache_policy; 1217 uint8_t no_bgi; 1218 uint8_t reserved[7]; 1219 } __packed; 1220 1221 struct mfi_ld_params { 1222 uint8_t primary_raid_level; 1223 uint8_t raid_level_qualifier; 1224 uint8_t secondary_raid_level; 1225 uint8_t stripe_size; 1226 uint8_t num_drives; 1227 uint8_t span_depth; 1228 uint8_t state; 1229 uint8_t init_state; 1230 #define MFI_LD_PARAMS_INIT_NO 0 1231 #define MFI_LD_PARAMS_INIT_QUICK 1 1232 #define MFI_LD_PARAMS_INIT_FULL 2 1233 uint8_t is_consistent; 1234 uint8_t reserved1[6]; 1235 uint8_t isSSCD; 1236 uint8_t reserved2[16]; 1237 } __packed; 1238 1239 struct mfi_ld_progress { 1240 uint32_t active; 1241 #define MFI_LD_PROGRESS_CC (1<<0) 1242 #define MFI_LD_PROGRESS_BGI (1<<1) 1243 #define MFI_LD_PROGRESS_FGI (1<<2) 1244 #define MFI_LD_PROGRESS_RECON (1<<3) 1245 struct mfi_progress cc; 1246 struct mfi_progress bgi; 1247 struct mfi_progress fgi; 1248 struct mfi_progress recon; 1249 struct mfi_progress reserved[4]; 1250 } __packed; 1251 1252 struct mfi_span { 1253 uint64_t start_block; 1254 uint64_t num_blocks; 1255 uint16_t array_ref; 1256 uint8_t reserved[6]; 1257 } __packed; 1258 1259 #define MFI_MAX_SPAN_DEPTH 8 1260 struct mfi_ld_config { 1261 struct mfi_ld_props properties; 1262 struct mfi_ld_params params; 1263 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1264 } __packed; 1265 1266 struct mfi_ld_info { 1267 struct mfi_ld_config ld_config; 1268 uint64_t size; 1269 struct mfi_ld_progress progress; 1270 uint16_t cluster_owner; 1271 uint8_t reconstruct_active; 1272 uint8_t reserved1[1]; 1273 uint8_t vpd_page83[64]; 1274 uint8_t reserved2[16]; 1275 } __packed; 1276 1277 #define MFI_MAX_ARRAYS 16 1278 struct mfi_spare { 1279 union mfi_pd_ref ref; 1280 uint8_t spare_type; 1281 #define MFI_SPARE_DEDICATED (1 << 0) 1282 #define MFI_SPARE_REVERTIBLE (1 << 1) 1283 #define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1284 uint8_t reserved[2]; 1285 uint8_t array_count; 1286 uint16_t array_ref[MFI_MAX_ARRAYS]; 1287 } __packed; 1288 1289 #define MFI_MAX_ROW_SIZE 32 1290 struct mfi_array { 1291 uint64_t size; 1292 uint8_t num_drives; 1293 uint8_t reserved; 1294 uint16_t array_ref; 1295 uint8_t pad[20]; 1296 struct { 1297 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1298 uint16_t fw_state; /* MFI_PD_STATE_* */ 1299 struct { 1300 uint8_t pd; 1301 uint8_t slot; 1302 } encl; 1303 } pd[MFI_MAX_ROW_SIZE]; 1304 } __packed; 1305 1306 struct mfi_config_data { 1307 uint32_t size; 1308 uint16_t array_count; 1309 uint16_t array_size; 1310 uint16_t log_drv_count; 1311 uint16_t log_drv_size; 1312 uint16_t spares_count; 1313 uint16_t spares_size; 1314 uint8_t reserved[16]; 1315 struct mfi_array array[0]; 1316 struct mfi_ld_config ld[0]; 1317 struct mfi_spare spare[0]; 1318 } __packed; 1319 1320 struct mfi_bbu_capacity_info { 1321 uint16_t relative_charge; 1322 uint16_t absolute_charge; 1323 uint16_t remaining_capacity; 1324 uint16_t full_charge_capacity; 1325 uint16_t run_time_to_empty; 1326 uint16_t average_time_to_empty; 1327 uint16_t average_time_to_full; 1328 uint16_t cycle_count; 1329 uint16_t max_error; 1330 uint16_t remaining_capacity_alarm; 1331 uint16_t remaining_time_alarm; 1332 uint8_t reserved[26]; 1333 } __packed; 1334 1335 struct mfi_bbu_design_info { 1336 uint32_t mfg_date; 1337 uint16_t design_capacity; 1338 uint16_t design_voltage; 1339 uint16_t spec_info; 1340 uint16_t serial_number; 1341 uint16_t pack_stat_config; 1342 uint8_t mfg_name[12]; 1343 uint8_t device_name[8]; 1344 uint8_t device_chemistry[8]; 1345 uint8_t mfg_data[8]; 1346 uint8_t reserved[17]; 1347 } __packed; 1348 1349 struct mfi_ibbu_state { 1350 uint16_t gas_guage_status; 1351 uint16_t relative_charge; 1352 uint16_t charger_system_state; 1353 uint16_t charger_system_ctrl; 1354 uint16_t charging_current; 1355 uint16_t absolute_charge; 1356 uint16_t max_error; 1357 uint8_t reserved[18]; 1358 } __packed; 1359 1360 struct mfi_bbu_state { 1361 uint16_t gas_guage_status; 1362 uint16_t relative_charge; 1363 uint16_t charger_status; 1364 uint16_t remaining_capacity; 1365 uint16_t full_charge_capacity; 1366 uint8_t is_SOH_good; 1367 uint8_t reserved[21]; 1368 } __packed; 1369 1370 union mfi_bbu_status_detail { 1371 struct mfi_ibbu_state ibbu; 1372 struct mfi_bbu_state bbu; 1373 }; 1374 1375 struct mfi_bbu_status { 1376 uint8_t battery_type; 1377 #define MFI_BBU_TYPE_NONE 0 1378 #define MFI_BBU_TYPE_IBBU 1 1379 #define MFI_BBU_TYPE_BBU 2 1380 uint8_t reserved; 1381 uint16_t voltage; 1382 int16_t current; 1383 uint16_t temperature; 1384 uint32_t fw_status; 1385 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1386 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1387 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1388 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1389 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1390 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1391 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1392 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1393 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1394 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1395 uint8_t pad[20]; 1396 union mfi_bbu_status_detail detail; 1397 } __packed; 1398 1399 enum mfi_pr_state { 1400 MFI_PR_STATE_STOPPED = 0, 1401 MFI_PR_STATE_READY = 1, 1402 MFI_PR_STATE_ACTIVE = 2, 1403 MFI_PR_STATE_ABORTED = 0xff 1404 }; 1405 1406 struct mfi_pr_status { 1407 uint32_t num_iteration; 1408 uint8_t state; 1409 uint8_t num_pd_done; 1410 uint8_t reserved[10]; 1411 }; 1412 1413 enum mfi_pr_opmode { 1414 MFI_PR_OPMODE_AUTO = 0, 1415 MFI_PR_OPMODE_MANUAL = 1, 1416 MFI_PR_OPMODE_DISABLED = 2 1417 }; 1418 1419 struct mfi_pr_properties { 1420 uint8_t op_mode; 1421 uint8_t max_pd; 1422 uint8_t reserved; 1423 uint8_t exclude_ld_count; 1424 uint16_t excluded_ld[MFI_MAX_LD]; 1425 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1426 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1427 uint32_t next_exec; 1428 uint32_t exec_freq; 1429 uint32_t clear_freq; 1430 }; 1431 1432 /* ThunderBolt support */ 1433 1434 /* 1435 * Raid Context structure which describes MegaRAID specific IO Paramenters 1436 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1437 */ 1438 typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1439 uint16_t resvd0; /* 0x00 - 0x01 */ 1440 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1441 uint8_t regLockFlags; 1442 uint8_t armId; 1443 uint16_t TargetID; /* 0x06 - 0x07 */ 1444 1445 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1446 1447 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1448 1449 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1450 uint8_t exStatus; /* 0x16 */ 1451 uint8_t Status; /* 0x17 status */ 1452 1453 uint8_t RAIDFlags; /* 0x18 */ 1454 uint8_t numSGE; /* 0x19 numSge */ 1455 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1456 uint8_t spanArm; /* 0x1C */ 1457 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1458 } MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1459 1460 /***************************************************************************** 1461 * 1462 * Message Functions 1463 * 1464 *****************************************************************************/ 1465 1466 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1467 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1468 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1469 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1470 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1471 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1472 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1473 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1474 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1475 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1476 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1477 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1478 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1479 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1480 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1481 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1482 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1483 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1484 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1485 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1486 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1487 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1488 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1489 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1490 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1491 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1492 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1493 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1494 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1495 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1496 1497 /* Doorbell functions */ 1498 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1499 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1500 1501 /***************************************************************************** 1502 * 1503 * MPI Version Definitions 1504 * 1505 *****************************************************************************/ 1506 1507 #define MPI2_VERSION_MAJOR (0x02) 1508 #define MPI2_VERSION_MINOR (0x00) 1509 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1510 #define MPI2_VERSION_MAJOR_SHIFT (8) 1511 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1512 #define MPI2_VERSION_MINOR_SHIFT (0) 1513 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1514 MPI2_VERSION_MINOR) 1515 1516 #define MPI2_VERSION_02_00 (0x0200) 1517 1518 /* versioning for this MPI header set */ 1519 #define MPI2_HEADER_VERSION_UNIT (0x10) 1520 #define MPI2_HEADER_VERSION_DEV (0x00) 1521 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1522 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1523 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1524 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1525 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1526 MPI2_HEADER_VERSION_DEV) 1527 1528 1529 /* IOCInit Request message */ 1530 struct MPI2_IOC_INIT_REQUEST { 1531 uint8_t WhoInit; /* 0x00 */ 1532 uint8_t Reserved1; /* 0x01 */ 1533 uint8_t ChainOffset; /* 0x02 */ 1534 uint8_t Function; /* 0x03 */ 1535 uint16_t Reserved2; /* 0x04 */ 1536 uint8_t Reserved3; /* 0x06 */ 1537 uint8_t MsgFlags; /* 0x07 */ 1538 uint8_t VP_ID; /* 0x08 */ 1539 uint8_t VF_ID; /* 0x09 */ 1540 uint16_t Reserved4; /* 0x0A */ 1541 uint16_t MsgVersion; /* 0x0C */ 1542 uint16_t HeaderVersion; /* 0x0E */ 1543 uint32_t Reserved5; /* 0x10 */ 1544 uint16_t Reserved6; /* 0x14 */ 1545 uint8_t Reserved7; /* 0x16 */ 1546 uint8_t HostMSIxVectors; /* 0x17 */ 1547 uint16_t Reserved8; /* 0x18 */ 1548 uint16_t SystemRequestFrameSize; /* 0x1A */ 1549 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1550 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1551 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1552 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1553 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1554 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1555 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1556 uint64_t TimeStamp; /* 0x40 */ 1557 }; 1558 1559 /* WhoInit values */ 1560 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1561 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1562 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1563 #define MPI2_WHOINIT_PCI_PEER (0x03) 1564 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1565 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1566 1567 struct MPI2_SGE_CHAIN_UNION { 1568 uint16_t Length; 1569 uint8_t NextChainOffset; 1570 uint8_t Flags; 1571 union { 1572 uint32_t Address32; 1573 uint64_t Address64; 1574 } u; 1575 }; 1576 1577 struct MPI2_IEEE_SGE_SIMPLE32 { 1578 uint32_t Address; 1579 uint32_t FlagsLength; 1580 }; 1581 1582 struct MPI2_IEEE_SGE_SIMPLE64 { 1583 uint64_t Address; 1584 uint32_t Length; 1585 uint16_t Reserved1; 1586 uint8_t Reserved2; 1587 uint8_t Flags; 1588 }; 1589 1590 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1591 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1592 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1593 } MPI2_IEEE_SGE_SIMPLE_UNION; 1594 1595 typedef struct _MPI2_SGE_SIMPLE_UNION { 1596 uint32_t FlagsLength; 1597 union { 1598 uint32_t Address32; 1599 uint64_t Address64; 1600 } u; 1601 } MPI2_SGE_SIMPLE_UNION; 1602 1603 /**************************************************************************** 1604 * IEEE SGE field definitions and masks 1605 ****************************************************************************/ 1606 1607 /* Flags field bit definitions */ 1608 1609 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1610 1611 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1612 1613 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1614 1615 /* Element Type */ 1616 1617 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1618 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1619 1620 /* Data Location Address Space */ 1621 1622 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1623 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1624 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1625 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1626 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1627 1628 /* Address Size */ 1629 1630 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1631 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1632 1633 /*******************/ 1634 /* SCSI IO Control bits */ 1635 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1636 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1637 1638 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1639 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1640 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1641 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1642 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1643 1644 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1645 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1646 1647 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1648 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1649 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1650 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1651 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1652 1653 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1654 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1655 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1656 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1657 1658 /*******************/ 1659 1660 typedef struct { 1661 uint8_t CDB[20]; /* 0x00 */ 1662 uint32_t PrimaryReferenceTag; /* 0x14 */ 1663 uint16_t PrimaryApplicationTag; /* 0x18 */ 1664 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1665 uint32_t TransferLength; /* 0x1C */ 1666 } MPI2_SCSI_IO_CDB_EEDP32; 1667 1668 1669 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1670 struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1671 struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1672 } MPI2_IEEE_SGE_CHAIN_UNION; 1673 1674 typedef union _MPI2_SIMPLE_SGE_UNION { 1675 MPI2_SGE_SIMPLE_UNION MpiSimple; 1676 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1677 } MPI2_SIMPLE_SGE_UNION; 1678 1679 typedef union _MPI2_SGE_IO_UNION { 1680 MPI2_SGE_SIMPLE_UNION MpiSimple; 1681 struct MPI2_SGE_CHAIN_UNION MpiChain; 1682 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1683 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1684 } MPI2_SGE_IO_UNION; 1685 1686 typedef union { 1687 uint8_t CDB32[32]; 1688 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1689 MPI2_SGE_SIMPLE_UNION SGE; 1690 } MPI2_SCSI_IO_CDB_UNION; 1691 1692 1693 /* MPI 2.5 SGLs */ 1694 1695 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1696 1697 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1698 uint64_t Address; 1699 uint32_t Length; 1700 uint16_t Reserved1; 1701 uint8_t NextChainOffset; 1702 uint8_t Flags; 1703 } MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1704 1705 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1706 1707 1708 /********/ 1709 1710 /* 1711 * RAID SCSI IO Request Message 1712 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1713 */ 1714 struct mfi_mpi2_request_raid_scsi_io { 1715 uint16_t DevHandle; /* 0x00 */ 1716 uint8_t ChainOffset; /* 0x02 */ 1717 uint8_t Function; /* 0x03 */ 1718 uint16_t Reserved1; /* 0x04 */ 1719 uint8_t Reserved2; /* 0x06 */ 1720 uint8_t MsgFlags; /* 0x07 */ 1721 uint8_t VP_ID; /* 0x08 */ 1722 uint8_t VF_ID; /* 0x09 */ 1723 uint16_t Reserved3; /* 0x0A */ 1724 uint32_t SenseBufferLowAddress; /* 0x0C */ 1725 uint16_t SGLFlags; /* 0x10 */ 1726 uint8_t SenseBufferLength; /* 0x12 */ 1727 uint8_t Reserved4; /* 0x13 */ 1728 uint8_t SGLOffset0; /* 0x14 */ 1729 uint8_t SGLOffset1; /* 0x15 */ 1730 uint8_t SGLOffset2; /* 0x16 */ 1731 uint8_t SGLOffset3; /* 0x17 */ 1732 uint32_t SkipCount; /* 0x18 */ 1733 uint32_t DataLength; /* 0x1C */ 1734 uint32_t BidirectionalDataLength; /* 0x20 */ 1735 uint16_t IoFlags; /* 0x24 */ 1736 uint16_t EEDPFlags; /* 0x26 */ 1737 uint32_t EEDPBlockSize; /* 0x28 */ 1738 uint32_t SecondaryReferenceTag; /* 0x2C */ 1739 uint16_t SecondaryApplicationTag; /* 0x30 */ 1740 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1741 uint8_t LUN[8]; /* 0x34 */ 1742 uint32_t Control; /* 0x3C */ 1743 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1744 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1745 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1746 } __packed; 1747 1748 /* 1749 * MPT RAID MFA IO Descriptor. 1750 */ 1751 typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1752 uint32_t RequestFlags : 8; 1753 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1754 uint32_t MessageAddress2; /* bits 61:32 */ 1755 } MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1756 1757 struct mfi_mpi2_request_header { 1758 uint8_t RequestFlags; /* 0x00 */ 1759 uint8_t MSIxIndex; /* 0x01 */ 1760 uint16_t SMID; /* 0x02 */ 1761 uint16_t LMID; /* 0x04 */ 1762 }; 1763 1764 /* defines for the RequestFlags field */ 1765 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1766 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1767 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1768 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1769 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1770 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1771 1772 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1773 1774 struct mfi_mpi2_request_high_priority { 1775 struct mfi_mpi2_request_header header; 1776 uint16_t reserved; 1777 }; 1778 1779 struct mfi_mpi2_request_scsi_io { 1780 struct mfi_mpi2_request_header header; 1781 uint16_t scsi_io_dev_handle; 1782 }; 1783 1784 struct mfi_mpi2_request_scsi_target { 1785 struct mfi_mpi2_request_header header; 1786 uint16_t scsi_target_io_index; 1787 }; 1788 1789 /* Request Descriptors */ 1790 union mfi_mpi2_request_descriptor { 1791 struct mfi_mpi2_request_header header; 1792 struct mfi_mpi2_request_high_priority high_priority; 1793 struct mfi_mpi2_request_scsi_io scsi_io; 1794 struct mfi_mpi2_request_scsi_target scsi_target; 1795 uint64_t words; 1796 }; 1797 1798 1799 struct mfi_mpi2_reply_header { 1800 uint8_t ReplyFlags; /* 0x00 */ 1801 uint8_t MSIxIndex; /* 0x01 */ 1802 uint16_t SMID; /* 0x02 */ 1803 }; 1804 1805 /* defines for the ReplyFlags field */ 1806 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1807 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1808 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1809 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1810 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1811 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1812 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1813 1814 /* values for marking a reply descriptor as unused */ 1815 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1816 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1817 1818 struct mfi_mpi2_reply_default { 1819 struct mfi_mpi2_reply_header header; 1820 uint32_t DescriptorTypeDependent2; 1821 }; 1822 1823 struct mfi_mpi2_reply_address { 1824 struct mfi_mpi2_reply_header header; 1825 uint32_t ReplyFrameAddress; 1826 }; 1827 1828 struct mfi_mpi2_reply_scsi_io { 1829 struct mfi_mpi2_reply_header header; 1830 uint16_t TaskTag; /* 0x04 */ 1831 uint16_t Reserved1; /* 0x06 */ 1832 }; 1833 1834 struct mfi_mpi2_reply_target_assist { 1835 struct mfi_mpi2_reply_header header; 1836 uint8_t SequenceNumber; /* 0x04 */ 1837 uint8_t Reserved1; /* 0x04 */ 1838 uint16_t IoIndex; /* 0x06 */ 1839 }; 1840 1841 struct mfi_mpi2_reply_target_cmd_buffer { 1842 struct mfi_mpi2_reply_header header; 1843 uint8_t SequenceNumber; /* 0x04 */ 1844 uint8_t Flags; /* 0x04 */ 1845 uint16_t InitiatorDevHandle; /* 0x06 */ 1846 uint16_t IoIndex; /* 0x06 */ 1847 }; 1848 1849 struct mfi_mpi2_reply_raid_accel { 1850 struct mfi_mpi2_reply_header header; 1851 uint8_t SequenceNumber; /* 0x04 */ 1852 uint32_t Reserved; /* 0x04 */ 1853 }; 1854 1855 /* union of Reply Descriptors */ 1856 union mfi_mpi2_reply_descriptor { 1857 struct mfi_mpi2_reply_header header; 1858 struct mfi_mpi2_reply_scsi_io scsi_io; 1859 struct mfi_mpi2_reply_target_assist target_assist; 1860 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1861 struct mfi_mpi2_reply_raid_accel raid_accel; 1862 struct mfi_mpi2_reply_default reply_default; 1863 uint64_t words; 1864 }; 1865 1866 struct IO_REQUEST_INFO { 1867 uint64_t ldStartBlock; 1868 uint32_t numBlocks; 1869 uint16_t ldTgtId; 1870 uint8_t isRead; 1871 uint16_t devHandle; 1872 uint64_t pdBlock; 1873 uint8_t fpOkForIo; 1874 }; 1875 1876 #define MFI_SCSI_MAX_TARGETS 128 1877 #define MFI_SCSI_MAX_LUNS 8 1878 #define MFI_SCSI_INITIATOR_ID 255 1879 #define MFI_SCSI_MAX_CMDS 8 1880 #define MFI_SCSI_MAX_CDB_LEN 16 1881 1882 #endif /* _MFIREG_H */ 1883