1 /*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /*- 27 * Copyright (c) 2007 LSI Corp. 28 * Copyright (c) 2007 Rajesh Prabhakaran. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53 #ifndef _MFIREG_H 54 #define _MFIREG_H 55 56 #include <sys/cdefs.h> 57 __FBSDID("$FreeBSD$"); 58 59 /* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. 66 */ 67 #define MEGAMFI_FRAME_SIZE 64 68 /* 69 * Start with the register set. All registers are 32 bits wide. 70 * The usual Intel IOP style setup. 71 */ 72 #define MFI_IMSG0 0x10 /* Inbound message 0 */ 73 #define MFI_IMSG1 0x14 /* Inbound message 1 */ 74 #define MFI_OMSG0 0x18 /* Outbound message 0 */ 75 #define MFI_OMSG1 0x1c /* Outbound message 1 */ 76 #define MFI_IDB 0x20 /* Inbound doorbell */ 77 #define MFI_ISTS 0x24 /* Inbound interrupt status */ 78 #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 79 #define MFI_ODB 0x2c /* Outbound doorbell */ 80 #define MFI_OSTS 0x30 /* Outbound interrupt status */ 81 #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 82 #define MFI_IQP 0x40 /* Inbound queue port */ 83 #define MFI_OQP 0x44 /* Outbound queue port */ 84 85 /* 86 * ThunderBolt specific Register 87 */ 88 89 #define MFI_RPI 0x6c /* reply_post_host_index */ 90 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 91 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 92 93 /* 94 * 1078 specific related register 95 */ 96 #define MFI_ODR0 0x9c /* outbound doorbell register0 */ 97 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 98 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 99 #define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 100 #define MFI_RMI 0x2 /* reply message interrupt */ 101 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 102 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 103 104 /* OCR registers */ 105 #define MFI_WSR 0x004 /* write sequence register */ 106 #define MFI_HDR 0x008 /* host diagnostic register */ 107 #define MFI_RSR 0x3c3 /* Reset Status Register */ 108 109 /* 110 * GEN2 specific changes 111 */ 112 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 113 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 114 115 /* 116 * skinny specific changes 117 */ 118 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 119 #define MFI_IQPL 0x000000c0 120 #define MFI_IQPH 0x000000c4 121 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 122 123 /* Bits for MFI_OSTS */ 124 #define MFI_OSTS_INTR_VALID 0x00000002 125 126 /* OCR specific flags */ 127 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 128 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 129 130 /* 131 * Firmware state values. Found in OMSG0 during initialization. 132 */ 133 #define MFI_FWSTATE_MASK 0xf0000000 134 #define MFI_FWSTATE_UNDEFINED 0x00000000 135 #define MFI_FWSTATE_BB_INIT 0x10000000 136 #define MFI_FWSTATE_FW_INIT 0x40000000 137 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 138 #define MFI_FWSTATE_FW_INIT_2 0x70000000 139 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 140 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 141 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 142 #define MFI_FWSTATE_READY 0xb0000000 143 #define MFI_FWSTATE_OPERATIONAL 0xc0000000 144 #define MFI_FWSTATE_FAULT 0xf0000000 145 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 146 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 147 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 148 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 149 #define MFI_RESET_REQUIRED 0x00000001 150 151 /* ThunderBolt Support */ 152 #define MFI_FWSTATE_TB_MASK 0xf0000000 153 #define MFI_FWSTATE_TB_RESET 0x00000000 154 #define MFI_FWSTATE_TB_READY 0x10000000 155 #define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 156 #define MFI_FWSTATE_TB_FAULT 0x40000000 157 158 /* 159 * Control bits to drive the card to ready state. These go into the IDB 160 * register. 161 */ 162 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 163 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 164 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 165 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 166 #define MFI_FWINIT_HOTPLUG 0x00000010 167 168 /* ADP reset flags */ 169 #define MFI_STOP_ADP 0x00000020 170 #define MFI_ADP_RESET 0x00000040 171 #define DIAG_WRITE_ENABLE 0x00000080 172 #define DIAG_RESET_ADAPTER 0x00000004 173 174 /* MFI Commands */ 175 typedef enum { 176 MFI_CMD_INIT = 0x00, 177 MFI_CMD_LD_READ, 178 MFI_CMD_LD_WRITE, 179 MFI_CMD_LD_SCSI_IO, 180 MFI_CMD_PD_SCSI_IO, 181 MFI_CMD_DCMD, 182 MFI_CMD_ABORT, 183 MFI_CMD_SMP, 184 MFI_CMD_STP 185 } mfi_cmd_t; 186 187 /* Direct commands */ 188 typedef enum { 189 MFI_DCMD_CTRL_GETINFO = 0x01010000, 190 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 191 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 192 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 193 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 194 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 195 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 196 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 197 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 198 MFI_DCMD_PR_GET_STATUS = 0x01070100, 199 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 200 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 201 MFI_DCMD_PR_START = 0x01070400, 202 MFI_DCMD_PR_STOP = 0x01070500, 203 MFI_DCMD_TIME_SECS_GET = 0x01080201, 204 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 205 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 206 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 207 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 208 MFI_DCMD_PD_GET_LIST = 0x02010000, 209 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 210 MFI_DCMD_PD_GET_INFO = 0x02020000, 211 MFI_DCMD_PD_STATE_SET = 0x02030100, 212 MFI_DCMD_PD_REBUILD_START = 0x02040100, 213 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 214 MFI_DCMD_PD_CLEAR_START = 0x02050100, 215 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 216 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 217 MFI_DCMD_PD_LOCATE_START = 0x02070100, 218 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 219 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 220 MFI_DCMD_LD_SYNC = 0x0300e102, 221 MFI_DCMD_LD_GET_LIST = 0x03010000, 222 MFI_DCMD_LD_GET_INFO = 0x03020000, 223 MFI_DCMD_LD_GET_PROP = 0x03030000, 224 MFI_DCMD_LD_SET_PROP = 0x03040000, 225 MFI_DCMD_LD_INIT_START = 0x03060100, 226 MFI_DCMD_LD_DELETE = 0x03090000, 227 MFI_DCMD_CFG_READ = 0x04010000, 228 MFI_DCMD_CFG_ADD = 0x04020000, 229 MFI_DCMD_CFG_CLEAR = 0x04030000, 230 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 231 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 232 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 233 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 234 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 235 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 236 MFI_DCMD_CLUSTER = 0x08000000, 237 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 238 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 239 } mfi_dcmd_t; 240 241 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 242 #define MFI_FLUSHCACHE_CTRL 0x01 243 #define MFI_FLUSHCACHE_DISK 0x02 244 245 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 246 #define MFI_SHUTDOWN_SPINDOWN 0x01 247 248 /* 249 * MFI Frame flags 250 */ 251 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 252 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 253 #define MFI_FRAME_SGL32 0x0000 254 #define MFI_FRAME_SGL64 0x0002 255 #define MFI_FRAME_SENSE32 0x0000 256 #define MFI_FRAME_SENSE64 0x0004 257 #define MFI_FRAME_DIR_NONE 0x0000 258 #define MFI_FRAME_DIR_WRITE 0x0008 259 #define MFI_FRAME_DIR_READ 0x0010 260 #define MFI_FRAME_DIR_BOTH 0x0018 261 #define MFI_FRAME_IEEE_SGL 0x0020 262 263 /* ThunderBolt Specific */ 264 265 /* 266 * Pre-TB command size and TB command size. 267 * We will be checking it at the load time for the time being 268 */ 269 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 270 271 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 272 /* 273 * We are defining only 128 byte message to reduce memory move over head 274 * and also it will reduce the SRB extension size by 128byte compared with 275 * 256 message size 276 */ 277 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 278 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 279 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 280 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 281 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 282 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 283 284 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 285 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 286 287 #define MR_INTERNAL_MFI_FRAMES_SMID 1 288 #define MR_CTRL_EVENT_WAIT_SMID 2 289 #define MR_INTERNAL_DRIVER_RESET_SMID 3 290 291 292 /* MFI Status codes */ 293 typedef enum { 294 MFI_STAT_OK = 0x00, 295 MFI_STAT_INVALID_CMD, 296 MFI_STAT_INVALID_DCMD, 297 MFI_STAT_INVALID_PARAMETER, 298 MFI_STAT_INVALID_SEQUENCE_NUMBER, 299 MFI_STAT_ABORT_NOT_POSSIBLE, 300 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 301 MFI_STAT_APP_IN_USE, 302 MFI_STAT_APP_NOT_INITIALIZED, 303 MFI_STAT_ARRAY_INDEX_INVALID, 304 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 305 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 306 MFI_STAT_DEVICE_NOT_FOUND, 307 MFI_STAT_DRIVE_TOO_SMALL, 308 MFI_STAT_FLASH_ALLOC_FAIL, 309 MFI_STAT_FLASH_BUSY, 310 MFI_STAT_FLASH_ERROR = 0x10, 311 MFI_STAT_FLASH_IMAGE_BAD, 312 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 313 MFI_STAT_FLASH_NOT_OPEN, 314 MFI_STAT_FLASH_NOT_STARTED, 315 MFI_STAT_FLUSH_FAILED, 316 MFI_STAT_HOST_CODE_NOT_FOUNT, 317 MFI_STAT_LD_CC_IN_PROGRESS, 318 MFI_STAT_LD_INIT_IN_PROGRESS, 319 MFI_STAT_LD_LBA_OUT_OF_RANGE, 320 MFI_STAT_LD_MAX_CONFIGURED, 321 MFI_STAT_LD_NOT_OPTIMAL, 322 MFI_STAT_LD_RBLD_IN_PROGRESS, 323 MFI_STAT_LD_RECON_IN_PROGRESS, 324 MFI_STAT_LD_WRONG_RAID_LEVEL, 325 MFI_STAT_MAX_SPARES_EXCEEDED, 326 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 327 MFI_STAT_MFC_HW_ERROR, 328 MFI_STAT_NO_HW_PRESENT, 329 MFI_STAT_NOT_FOUND, 330 MFI_STAT_NOT_IN_ENCL, 331 MFI_STAT_PD_CLEAR_IN_PROGRESS, 332 MFI_STAT_PD_TYPE_WRONG, 333 MFI_STAT_PR_DISABLED, 334 MFI_STAT_ROW_INDEX_INVALID, 335 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 336 MFI_STAT_SAS_CONFIG_INVALID_DATA, 337 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 338 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 339 MFI_STAT_SCSI_DONE_WITH_ERROR, 340 MFI_STAT_SCSI_IO_FAILED, 341 MFI_STAT_SCSI_RESERVATION_CONFLICT, 342 MFI_STAT_SHUTDOWN_FAILED = 0x30, 343 MFI_STAT_TIME_NOT_SET, 344 MFI_STAT_WRONG_STATE, 345 MFI_STAT_LD_OFFLINE, 346 MFI_STAT_PEER_NOTIFICATION_REJECTED, 347 MFI_STAT_PEER_NOTIFICATION_FAILED, 348 MFI_STAT_RESERVATION_IN_PROGRESS, 349 MFI_STAT_I2C_ERRORS_DETECTED, 350 MFI_STAT_PCI_ERRORS_DETECTED, 351 MFI_STAT_DIAG_FAILED, 352 MFI_STAT_BOOT_MSG_PENDING, 353 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 354 MFI_STAT_INVALID_STATUS = 0xFF 355 } mfi_status_t; 356 357 typedef enum { 358 MFI_EVT_CLASS_DEBUG = -2, 359 MFI_EVT_CLASS_PROGRESS = -1, 360 MFI_EVT_CLASS_INFO = 0, 361 MFI_EVT_CLASS_WARNING = 1, 362 MFI_EVT_CLASS_CRITICAL = 2, 363 MFI_EVT_CLASS_FATAL = 3, 364 MFI_EVT_CLASS_DEAD = 4 365 } mfi_evt_class_t; 366 367 typedef enum { 368 MFI_EVT_LOCALE_LD = 0x0001, 369 MFI_EVT_LOCALE_PD = 0x0002, 370 MFI_EVT_LOCALE_ENCL = 0x0004, 371 MFI_EVT_LOCALE_BBU = 0x0008, 372 MFI_EVT_LOCALE_SAS = 0x0010, 373 MFI_EVT_LOCALE_CTRL = 0x0020, 374 MFI_EVT_LOCALE_CONFIG = 0x0040, 375 MFI_EVT_LOCALE_CLUSTER = 0x0080, 376 MFI_EVT_LOCALE_ALL = 0xffff 377 } mfi_evt_locale_t; 378 379 typedef enum { 380 MR_EVT_ARGS_NONE = 0x00, 381 MR_EVT_ARGS_CDB_SENSE, 382 MR_EVT_ARGS_LD, 383 MR_EVT_ARGS_LD_COUNT, 384 MR_EVT_ARGS_LD_LBA, 385 MR_EVT_ARGS_LD_OWNER, 386 MR_EVT_ARGS_LD_LBA_PD_LBA, 387 MR_EVT_ARGS_LD_PROG, 388 MR_EVT_ARGS_LD_STATE, 389 MR_EVT_ARGS_LD_STRIP, 390 MR_EVT_ARGS_PD, 391 MR_EVT_ARGS_PD_ERR, 392 MR_EVT_ARGS_PD_LBA, 393 MR_EVT_ARGS_PD_LBA_LD, 394 MR_EVT_ARGS_PD_PROG, 395 MR_EVT_ARGS_PD_STATE, 396 MR_EVT_ARGS_PCI, 397 MR_EVT_ARGS_RATE, 398 MR_EVT_ARGS_STR, 399 MR_EVT_ARGS_TIME, 400 MR_EVT_ARGS_ECC 401 } mfi_evt_args; 402 403 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 404 #define MR_EVT_PD_REMOVED 0x0070 405 #define MR_EVT_PD_INSERTED 0x005b 406 407 typedef enum { 408 MR_LD_CACHE_WRITE_BACK = 0x01, 409 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 410 MR_LD_CACHE_READ_AHEAD = 0x04, 411 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 412 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 413 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 414 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 415 } mfi_ld_cache; 416 #define MR_LD_CACHE_MASK 0x7f 417 418 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 419 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 420 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 421 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 422 #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 423 #define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 424 #define MR_LD_CACHE_POLICY_IO_CACHED \ 425 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 426 #define MR_LD_CACHE_POLICY_IO_DIRECT 0 427 428 typedef enum { 429 MR_PD_CACHE_UNCHANGED = 0, 430 MR_PD_CACHE_ENABLE = 1, 431 MR_PD_CACHE_DISABLE = 2 432 } mfi_pd_cache; 433 434 typedef enum { 435 MR_PD_QUERY_TYPE_ALL = 0, 436 MR_PD_QUERY_TYPE_STATE = 1, 437 MR_PD_QUERY_TYPE_POWER_STATE = 2, 438 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 439 MR_PD_QUERY_TYPE_SPEED = 4, 440 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 441 } mfi_pd_query_type; 442 443 /* 444 * Other propertities and definitions 445 */ 446 #define MFI_MAX_PD_CHANNELS 2 447 #define MFI_MAX_LD_CHANNELS 2 448 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 449 #define MFI_MAX_CHANNEL_DEVS 128 450 #define MFI_DEFAULT_ID -1 451 #define MFI_MAX_LUN 8 452 #define MFI_MAX_LD 64 453 #define MFI_MAX_PD 256 454 455 #define MFI_FRAME_SIZE 64 456 #define MFI_MBOX_SIZE 12 457 458 /* Firmware flashing can take 40s */ 459 #define MFI_POLL_TIMEOUT_SECS 50 460 461 /* Allow for speedier math calculations */ 462 #define MFI_SECTOR_LEN 512 463 464 /* Scatter Gather elements */ 465 struct mfi_sg32 { 466 uint32_t addr; 467 uint32_t len; 468 } __packed; 469 470 struct mfi_sg64 { 471 uint64_t addr; 472 uint32_t len; 473 } __packed; 474 475 struct mfi_sg_skinny { 476 uint64_t addr; 477 uint32_t len; 478 uint32_t flag; 479 } __packed; 480 481 union mfi_sgl { 482 struct mfi_sg32 sg32[1]; 483 struct mfi_sg64 sg64[1]; 484 struct mfi_sg_skinny sg_skinny[1]; 485 } __packed; 486 487 /* Message frames. All messages have a common header */ 488 struct mfi_frame_header { 489 uint8_t cmd; 490 uint8_t sense_len; 491 uint8_t cmd_status; 492 uint8_t scsi_status; 493 uint8_t target_id; 494 uint8_t lun_id; 495 uint8_t cdb_len; 496 uint8_t sg_count; 497 uint32_t context; 498 /* 499 * pad0 is MSI Specific. Not used by Driver. Zero the value before 500 * sending the command to f/w. 501 */ 502 uint32_t pad0; 503 uint16_t flags; 504 #define MFI_FRAME_DATAOUT 0x08 505 #define MFI_FRAME_DATAIN 0x10 506 uint16_t timeout; 507 uint32_t data_len; 508 } __packed; 509 510 struct mfi_init_frame { 511 struct mfi_frame_header header; 512 uint32_t qinfo_new_addr_lo; 513 uint32_t qinfo_new_addr_hi; 514 uint32_t qinfo_old_addr_lo; 515 uint32_t qinfo_old_addr_hi; 516 // Start LSIP200113393 517 uint32_t driver_ver_lo; /*28h */ 518 uint32_t driver_ver_hi; /*2Ch */ 519 520 uint32_t reserved[4]; 521 // End LSIP200113393 522 } __packed; 523 524 /* 525 * Define MFI Address Context union. 526 */ 527 #ifdef MFI_ADDRESS_IS_uint64_t 528 typedef uint64_t MFI_ADDRESS; 529 #else 530 typedef union _MFI_ADDRESS { 531 struct { 532 uint32_t addressLow; 533 uint32_t addressHigh; 534 } u; 535 uint64_t address; 536 } MFI_ADDRESS, *PMFI_ADDRESS; 537 #endif 538 539 #define MFI_IO_FRAME_SIZE 40 540 struct mfi_io_frame { 541 struct mfi_frame_header header; 542 uint32_t sense_addr_lo; 543 uint32_t sense_addr_hi; 544 uint32_t lba_lo; 545 uint32_t lba_hi; 546 union mfi_sgl sgl; 547 } __packed; 548 549 #define MFI_PASS_FRAME_SIZE 48 550 struct mfi_pass_frame { 551 struct mfi_frame_header header; 552 uint32_t sense_addr_lo; 553 uint32_t sense_addr_hi; 554 uint8_t cdb[16]; 555 union mfi_sgl sgl; 556 } __packed; 557 558 #define MFI_DCMD_FRAME_SIZE 40 559 struct mfi_dcmd_frame { 560 struct mfi_frame_header header; 561 uint32_t opcode; 562 uint8_t mbox[MFI_MBOX_SIZE]; 563 union mfi_sgl sgl; 564 } __packed; 565 566 struct mfi_abort_frame { 567 struct mfi_frame_header header; 568 uint32_t abort_context; 569 /* pad is changed to reserved.*/ 570 uint32_t reserved0; 571 uint32_t abort_mfi_addr_lo; 572 uint32_t abort_mfi_addr_hi; 573 uint32_t reserved1[6]; 574 } __packed; 575 576 struct mfi_smp_frame { 577 struct mfi_frame_header header; 578 uint64_t sas_addr; 579 union { 580 struct mfi_sg32 sg32[2]; 581 struct mfi_sg64 sg64[2]; 582 } sgl; 583 } __packed; 584 585 struct mfi_stp_frame { 586 struct mfi_frame_header header; 587 uint16_t fis[10]; 588 uint32_t stp_flags; 589 union { 590 struct mfi_sg32 sg32[2]; 591 struct mfi_sg64 sg64[2]; 592 } sgl; 593 } __packed; 594 595 union mfi_frame { 596 struct mfi_frame_header header; 597 struct mfi_init_frame init; 598 /* ThunderBolt Initialization */ 599 struct mfi_io_frame io; 600 struct mfi_pass_frame pass; 601 struct mfi_dcmd_frame dcmd; 602 struct mfi_abort_frame abort; 603 struct mfi_smp_frame smp; 604 struct mfi_stp_frame stp; 605 uint8_t bytes[MFI_FRAME_SIZE]; 606 }; 607 608 #define MFI_SENSE_LEN 128 609 struct mfi_sense { 610 uint8_t data[MFI_SENSE_LEN]; 611 }; 612 613 /* The queue init structure that is passed with the init message */ 614 struct mfi_init_qinfo { 615 uint32_t flags; 616 uint32_t rq_entries; 617 uint32_t rq_addr_lo; 618 uint32_t rq_addr_hi; 619 uint32_t pi_addr_lo; 620 uint32_t pi_addr_hi; 621 uint32_t ci_addr_lo; 622 uint32_t ci_addr_hi; 623 } __packed; 624 625 /* SAS (?) controller properties, part of mfi_ctrl_info */ 626 struct mfi_ctrl_props { 627 uint16_t seq_num; 628 uint16_t pred_fail_poll_interval; 629 uint16_t intr_throttle_cnt; 630 uint16_t intr_throttle_timeout; 631 uint8_t rebuild_rate; 632 uint8_t patrol_read_rate; 633 uint8_t bgi_rate; 634 uint8_t cc_rate; 635 uint8_t recon_rate; 636 uint8_t cache_flush_interval; 637 uint8_t spinup_drv_cnt; 638 uint8_t spinup_delay; 639 uint8_t cluster_enable; 640 uint8_t coercion_mode; 641 uint8_t alarm_enable; 642 uint8_t disable_auto_rebuild; 643 uint8_t disable_battery_warn; 644 uint8_t ecc_bucket_size; 645 uint16_t ecc_bucket_leak_rate; 646 uint8_t restore_hotspare_on_insertion; 647 uint8_t expose_encl_devices; 648 uint8_t maintainPdFailHistory; 649 uint8_t disallowHostRequestReordering; 650 /* set TRUE to abort CC on detecting an inconsistency */ 651 uint8_t abortCCOnError; 652 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 653 uint8_t loadBalanceMode; 654 /* 655 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 656 * h/w mechansim like GPIO pins 657 * 1 - disable auto detect SGPIO, 658 * 2 - disable i2c SEP auto detect 659 * 3 - disable both auto detect 660 */ 661 uint8_t disableAutoDetectBackplane; 662 /* 663 * % of source LD to be reserved for a VDs snapshot in snapshot 664 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 665 */ 666 uint8_t snapVDSpace; 667 668 /* 669 * Add properties that can be controlled by a bit in the following 670 * structure. 671 */ 672 struct { 673 /* set TRUE to disable copyBack (0=copback enabled) */ 674 uint32_t copyBackDisabled :1; 675 uint32_t SMARTerEnabled :1; 676 uint32_t prCorrectUnconfiguredAreas :1; 677 uint32_t useFdeOnly :1; 678 uint32_t disableNCQ :1; 679 uint32_t SSDSMARTerEnabled :1; 680 uint32_t SSDPatrolReadEnabled :1; 681 uint32_t enableSpinDownUnconfigured :1; 682 uint32_t autoEnhancedImport :1; 683 uint32_t enableSecretKeyControl :1; 684 uint32_t disableOnlineCtrlReset :1; 685 uint32_t allowBootWithPinnedCache :1; 686 uint32_t disableSpinDownHS :1; 687 uint32_t enableJBOD :1; 688 uint32_t reserved :18; 689 } OnOffProperties; 690 /* 691 * % of source LD to be reserved for auto snapshot in snapshot 692 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 693 */ 694 uint8_t autoSnapVDSpace; 695 /* 696 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 697 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 698 */ 699 uint8_t viewSpace; 700 /* # of idle minutes before device is spun down (0=use FW defaults) */ 701 uint16_t spinDownTime; 702 uint8_t reserved[24]; 703 } __packed; 704 705 /* PCI information about the card. */ 706 struct mfi_info_pci { 707 uint16_t vendor; 708 uint16_t device; 709 uint16_t subvendor; 710 uint16_t subdevice; 711 uint8_t reserved[24]; 712 } __packed; 713 714 /* Host (front end) interface information */ 715 struct mfi_info_host { 716 uint8_t type; 717 #define MFI_INFO_HOST_PCIX 0x01 718 #define MFI_INFO_HOST_PCIE 0x02 719 #define MFI_INFO_HOST_ISCSI 0x04 720 #define MFI_INFO_HOST_SAS3G 0x08 721 uint8_t reserved[6]; 722 uint8_t port_count; 723 uint64_t port_addr[8]; 724 } __packed; 725 726 /* Device (back end) interface information */ 727 struct mfi_info_device { 728 uint8_t type; 729 #define MFI_INFO_DEV_SPI 0x01 730 #define MFI_INFO_DEV_SAS3G 0x02 731 #define MFI_INFO_DEV_SATA1 0x04 732 #define MFI_INFO_DEV_SATA3G 0x08 733 uint8_t reserved[6]; 734 uint8_t port_count; 735 uint64_t port_addr[8]; 736 } __packed; 737 738 /* Firmware component information */ 739 struct mfi_info_component { 740 char name[8]; 741 char version[32]; 742 char build_date[16]; 743 char build_time[16]; 744 } __packed; 745 746 /* Controller default settings */ 747 struct mfi_defaults { 748 uint64_t sas_addr; 749 uint8_t phy_polarity; 750 uint8_t background_rate; 751 uint8_t stripe_size; 752 uint8_t flush_time; 753 uint8_t write_back; 754 uint8_t read_ahead; 755 uint8_t cache_when_bbu_bad; 756 uint8_t cached_io; 757 uint8_t smart_mode; 758 uint8_t alarm_disable; 759 uint8_t coercion; 760 uint8_t zrc_config; 761 uint8_t dirty_led_shows_drive_activity; 762 uint8_t bios_continue_on_error; 763 uint8_t spindown_mode; 764 uint8_t allowed_device_types; 765 uint8_t allow_mix_in_enclosure; 766 uint8_t allow_mix_in_ld; 767 uint8_t allow_sata_in_cluster; 768 uint8_t max_chained_enclosures; 769 uint8_t disable_ctrl_r; 770 uint8_t enabel_web_bios; 771 uint8_t phy_polarity_split; 772 uint8_t direct_pd_mapping; 773 uint8_t bios_enumerate_lds; 774 uint8_t restored_hot_spare_on_insertion; 775 uint8_t expose_enclosure_devices; 776 uint8_t maintain_pd_fail_history; 777 uint8_t resv[28]; 778 } __packed; 779 780 /* Controller default settings */ 781 struct mfi_bios_data { 782 uint16_t boot_target_id; 783 uint8_t do_not_int_13; 784 uint8_t continue_on_error; 785 uint8_t verbose; 786 uint8_t geometry; 787 uint8_t expose_all_drives; 788 uint8_t reserved[56]; 789 uint8_t check_sum; 790 } __packed; 791 792 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 793 struct mfi_ctrl_info { 794 struct mfi_info_pci pci; 795 struct mfi_info_host host; 796 struct mfi_info_device device; 797 798 /* Firmware components that are present and active. */ 799 uint32_t image_check_word; 800 uint32_t image_component_count; 801 struct mfi_info_component image_component[8]; 802 803 /* Firmware components that have been flashed but are inactive */ 804 uint32_t pending_image_component_count; 805 struct mfi_info_component pending_image_component[8]; 806 807 uint8_t max_arms; 808 uint8_t max_spans; 809 uint8_t max_arrays; 810 uint8_t max_lds; 811 char product_name[80]; 812 char serial_number[32]; 813 uint32_t hw_present; 814 #define MFI_INFO_HW_BBU 0x01 815 #define MFI_INFO_HW_ALARM 0x02 816 #define MFI_INFO_HW_NVRAM 0x04 817 #define MFI_INFO_HW_UART 0x08 818 uint32_t current_fw_time; 819 uint16_t max_cmds; 820 uint16_t max_sg_elements; 821 uint32_t max_request_size; 822 uint16_t lds_present; 823 uint16_t lds_degraded; 824 uint16_t lds_offline; 825 uint16_t pd_present; 826 uint16_t pd_disks_present; 827 uint16_t pd_disks_pred_failure; 828 uint16_t pd_disks_failed; 829 uint16_t nvram_size; 830 uint16_t memory_size; 831 uint16_t flash_size; 832 uint16_t ram_correctable_errors; 833 uint16_t ram_uncorrectable_errors; 834 uint8_t cluster_allowed; 835 uint8_t cluster_active; 836 uint16_t max_strips_per_io; 837 838 uint32_t raid_levels; 839 #define MFI_INFO_RAID_0 0x01 840 #define MFI_INFO_RAID_1 0x02 841 #define MFI_INFO_RAID_5 0x04 842 #define MFI_INFO_RAID_1E 0x08 843 #define MFI_INFO_RAID_6 0x10 844 845 uint32_t adapter_ops; 846 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 847 #define MFI_INFO_AOPS_CC_RATE 0x0002 848 #define MFI_INFO_AOPS_BGI_RATE 0x0004 849 #define MFI_INFO_AOPS_RECON_RATE 0x0008 850 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 851 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 852 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 853 #define MFI_INFO_AOPS_BBU 0x0080 854 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 855 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 856 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 857 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 858 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 859 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 860 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 861 862 uint32_t ld_ops; 863 #define MFI_INFO_LDOPS_READ_POLICY 0x01 864 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 865 #define MFI_INFO_LDOPS_IO_POLICY 0x04 866 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 867 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 868 869 struct { 870 uint8_t min; 871 uint8_t max; 872 uint8_t reserved[2]; 873 } __packed stripe_sz_ops; 874 875 uint32_t pd_ops; 876 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 877 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 878 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 879 880 uint32_t pd_mix_support; 881 #define MFI_INFO_PDMIX_SAS 0x01 882 #define MFI_INFO_PDMIX_SATA 0x02 883 #define MFI_INFO_PDMIX_ENCL 0x04 884 #define MFI_INFO_PDMIX_LD 0x08 885 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 886 887 uint8_t ecc_bucket_count; 888 uint8_t reserved2[11]; 889 struct mfi_ctrl_props properties; 890 char package_version[0x60]; 891 uint8_t pad[0x800 - 0x6a0]; 892 } __packed; 893 894 /* keep track of an event. */ 895 union mfi_evt { 896 struct { 897 uint16_t locale; 898 uint8_t reserved; 899 int8_t evt_class; 900 } members; 901 uint32_t word; 902 } __packed; 903 904 /* event log state. */ 905 struct mfi_evt_log_state { 906 uint32_t newest_seq_num; 907 uint32_t oldest_seq_num; 908 uint32_t clear_seq_num; 909 uint32_t shutdown_seq_num; 910 uint32_t boot_seq_num; 911 } __packed; 912 913 struct mfi_progress { 914 uint16_t progress; 915 uint16_t elapsed_seconds; 916 } __packed; 917 918 struct mfi_evt_ld { 919 uint16_t target_id; 920 uint8_t ld_index; 921 uint8_t reserved; 922 } __packed; 923 924 struct mfi_evt_pd { 925 uint16_t device_id; 926 uint8_t enclosure_index; 927 uint8_t slot_number; 928 } __packed; 929 930 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 931 struct mfi_evt_detail { 932 uint32_t seq; 933 uint32_t time; 934 uint32_t code; 935 union mfi_evt evt_class; 936 uint8_t arg_type; 937 uint8_t reserved1[15]; 938 939 union { 940 struct { 941 struct mfi_evt_pd pd; 942 uint8_t cdb_len; 943 uint8_t sense_len; 944 uint8_t reserved[2]; 945 uint8_t cdb[16]; 946 uint8_t sense[64]; 947 } cdb_sense; 948 949 struct mfi_evt_ld ld; 950 951 struct { 952 struct mfi_evt_ld ld; 953 uint64_t count; 954 } ld_count; 955 956 struct { 957 uint64_t lba; 958 struct mfi_evt_ld ld; 959 } ld_lba; 960 961 struct { 962 struct mfi_evt_ld ld; 963 uint32_t pre_owner; 964 uint32_t new_owner; 965 } ld_owner; 966 967 struct { 968 uint64_t ld_lba; 969 uint64_t pd_lba; 970 struct mfi_evt_ld ld; 971 struct mfi_evt_pd pd; 972 } ld_lba_pd_lba; 973 974 struct { 975 struct mfi_evt_ld ld; 976 struct mfi_progress prog; 977 } ld_prog; 978 979 struct { 980 struct mfi_evt_ld ld; 981 uint32_t prev_state; 982 uint32_t new_state; 983 } ld_state; 984 985 struct { 986 uint64_t strip; 987 struct mfi_evt_ld ld; 988 } ld_strip; 989 990 struct mfi_evt_pd pd; 991 992 struct { 993 struct mfi_evt_pd pd; 994 uint32_t err; 995 } pd_err; 996 997 struct { 998 uint64_t lba; 999 struct mfi_evt_pd pd; 1000 } pd_lba; 1001 1002 struct { 1003 uint64_t lba; 1004 struct mfi_evt_pd pd; 1005 struct mfi_evt_ld ld; 1006 } pd_lba_ld; 1007 1008 struct { 1009 struct mfi_evt_pd pd; 1010 struct mfi_progress prog; 1011 } pd_prog; 1012 1013 struct { 1014 struct mfi_evt_pd ld; 1015 uint32_t prev_state; 1016 uint32_t new_state; 1017 } pd_state; 1018 1019 struct { 1020 uint16_t venderId; 1021 uint16_t deviceId; 1022 uint16_t subVenderId; 1023 uint16_t subDeviceId; 1024 } pci; 1025 1026 uint32_t rate; 1027 1028 char str[96]; 1029 1030 struct { 1031 uint32_t rtc; 1032 uint16_t elapsedSeconds; 1033 } time; 1034 1035 struct { 1036 uint32_t ecar; 1037 uint32_t elog; 1038 char str[64]; 1039 } ecc; 1040 1041 uint8_t b[96]; 1042 uint16_t s[48]; 1043 uint32_t w[24]; 1044 uint64_t d[12]; 1045 } args; 1046 1047 char description[128]; 1048 } __packed; 1049 1050 struct mfi_evt_list { 1051 uint32_t count; 1052 uint32_t reserved; 1053 struct mfi_evt_detail event[1]; 1054 } __packed; 1055 1056 union mfi_pd_ref { 1057 struct { 1058 uint16_t device_id; 1059 uint16_t seq_num; 1060 } v; 1061 uint32_t ref; 1062 } __packed; 1063 1064 union mfi_pd_ddf_type { 1065 struct { 1066 union { 1067 struct { 1068 uint16_t forced_pd_guid : 1; 1069 uint16_t in_vd : 1; 1070 uint16_t is_global_spare : 1; 1071 uint16_t is_spare : 1; 1072 uint16_t is_foreign : 1; 1073 uint16_t reserved : 7; 1074 uint16_t intf : 4; 1075 } pd_type; 1076 uint16_t type; 1077 } v; 1078 uint16_t reserved; 1079 } ddf; 1080 struct { 1081 uint32_t reserved; 1082 } non_disk; 1083 uint32_t type; 1084 } __packed; 1085 1086 struct mfi_pd_progress { 1087 uint32_t active; 1088 #define MFI_PD_PROGRESS_REBUILD (1<<0) 1089 #define MFI_PD_PROGRESS_PATROL (1<<1) 1090 #define MFI_PD_PROGRESS_CLEAR (1<<2) 1091 struct mfi_progress rbld; 1092 struct mfi_progress patrol; 1093 struct mfi_progress clear; 1094 struct mfi_progress reserved[4]; 1095 } __packed; 1096 1097 struct mfi_pd_info { 1098 union mfi_pd_ref ref; 1099 uint8_t inquiry_data[96]; 1100 uint8_t vpd_page83[64]; 1101 uint8_t not_supported; 1102 uint8_t scsi_dev_type; 1103 uint8_t connected_port_bitmap; 1104 uint8_t device_speed; 1105 uint32_t media_err_count; 1106 uint32_t other_err_count; 1107 uint32_t pred_fail_count; 1108 uint32_t last_pred_fail_event_seq_num; 1109 uint16_t fw_state; /* MFI_PD_STATE_* */ 1110 uint8_t disabled_for_removal; 1111 uint8_t link_speed; 1112 union mfi_pd_ddf_type state; 1113 struct { 1114 uint8_t count; 1115 uint8_t is_path_broken; 1116 uint8_t reserved[6]; 1117 uint64_t sas_addr[4]; 1118 } path_info; 1119 uint64_t raw_size; 1120 uint64_t non_coerced_size; 1121 uint64_t coerced_size; 1122 uint16_t encl_device_id; 1123 uint8_t encl_index; 1124 uint8_t slot_number; 1125 struct mfi_pd_progress prog_info; 1126 uint8_t bad_block_table_full; 1127 uint8_t unusable_in_current_config; 1128 uint8_t vpd_page83_ext[64]; 1129 uint8_t reserved[512-358]; 1130 } __packed; 1131 1132 struct mfi_pd_address { 1133 uint16_t device_id; 1134 uint16_t encl_device_id; 1135 uint8_t encl_index; 1136 uint8_t slot_number; 1137 uint8_t scsi_dev_type; /* 0 = disk */ 1138 uint8_t connect_port_bitmap; 1139 uint64_t sas_addr[2]; 1140 } __packed; 1141 1142 #define MAX_SYS_PDS 240 1143 struct mfi_pd_list { 1144 uint32_t size; 1145 uint32_t count; 1146 struct mfi_pd_address addr[MAX_SYS_PDS]; 1147 } __packed; 1148 1149 enum mfi_pd_state { 1150 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1151 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1152 MFI_PD_STATE_HOT_SPARE = 0x02, 1153 MFI_PD_STATE_OFFLINE = 0x10, 1154 MFI_PD_STATE_FAILED = 0x11, 1155 MFI_PD_STATE_REBUILD = 0x14, 1156 MFI_PD_STATE_ONLINE = 0x18, 1157 MFI_PD_STATE_COPYBACK = 0x20, 1158 MFI_PD_STATE_SYSTEM = 0x40 1159 }; 1160 1161 /* 1162 * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1163 * Adding a #define to denote this. 1164 */ 1165 #define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1166 1167 union mfi_ld_ref { 1168 struct { 1169 uint8_t target_id; 1170 uint8_t reserved; 1171 uint16_t seq; 1172 } v; 1173 uint32_t ref; 1174 } __packed; 1175 1176 struct mfi_ld_list { 1177 uint32_t ld_count; 1178 uint32_t reserved1; 1179 struct { 1180 union mfi_ld_ref ld; 1181 uint8_t state; 1182 uint8_t reserved2[3]; 1183 uint64_t size; 1184 } ld_list[MFI_MAX_LD]; 1185 } __packed; 1186 1187 enum mfi_ld_access { 1188 MFI_LD_ACCESS_RW = 0, 1189 MFI_LD_ACCSSS_RO = 2, 1190 MFI_LD_ACCESS_BLOCKED = 3, 1191 }; 1192 #define MFI_LD_ACCESS_MASK 3 1193 1194 enum mfi_ld_state { 1195 MFI_LD_STATE_OFFLINE = 0, 1196 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1197 MFI_LD_STATE_DEGRADED = 2, 1198 MFI_LD_STATE_OPTIMAL = 3 1199 }; 1200 1201 struct mfi_ld_props { 1202 union mfi_ld_ref ld; 1203 char name[16]; 1204 uint8_t default_cache_policy; 1205 uint8_t access_policy; 1206 uint8_t disk_cache_policy; 1207 uint8_t current_cache_policy; 1208 uint8_t no_bgi; 1209 uint8_t reserved[7]; 1210 } __packed; 1211 1212 struct mfi_ld_params { 1213 uint8_t primary_raid_level; 1214 uint8_t raid_level_qualifier; 1215 uint8_t secondary_raid_level; 1216 uint8_t stripe_size; 1217 uint8_t num_drives; 1218 uint8_t span_depth; 1219 uint8_t state; 1220 uint8_t init_state; 1221 #define MFI_LD_PARAMS_INIT_NO 0 1222 #define MFI_LD_PARAMS_INIT_QUICK 1 1223 #define MFI_LD_PARAMS_INIT_FULL 2 1224 uint8_t is_consistent; 1225 uint8_t reserved1[6]; 1226 uint8_t isSSCD; 1227 uint8_t reserved2[16]; 1228 } __packed; 1229 1230 struct mfi_ld_progress { 1231 uint32_t active; 1232 #define MFI_LD_PROGRESS_CC (1<<0) 1233 #define MFI_LD_PROGRESS_BGI (1<<1) 1234 #define MFI_LD_PROGRESS_FGI (1<<2) 1235 #define MFI_LD_PROGRESS_RECON (1<<3) 1236 struct mfi_progress cc; 1237 struct mfi_progress bgi; 1238 struct mfi_progress fgi; 1239 struct mfi_progress recon; 1240 struct mfi_progress reserved[4]; 1241 } __packed; 1242 1243 struct mfi_span { 1244 uint64_t start_block; 1245 uint64_t num_blocks; 1246 uint16_t array_ref; 1247 uint8_t reserved[6]; 1248 } __packed; 1249 1250 #define MFI_MAX_SPAN_DEPTH 8 1251 struct mfi_ld_config { 1252 struct mfi_ld_props properties; 1253 struct mfi_ld_params params; 1254 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1255 } __packed; 1256 1257 struct mfi_ld_info { 1258 struct mfi_ld_config ld_config; 1259 uint64_t size; 1260 struct mfi_ld_progress progress; 1261 uint16_t cluster_owner; 1262 uint8_t reconstruct_active; 1263 uint8_t reserved1[1]; 1264 uint8_t vpd_page83[64]; 1265 uint8_t reserved2[16]; 1266 } __packed; 1267 1268 #define MFI_MAX_ARRAYS 16 1269 struct mfi_spare { 1270 union mfi_pd_ref ref; 1271 uint8_t spare_type; 1272 #define MFI_SPARE_DEDICATED (1 << 0) 1273 #define MFI_SPARE_REVERTIBLE (1 << 1) 1274 #define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1275 uint8_t reserved[2]; 1276 uint8_t array_count; 1277 uint16_t array_ref[MFI_MAX_ARRAYS]; 1278 } __packed; 1279 1280 #define MFI_MAX_ROW_SIZE 32 1281 struct mfi_array { 1282 uint64_t size; 1283 uint8_t num_drives; 1284 uint8_t reserved; 1285 uint16_t array_ref; 1286 uint8_t pad[20]; 1287 struct { 1288 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1289 uint16_t fw_state; /* MFI_PD_STATE_* */ 1290 struct { 1291 uint8_t pd; 1292 uint8_t slot; 1293 } encl; 1294 } pd[MFI_MAX_ROW_SIZE]; 1295 } __packed; 1296 1297 struct mfi_config_data { 1298 uint32_t size; 1299 uint16_t array_count; 1300 uint16_t array_size; 1301 uint16_t log_drv_count; 1302 uint16_t log_drv_size; 1303 uint16_t spares_count; 1304 uint16_t spares_size; 1305 uint8_t reserved[16]; 1306 struct mfi_array array[0]; 1307 struct mfi_ld_config ld[0]; 1308 struct mfi_spare spare[0]; 1309 } __packed; 1310 1311 struct mfi_bbu_capacity_info { 1312 uint16_t relative_charge; 1313 uint16_t absolute_charge; 1314 uint16_t remaining_capacity; 1315 uint16_t full_charge_capacity; 1316 uint16_t run_time_to_empty; 1317 uint16_t average_time_to_empty; 1318 uint16_t average_time_to_full; 1319 uint16_t cycle_count; 1320 uint16_t max_error; 1321 uint16_t remaining_capacity_alarm; 1322 uint16_t remaining_time_alarm; 1323 uint8_t reserved[26]; 1324 } __packed; 1325 1326 struct mfi_bbu_design_info { 1327 uint32_t mfg_date; 1328 uint16_t design_capacity; 1329 uint16_t design_voltage; 1330 uint16_t spec_info; 1331 uint16_t serial_number; 1332 uint16_t pack_stat_config; 1333 uint8_t mfg_name[12]; 1334 uint8_t device_name[8]; 1335 uint8_t device_chemistry[8]; 1336 uint8_t mfg_data[8]; 1337 uint8_t reserved[17]; 1338 } __packed; 1339 1340 struct mfi_ibbu_state { 1341 uint16_t gas_guage_status; 1342 uint16_t relative_charge; 1343 uint16_t charger_system_state; 1344 uint16_t charger_system_ctrl; 1345 uint16_t charging_current; 1346 uint16_t absolute_charge; 1347 uint16_t max_error; 1348 uint8_t reserved[18]; 1349 } __packed; 1350 1351 struct mfi_bbu_state { 1352 uint16_t gas_guage_status; 1353 uint16_t relative_charge; 1354 uint16_t charger_status; 1355 uint16_t remaining_capacity; 1356 uint16_t full_charge_capacity; 1357 uint8_t is_SOH_good; 1358 uint8_t reserved[21]; 1359 } __packed; 1360 1361 union mfi_bbu_status_detail { 1362 struct mfi_ibbu_state ibbu; 1363 struct mfi_bbu_state bbu; 1364 }; 1365 1366 struct mfi_bbu_status { 1367 uint8_t battery_type; 1368 #define MFI_BBU_TYPE_NONE 0 1369 #define MFI_BBU_TYPE_IBBU 1 1370 #define MFI_BBU_TYPE_BBU 2 1371 uint8_t reserved; 1372 uint16_t voltage; 1373 int16_t current; 1374 uint16_t temperature; 1375 uint32_t fw_status; 1376 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1377 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1378 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1379 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 0) 1380 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 0) 1381 uint8_t pad[20]; 1382 union mfi_bbu_status_detail detail; 1383 } __packed; 1384 1385 enum mfi_pr_state { 1386 MFI_PR_STATE_STOPPED = 0, 1387 MFI_PR_STATE_READY = 1, 1388 MFI_PR_STATE_ACTIVE = 2, 1389 MFI_PR_STATE_ABORTED = 0xff 1390 }; 1391 1392 struct mfi_pr_status { 1393 uint32_t num_iteration; 1394 uint8_t state; 1395 uint8_t num_pd_done; 1396 uint8_t reserved[10]; 1397 }; 1398 1399 enum mfi_pr_opmode { 1400 MFI_PR_OPMODE_AUTO = 0, 1401 MFI_PR_OPMODE_MANUAL = 1, 1402 MFI_PR_OPMODE_DISABLED = 2 1403 }; 1404 1405 struct mfi_pr_properties { 1406 uint8_t op_mode; 1407 uint8_t max_pd; 1408 uint8_t reserved; 1409 uint8_t exclude_ld_count; 1410 uint16_t excluded_ld[MFI_MAX_LD]; 1411 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1412 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1413 uint32_t next_exec; 1414 uint32_t exec_freq; 1415 uint32_t clear_freq; 1416 }; 1417 1418 /* ThunderBolt support */ 1419 1420 /* 1421 * Raid Context structure which describes MegaRAID specific IO Paramenters 1422 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1423 */ 1424 typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1425 uint16_t resvd0; /* 0x00 - 0x01 */ 1426 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1427 uint8_t regLockFlags; 1428 uint8_t armId; 1429 uint16_t TargetID; /* 0x06 - 0x07 */ 1430 1431 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1432 1433 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1434 1435 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1436 uint8_t exStatus; /* 0x16 */ 1437 uint8_t Status; /* 0x17 status */ 1438 1439 uint8_t RAIDFlags; /* 0x18 */ 1440 uint8_t numSGE; /* 0x19 numSge */ 1441 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1442 uint8_t spanArm; /* 0x1C */ 1443 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1444 } MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1445 1446 /***************************************************************************** 1447 * 1448 * Message Functions 1449 * 1450 *****************************************************************************/ 1451 1452 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1453 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1454 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1455 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1456 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1457 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1458 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1459 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1460 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1461 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1462 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1463 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1464 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1465 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1466 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1467 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1468 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1469 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1470 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1471 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1472 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1473 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1474 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1475 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1476 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1477 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1478 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1479 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1480 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1481 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1482 1483 /* Doorbell functions */ 1484 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1485 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1486 1487 /***************************************************************************** 1488 * 1489 * MPI Version Definitions 1490 * 1491 *****************************************************************************/ 1492 1493 #define MPI2_VERSION_MAJOR (0x02) 1494 #define MPI2_VERSION_MINOR (0x00) 1495 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1496 #define MPI2_VERSION_MAJOR_SHIFT (8) 1497 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1498 #define MPI2_VERSION_MINOR_SHIFT (0) 1499 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1500 MPI2_VERSION_MINOR) 1501 1502 #define MPI2_VERSION_02_00 (0x0200) 1503 1504 /* versioning for this MPI header set */ 1505 #define MPI2_HEADER_VERSION_UNIT (0x10) 1506 #define MPI2_HEADER_VERSION_DEV (0x00) 1507 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1508 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1509 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1510 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1511 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1512 MPI2_HEADER_VERSION_DEV) 1513 1514 1515 /* IOCInit Request message */ 1516 struct MPI2_IOC_INIT_REQUEST { 1517 uint8_t WhoInit; /* 0x00 */ 1518 uint8_t Reserved1; /* 0x01 */ 1519 uint8_t ChainOffset; /* 0x02 */ 1520 uint8_t Function; /* 0x03 */ 1521 uint16_t Reserved2; /* 0x04 */ 1522 uint8_t Reserved3; /* 0x06 */ 1523 uint8_t MsgFlags; /* 0x07 */ 1524 uint8_t VP_ID; /* 0x08 */ 1525 uint8_t VF_ID; /* 0x09 */ 1526 uint16_t Reserved4; /* 0x0A */ 1527 uint16_t MsgVersion; /* 0x0C */ 1528 uint16_t HeaderVersion; /* 0x0E */ 1529 uint32_t Reserved5; /* 0x10 */ 1530 uint16_t Reserved6; /* 0x14 */ 1531 uint8_t Reserved7; /* 0x16 */ 1532 uint8_t HostMSIxVectors; /* 0x17 */ 1533 uint16_t Reserved8; /* 0x18 */ 1534 uint16_t SystemRequestFrameSize; /* 0x1A */ 1535 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1536 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1537 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1538 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1539 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1540 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1541 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1542 uint64_t TimeStamp; /* 0x40 */ 1543 }; 1544 1545 /* WhoInit values */ 1546 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1547 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1548 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1549 #define MPI2_WHOINIT_PCI_PEER (0x03) 1550 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1551 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1552 1553 struct MPI2_SGE_CHAIN_UNION { 1554 uint16_t Length; 1555 uint8_t NextChainOffset; 1556 uint8_t Flags; 1557 union { 1558 uint32_t Address32; 1559 uint64_t Address64; 1560 } u; 1561 }; 1562 1563 struct MPI2_IEEE_SGE_SIMPLE32 { 1564 uint32_t Address; 1565 uint32_t FlagsLength; 1566 }; 1567 1568 struct MPI2_IEEE_SGE_SIMPLE64 { 1569 uint64_t Address; 1570 uint32_t Length; 1571 uint16_t Reserved1; 1572 uint8_t Reserved2; 1573 uint8_t Flags; 1574 }; 1575 1576 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1577 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1578 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1579 } MPI2_IEEE_SGE_SIMPLE_UNION; 1580 1581 typedef struct _MPI2_SGE_SIMPLE_UNION { 1582 uint32_t FlagsLength; 1583 union { 1584 uint32_t Address32; 1585 uint64_t Address64; 1586 } u; 1587 } MPI2_SGE_SIMPLE_UNION; 1588 1589 /**************************************************************************** 1590 * IEEE SGE field definitions and masks 1591 ****************************************************************************/ 1592 1593 /* Flags field bit definitions */ 1594 1595 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1596 1597 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1598 1599 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1600 1601 /* Element Type */ 1602 1603 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1604 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1605 1606 /* Data Location Address Space */ 1607 1608 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1609 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1610 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1611 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1612 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1613 1614 /* Address Size */ 1615 1616 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1617 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1618 1619 /*******************/ 1620 /* SCSI IO Control bits */ 1621 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1622 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1623 1624 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1625 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1626 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1627 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1628 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1629 1630 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1631 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1632 1633 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1634 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1635 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1636 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1637 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1638 1639 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1640 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1641 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1642 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1643 1644 /*******************/ 1645 1646 typedef struct { 1647 uint8_t CDB[20]; /* 0x00 */ 1648 uint32_t PrimaryReferenceTag; /* 0x14 */ 1649 uint16_t PrimaryApplicationTag; /* 0x18 */ 1650 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1651 uint32_t TransferLength; /* 0x1C */ 1652 } MPI2_SCSI_IO_CDB_EEDP32; 1653 1654 1655 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1656 struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1657 struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1658 } MPI2_IEEE_SGE_CHAIN_UNION; 1659 1660 typedef union _MPI2_SIMPLE_SGE_UNION { 1661 MPI2_SGE_SIMPLE_UNION MpiSimple; 1662 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1663 } MPI2_SIMPLE_SGE_UNION; 1664 1665 typedef union _MPI2_SGE_IO_UNION { 1666 MPI2_SGE_SIMPLE_UNION MpiSimple; 1667 struct MPI2_SGE_CHAIN_UNION MpiChain; 1668 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1669 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1670 } MPI2_SGE_IO_UNION; 1671 1672 typedef union { 1673 uint8_t CDB32[32]; 1674 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1675 MPI2_SGE_SIMPLE_UNION SGE; 1676 } MPI2_SCSI_IO_CDB_UNION; 1677 1678 1679 /* MPI 2.5 SGLs */ 1680 1681 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1682 1683 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1684 uint64_t Address; 1685 uint32_t Length; 1686 uint16_t Reserved1; 1687 uint8_t NextChainOffset; 1688 uint8_t Flags; 1689 } MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1690 1691 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1692 1693 1694 /********/ 1695 1696 /* 1697 * RAID SCSI IO Request Message 1698 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1699 */ 1700 struct mfi_mpi2_request_raid_scsi_io { 1701 uint16_t DevHandle; /* 0x00 */ 1702 uint8_t ChainOffset; /* 0x02 */ 1703 uint8_t Function; /* 0x03 */ 1704 uint16_t Reserved1; /* 0x04 */ 1705 uint8_t Reserved2; /* 0x06 */ 1706 uint8_t MsgFlags; /* 0x07 */ 1707 uint8_t VP_ID; /* 0x08 */ 1708 uint8_t VF_ID; /* 0x09 */ 1709 uint16_t Reserved3; /* 0x0A */ 1710 uint32_t SenseBufferLowAddress; /* 0x0C */ 1711 uint16_t SGLFlags; /* 0x10 */ 1712 uint8_t SenseBufferLength; /* 0x12 */ 1713 uint8_t Reserved4; /* 0x13 */ 1714 uint8_t SGLOffset0; /* 0x14 */ 1715 uint8_t SGLOffset1; /* 0x15 */ 1716 uint8_t SGLOffset2; /* 0x16 */ 1717 uint8_t SGLOffset3; /* 0x17 */ 1718 uint32_t SkipCount; /* 0x18 */ 1719 uint32_t DataLength; /* 0x1C */ 1720 uint32_t BidirectionalDataLength; /* 0x20 */ 1721 uint16_t IoFlags; /* 0x24 */ 1722 uint16_t EEDPFlags; /* 0x26 */ 1723 uint32_t EEDPBlockSize; /* 0x28 */ 1724 uint32_t SecondaryReferenceTag; /* 0x2C */ 1725 uint16_t SecondaryApplicationTag; /* 0x30 */ 1726 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1727 uint8_t LUN[8]; /* 0x34 */ 1728 uint32_t Control; /* 0x3C */ 1729 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1730 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1731 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1732 } __packed; 1733 1734 /* 1735 * MPT RAID MFA IO Descriptor. 1736 */ 1737 typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1738 uint32_t RequestFlags : 8; 1739 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1740 uint32_t MessageAddress2; /* bits 61:32 */ 1741 } MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1742 1743 struct mfi_mpi2_request_header { 1744 uint8_t RequestFlags; /* 0x00 */ 1745 uint8_t MSIxIndex; /* 0x01 */ 1746 uint16_t SMID; /* 0x02 */ 1747 uint16_t LMID; /* 0x04 */ 1748 }; 1749 1750 /* defines for the RequestFlags field */ 1751 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1752 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1753 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1754 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1755 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1756 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1757 1758 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1759 1760 struct mfi_mpi2_request_high_priority { 1761 struct mfi_mpi2_request_header header; 1762 uint16_t reserved; 1763 }; 1764 1765 struct mfi_mpi2_request_scsi_io { 1766 struct mfi_mpi2_request_header header; 1767 uint16_t scsi_io_dev_handle; 1768 }; 1769 1770 struct mfi_mpi2_request_scsi_target { 1771 struct mfi_mpi2_request_header header; 1772 uint16_t scsi_target_io_index; 1773 }; 1774 1775 /* Request Descriptors */ 1776 union mfi_mpi2_request_descriptor { 1777 struct mfi_mpi2_request_header header; 1778 struct mfi_mpi2_request_high_priority high_priority; 1779 struct mfi_mpi2_request_scsi_io scsi_io; 1780 struct mfi_mpi2_request_scsi_target scsi_target; 1781 uint64_t words; 1782 }; 1783 1784 1785 struct mfi_mpi2_reply_header { 1786 uint8_t ReplyFlags; /* 0x00 */ 1787 uint8_t MSIxIndex; /* 0x01 */ 1788 uint16_t SMID; /* 0x02 */ 1789 }; 1790 1791 /* defines for the ReplyFlags field */ 1792 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1793 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1794 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1795 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1796 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1797 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1798 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1799 1800 /* values for marking a reply descriptor as unused */ 1801 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1802 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1803 1804 struct mfi_mpi2_reply_default { 1805 struct mfi_mpi2_reply_header header; 1806 uint32_t DescriptorTypeDependent2; 1807 }; 1808 1809 struct mfi_mpi2_reply_address { 1810 struct mfi_mpi2_reply_header header; 1811 uint32_t ReplyFrameAddress; 1812 }; 1813 1814 struct mfi_mpi2_reply_scsi_io { 1815 struct mfi_mpi2_reply_header header; 1816 uint16_t TaskTag; /* 0x04 */ 1817 uint16_t Reserved1; /* 0x06 */ 1818 }; 1819 1820 struct mfi_mpi2_reply_target_assist { 1821 struct mfi_mpi2_reply_header header; 1822 uint8_t SequenceNumber; /* 0x04 */ 1823 uint8_t Reserved1; /* 0x04 */ 1824 uint16_t IoIndex; /* 0x06 */ 1825 }; 1826 1827 struct mfi_mpi2_reply_target_cmd_buffer { 1828 struct mfi_mpi2_reply_header header; 1829 uint8_t SequenceNumber; /* 0x04 */ 1830 uint8_t Flags; /* 0x04 */ 1831 uint16_t InitiatorDevHandle; /* 0x06 */ 1832 uint16_t IoIndex; /* 0x06 */ 1833 }; 1834 1835 struct mfi_mpi2_reply_raid_accel { 1836 struct mfi_mpi2_reply_header header; 1837 uint8_t SequenceNumber; /* 0x04 */ 1838 uint32_t Reserved; /* 0x04 */ 1839 }; 1840 1841 /* union of Reply Descriptors */ 1842 union mfi_mpi2_reply_descriptor { 1843 struct mfi_mpi2_reply_header header; 1844 struct mfi_mpi2_reply_scsi_io scsi_io; 1845 struct mfi_mpi2_reply_target_assist target_assist; 1846 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1847 struct mfi_mpi2_reply_raid_accel raid_accel; 1848 struct mfi_mpi2_reply_default reply_default; 1849 uint64_t words; 1850 }; 1851 1852 struct IO_REQUEST_INFO { 1853 uint64_t ldStartBlock; 1854 uint32_t numBlocks; 1855 uint16_t ldTgtId; 1856 uint8_t isRead; 1857 uint16_t devHandle; 1858 uint64_t pdBlock; 1859 uint8_t fpOkForIo; 1860 }; 1861 1862 #define MFI_SCSI_MAX_TARGETS 128 1863 #define MFI_SCSI_MAX_LUNS 8 1864 #define MFI_SCSI_INITIATOR_ID 255 1865 #define MFI_SCSI_MAX_CMDS 8 1866 #define MFI_SCSI_MAX_CDB_LEN 16 1867 1868 #endif /* _MFIREG_H */ 1869