1 /*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 /*- 27 * Copyright (c) 2007 LSI Corp. 28 * Copyright (c) 2007 Rajesh Prabhakaran. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53 #ifndef _MFIREG_H 54 #define _MFIREG_H 55 56 #include <sys/cdefs.h> 57 __FBSDID("$FreeBSD$"); 58 59 /* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. 66 */ 67 #define MEGAMFI_FRAME_SIZE 64 68 /* 69 * Start with the register set. All registers are 32 bits wide. 70 * The usual Intel IOP style setup. 71 */ 72 #define MFI_IMSG0 0x10 /* Inbound message 0 */ 73 #define MFI_IMSG1 0x14 /* Inbound message 1 */ 74 #define MFI_OMSG0 0x18 /* Outbound message 0 */ 75 #define MFI_OMSG1 0x1c /* Outbound message 1 */ 76 #define MFI_IDB 0x20 /* Inbound doorbell */ 77 #define MFI_ISTS 0x24 /* Inbound interrupt status */ 78 #define MFI_IMSK 0x28 /* Inbound interrupt mask */ 79 #define MFI_ODB 0x2c /* Outbound doorbell */ 80 #define MFI_OSTS 0x30 /* Outbound interrupt status */ 81 #define MFI_OMSK 0x34 /* Outbound interrupt mask */ 82 #define MFI_IQP 0x40 /* Inbound queue port */ 83 #define MFI_OQP 0x44 /* Outbound queue port */ 84 85 /* 86 * ThunderBolt specific Register 87 */ 88 89 #define MFI_RFPI 0x48 /* reply_free_post_host_index */ 90 #define MFI_RPI 0x6c /* reply_post_host_index */ 91 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 92 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 93 94 /* 95 * 1078 specific related register 96 */ 97 #define MFI_ODR0 0x9c /* outbound doorbell register0 */ 98 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 99 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 100 #define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ 101 #define MFI_RMI 0x2 /* reply message interrupt */ 102 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 103 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 104 105 /* OCR registers */ 106 #define MFI_WSR 0x004 /* write sequence register */ 107 #define MFI_HDR 0x008 /* host diagnostic register */ 108 #define MFI_RSR 0x3c3 /* Reset Status Register */ 109 110 /* 111 * GEN2 specific changes 112 */ 113 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 114 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ 115 116 /* 117 * skinny specific changes 118 */ 119 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 120 #define MFI_IQPL 0x000000c0 121 #define MFI_IQPH 0x000000c4 122 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */ 123 124 /* Bits for MFI_OSTS */ 125 #define MFI_OSTS_INTR_VALID 0x00000002 126 127 /* OCR specific flags */ 128 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002 129 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */ 130 131 /* 132 * Firmware state values. Found in OMSG0 during initialization. 133 */ 134 #define MFI_FWSTATE_MASK 0xf0000000 135 #define MFI_FWSTATE_UNDEFINED 0x00000000 136 #define MFI_FWSTATE_BB_INIT 0x10000000 137 #define MFI_FWSTATE_FW_INIT 0x40000000 138 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000 139 #define MFI_FWSTATE_FW_INIT_2 0x70000000 140 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000 141 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 142 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000 143 #define MFI_FWSTATE_READY 0xb0000000 144 #define MFI_FWSTATE_OPERATIONAL 0xc0000000 145 #define MFI_FWSTATE_FAULT 0xf0000000 146 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000 147 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff 148 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000 149 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000 150 #define MFI_RESET_REQUIRED 0x00000001 151 152 /* ThunderBolt Support */ 153 #define MFI_FWSTATE_TB_MASK 0xf0000000 154 #define MFI_FWSTATE_TB_RESET 0x00000000 155 #define MFI_FWSTATE_TB_READY 0x10000000 156 #define MFI_FWSTATE_TB_OPERATIONAL 0x20000000 157 #define MFI_FWSTATE_TB_FAULT 0x40000000 158 159 /* 160 * Control bits to drive the card to ready state. These go into the IDB 161 * register. 162 */ 163 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */ 164 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */ 165 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */ 166 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */ 167 #define MFI_FWINIT_HOTPLUG 0x00000010 168 169 /* ADP reset flags */ 170 #define MFI_STOP_ADP 0x00000020 171 #define MFI_ADP_RESET 0x00000040 172 #define DIAG_WRITE_ENABLE 0x00000080 173 #define DIAG_RESET_ADAPTER 0x00000004 174 175 /* MFI Commands */ 176 typedef enum { 177 MFI_CMD_INIT = 0x00, 178 MFI_CMD_LD_READ, 179 MFI_CMD_LD_WRITE, 180 MFI_CMD_LD_SCSI_IO, 181 MFI_CMD_PD_SCSI_IO, 182 MFI_CMD_DCMD, 183 MFI_CMD_ABORT, 184 MFI_CMD_SMP, 185 MFI_CMD_STP 186 } mfi_cmd_t; 187 188 /* Direct commands */ 189 typedef enum { 190 MFI_DCMD_CTRL_GETINFO = 0x01010000, 191 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100, 192 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 193 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 194 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 195 MFI_DCMD_CTRL_GET_PROPS = 0x01020100, 196 MFI_DCMD_CTRL_SET_PROPS = 0x01020200, 197 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 198 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 199 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 200 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, 201 MFI_DCMD_PR_GET_STATUS = 0x01070100, 202 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 203 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 204 MFI_DCMD_PR_START = 0x01070400, 205 MFI_DCMD_PR_STOP = 0x01070500, 206 MFI_DCMD_TIME_SECS_GET = 0x01080201, 207 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 208 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 209 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 210 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 211 MFI_DCMD_PD_GET_LIST = 0x02010000, 212 MFI_DCMD_PD_LIST_QUERY = 0x02010100, 213 MFI_DCMD_PD_GET_INFO = 0x02020000, 214 MFI_DCMD_PD_STATE_SET = 0x02030100, 215 MFI_DCMD_PD_REBUILD_START = 0x02040100, 216 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 217 MFI_DCMD_PD_CLEAR_START = 0x02050100, 218 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 219 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 220 MFI_DCMD_PD_LOCATE_START = 0x02070100, 221 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, 222 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101, 223 MFI_DCMD_LD_SYNC = 0x0300e102, 224 MFI_DCMD_LD_GET_LIST = 0x03010000, 225 MFI_DCMD_LD_GET_INFO = 0x03020000, 226 MFI_DCMD_LD_GET_PROP = 0x03030000, 227 MFI_DCMD_LD_SET_PROP = 0x03040000, 228 MFI_DCMD_LD_INIT_START = 0x03060100, 229 MFI_DCMD_LD_DELETE = 0x03090000, 230 MFI_DCMD_CFG_READ = 0x04010000, 231 MFI_DCMD_CFG_ADD = 0x04020000, 232 MFI_DCMD_CFG_CLEAR = 0x04030000, 233 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 234 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, 235 MFI_DCMD_CFG_FOREIGN_SCAN = 0x04060100, 236 MFI_DCMD_CFG_FOREIGN_DISPLAY = 0x04060200, 237 MFI_DCMD_CFG_FOREIGN_PREVIEW = 0x04060300, 238 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, 239 MFI_DCMD_CFG_FOREIGN_CLEAR = 0x04060500, 240 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 241 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 242 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, 243 MFI_DCMD_BBU_START_LEARN = 0x05040000, 244 MFI_DCMD_BBU_GET_PROP = 0x05050100, 245 MFI_DCMD_BBU_SET_PROP = 0x05050200, 246 MFI_DCMD_CLUSTER = 0x08000000, 247 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 248 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 249 } mfi_dcmd_t; 250 251 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 252 #define MFI_FLUSHCACHE_CTRL 0x01 253 #define MFI_FLUSHCACHE_DISK 0x02 254 255 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */ 256 #define MFI_SHUTDOWN_SPINDOWN 0x01 257 258 /* 259 * MFI Frame flags 260 */ 261 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 262 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 263 #define MFI_FRAME_SGL32 0x0000 264 #define MFI_FRAME_SGL64 0x0002 265 #define MFI_FRAME_SENSE32 0x0000 266 #define MFI_FRAME_SENSE64 0x0004 267 #define MFI_FRAME_DIR_NONE 0x0000 268 #define MFI_FRAME_DIR_WRITE 0x0008 269 #define MFI_FRAME_DIR_READ 0x0010 270 #define MFI_FRAME_DIR_BOTH 0x0018 271 #define MFI_FRAME_IEEE_SGL 0x0020 272 #define MFI_FRAME_FMT "\20" \ 273 "\1NOPOST" \ 274 "\2SGL64" \ 275 "\3SENSE64" \ 276 "\4WRITE" \ 277 "\5READ" \ 278 "\6IEEESGL" 279 280 /* ThunderBolt Specific */ 281 282 /* 283 * Pre-TB command size and TB command size. 284 * We will be checking it at the load time for the time being 285 */ 286 #define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 287 288 #define MEGASAS_THUNDERBOLT_MSG_ALLIGNMENT 256 289 /* 290 * We are defining only 128 byte message to reduce memory move over head 291 * and also it will reduce the SRB extension size by 128byte compared with 292 * 256 message size 293 */ 294 #define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 295 #define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 296 #define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 297 #define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 298 #define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 299 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 300 301 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 302 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 303 304 #define MR_INTERNAL_MFI_FRAMES_SMID 1 305 #define MR_CTRL_EVENT_WAIT_SMID 2 306 #define MR_INTERNAL_DRIVER_RESET_SMID 3 307 308 309 /* MFI Status codes */ 310 typedef enum { 311 MFI_STAT_OK = 0x00, 312 MFI_STAT_INVALID_CMD, 313 MFI_STAT_INVALID_DCMD, 314 MFI_STAT_INVALID_PARAMETER, 315 MFI_STAT_INVALID_SEQUENCE_NUMBER, 316 MFI_STAT_ABORT_NOT_POSSIBLE, 317 MFI_STAT_APP_HOST_CODE_NOT_FOUND, 318 MFI_STAT_APP_IN_USE, 319 MFI_STAT_APP_NOT_INITIALIZED, 320 MFI_STAT_ARRAY_INDEX_INVALID, 321 MFI_STAT_ARRAY_ROW_NOT_EMPTY, 322 MFI_STAT_CONFIG_RESOURCE_CONFLICT, 323 MFI_STAT_DEVICE_NOT_FOUND, 324 MFI_STAT_DRIVE_TOO_SMALL, 325 MFI_STAT_FLASH_ALLOC_FAIL, 326 MFI_STAT_FLASH_BUSY, 327 MFI_STAT_FLASH_ERROR = 0x10, 328 MFI_STAT_FLASH_IMAGE_BAD, 329 MFI_STAT_FLASH_IMAGE_INCOMPLETE, 330 MFI_STAT_FLASH_NOT_OPEN, 331 MFI_STAT_FLASH_NOT_STARTED, 332 MFI_STAT_FLUSH_FAILED, 333 MFI_STAT_HOST_CODE_NOT_FOUNT, 334 MFI_STAT_LD_CC_IN_PROGRESS, 335 MFI_STAT_LD_INIT_IN_PROGRESS, 336 MFI_STAT_LD_LBA_OUT_OF_RANGE, 337 MFI_STAT_LD_MAX_CONFIGURED, 338 MFI_STAT_LD_NOT_OPTIMAL, 339 MFI_STAT_LD_RBLD_IN_PROGRESS, 340 MFI_STAT_LD_RECON_IN_PROGRESS, 341 MFI_STAT_LD_WRONG_RAID_LEVEL, 342 MFI_STAT_MAX_SPARES_EXCEEDED, 343 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 344 MFI_STAT_MFC_HW_ERROR, 345 MFI_STAT_NO_HW_PRESENT, 346 MFI_STAT_NOT_FOUND, 347 MFI_STAT_NOT_IN_ENCL, 348 MFI_STAT_PD_CLEAR_IN_PROGRESS, 349 MFI_STAT_PD_TYPE_WRONG, 350 MFI_STAT_PR_DISABLED, 351 MFI_STAT_ROW_INDEX_INVALID, 352 MFI_STAT_SAS_CONFIG_INVALID_ACTION, 353 MFI_STAT_SAS_CONFIG_INVALID_DATA, 354 MFI_STAT_SAS_CONFIG_INVALID_PAGE, 355 MFI_STAT_SAS_CONFIG_INVALID_TYPE, 356 MFI_STAT_SCSI_DONE_WITH_ERROR, 357 MFI_STAT_SCSI_IO_FAILED, 358 MFI_STAT_SCSI_RESERVATION_CONFLICT, 359 MFI_STAT_SHUTDOWN_FAILED = 0x30, 360 MFI_STAT_TIME_NOT_SET, 361 MFI_STAT_WRONG_STATE, 362 MFI_STAT_LD_OFFLINE, 363 MFI_STAT_PEER_NOTIFICATION_REJECTED, 364 MFI_STAT_PEER_NOTIFICATION_FAILED, 365 MFI_STAT_RESERVATION_IN_PROGRESS, 366 MFI_STAT_I2C_ERRORS_DETECTED, 367 MFI_STAT_PCI_ERRORS_DETECTED, 368 MFI_STAT_DIAG_FAILED, 369 MFI_STAT_BOOT_MSG_PENDING, 370 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, 371 MFI_STAT_INVALID_STATUS = 0xFF 372 } mfi_status_t; 373 374 typedef enum { 375 MFI_EVT_CLASS_DEBUG = -2, 376 MFI_EVT_CLASS_PROGRESS = -1, 377 MFI_EVT_CLASS_INFO = 0, 378 MFI_EVT_CLASS_WARNING = 1, 379 MFI_EVT_CLASS_CRITICAL = 2, 380 MFI_EVT_CLASS_FATAL = 3, 381 MFI_EVT_CLASS_DEAD = 4 382 } mfi_evt_class_t; 383 384 typedef enum { 385 MFI_EVT_LOCALE_LD = 0x0001, 386 MFI_EVT_LOCALE_PD = 0x0002, 387 MFI_EVT_LOCALE_ENCL = 0x0004, 388 MFI_EVT_LOCALE_BBU = 0x0008, 389 MFI_EVT_LOCALE_SAS = 0x0010, 390 MFI_EVT_LOCALE_CTRL = 0x0020, 391 MFI_EVT_LOCALE_CONFIG = 0x0040, 392 MFI_EVT_LOCALE_CLUSTER = 0x0080, 393 MFI_EVT_LOCALE_ALL = 0xffff 394 } mfi_evt_locale_t; 395 396 typedef enum { 397 MR_EVT_ARGS_NONE = 0x00, 398 MR_EVT_ARGS_CDB_SENSE, 399 MR_EVT_ARGS_LD, 400 MR_EVT_ARGS_LD_COUNT, 401 MR_EVT_ARGS_LD_LBA, 402 MR_EVT_ARGS_LD_OWNER, 403 MR_EVT_ARGS_LD_LBA_PD_LBA, 404 MR_EVT_ARGS_LD_PROG, 405 MR_EVT_ARGS_LD_STATE, 406 MR_EVT_ARGS_LD_STRIP, 407 MR_EVT_ARGS_PD, 408 MR_EVT_ARGS_PD_ERR, 409 MR_EVT_ARGS_PD_LBA, 410 MR_EVT_ARGS_PD_LBA_LD, 411 MR_EVT_ARGS_PD_PROG, 412 MR_EVT_ARGS_PD_STATE, 413 MR_EVT_ARGS_PCI, 414 MR_EVT_ARGS_RATE, 415 MR_EVT_ARGS_STR, 416 MR_EVT_ARGS_TIME, 417 MR_EVT_ARGS_ECC 418 } mfi_evt_args; 419 420 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 421 #define MR_EVT_PD_REMOVED 0x0070 422 #define MR_EVT_PD_INSERTED 0x005b 423 #define MR_EVT_LD_CHANGE 0x0051 424 425 typedef enum { 426 MR_LD_CACHE_WRITE_BACK = 0x01, 427 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 428 MR_LD_CACHE_READ_AHEAD = 0x04, 429 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 430 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 431 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 432 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 433 } mfi_ld_cache; 434 #define MR_LD_CACHE_MASK 0x7f 435 436 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 437 #define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 438 #define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 439 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 440 #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 441 #define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 442 #define MR_LD_CACHE_POLICY_IO_CACHED \ 443 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 444 #define MR_LD_CACHE_POLICY_IO_DIRECT 0 445 446 typedef enum { 447 MR_PD_CACHE_UNCHANGED = 0, 448 MR_PD_CACHE_ENABLE = 1, 449 MR_PD_CACHE_DISABLE = 2 450 } mfi_pd_cache; 451 452 typedef enum { 453 MR_PD_QUERY_TYPE_ALL = 0, 454 MR_PD_QUERY_TYPE_STATE = 1, 455 MR_PD_QUERY_TYPE_POWER_STATE = 2, 456 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 457 MR_PD_QUERY_TYPE_SPEED = 4, 458 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 459 } mfi_pd_query_type; 460 461 /* 462 * Other propertities and definitions 463 */ 464 #define MFI_MAX_PD_CHANNELS 2 465 #define MFI_MAX_LD_CHANNELS 2 466 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 467 #define MFI_MAX_CHANNEL_DEVS 128 468 #define MFI_DEFAULT_ID -1 469 #define MFI_MAX_LUN 8 470 #define MFI_MAX_LD 64 471 #define MFI_MAX_PD 256 472 473 #define MFI_FRAME_SIZE 64 474 #define MFI_MBOX_SIZE 12 475 476 /* Firmware flashing can take 50+ seconds */ 477 #define MFI_POLL_TIMEOUT_SECS 60 478 479 /* Allow for speedier math calculations */ 480 #define MFI_SECTOR_LEN 512 481 482 /* Scatter Gather elements */ 483 struct mfi_sg32 { 484 uint32_t addr; 485 uint32_t len; 486 } __packed; 487 488 struct mfi_sg64 { 489 uint64_t addr; 490 uint32_t len; 491 } __packed; 492 493 struct mfi_sg_skinny { 494 uint64_t addr; 495 uint32_t len; 496 uint32_t flag; 497 } __packed; 498 499 union mfi_sgl { 500 struct mfi_sg32 sg32[1]; 501 struct mfi_sg64 sg64[1]; 502 struct mfi_sg_skinny sg_skinny[1]; 503 } __packed; 504 505 /* Message frames. All messages have a common header */ 506 struct mfi_frame_header { 507 uint8_t cmd; 508 uint8_t sense_len; 509 uint8_t cmd_status; 510 uint8_t scsi_status; 511 uint8_t target_id; 512 uint8_t lun_id; 513 uint8_t cdb_len; 514 uint8_t sg_count; 515 uint32_t context; 516 /* 517 * pad0 is MSI Specific. Not used by Driver. Zero the value before 518 * sending the command to f/w. 519 */ 520 uint32_t pad0; 521 uint16_t flags; 522 #define MFI_FRAME_DATAOUT 0x08 523 #define MFI_FRAME_DATAIN 0x10 524 uint16_t timeout; 525 uint32_t data_len; 526 } __packed; 527 528 struct mfi_init_frame { 529 struct mfi_frame_header header; 530 uint32_t qinfo_new_addr_lo; 531 uint32_t qinfo_new_addr_hi; 532 uint32_t qinfo_old_addr_lo; 533 uint32_t qinfo_old_addr_hi; 534 // Start LSIP200113393 535 uint32_t driver_ver_lo; /*28h */ 536 uint32_t driver_ver_hi; /*2Ch */ 537 538 uint32_t reserved[4]; 539 // End LSIP200113393 540 } __packed; 541 542 /* 543 * Define MFI Address Context union. 544 */ 545 #ifdef MFI_ADDRESS_IS_uint64_t 546 typedef uint64_t MFI_ADDRESS; 547 #else 548 typedef union _MFI_ADDRESS { 549 struct { 550 uint32_t addressLow; 551 uint32_t addressHigh; 552 } u; 553 uint64_t address; 554 } MFI_ADDRESS, *PMFI_ADDRESS; 555 #endif 556 557 #define MFI_IO_FRAME_SIZE 40 558 struct mfi_io_frame { 559 struct mfi_frame_header header; 560 uint32_t sense_addr_lo; 561 uint32_t sense_addr_hi; 562 uint32_t lba_lo; 563 uint32_t lba_hi; 564 union mfi_sgl sgl; 565 } __packed; 566 567 #define MFI_PASS_FRAME_SIZE 48 568 struct mfi_pass_frame { 569 struct mfi_frame_header header; 570 uint32_t sense_addr_lo; 571 uint32_t sense_addr_hi; 572 uint8_t cdb[16]; 573 union mfi_sgl sgl; 574 } __packed; 575 576 #define MFI_DCMD_FRAME_SIZE 40 577 struct mfi_dcmd_frame { 578 struct mfi_frame_header header; 579 uint32_t opcode; 580 uint8_t mbox[MFI_MBOX_SIZE]; 581 union mfi_sgl sgl; 582 } __packed; 583 584 struct mfi_abort_frame { 585 struct mfi_frame_header header; 586 uint32_t abort_context; 587 /* pad is changed to reserved.*/ 588 uint32_t reserved0; 589 uint32_t abort_mfi_addr_lo; 590 uint32_t abort_mfi_addr_hi; 591 uint32_t reserved1[6]; 592 } __packed; 593 594 struct mfi_smp_frame { 595 struct mfi_frame_header header; 596 uint64_t sas_addr; 597 union { 598 struct mfi_sg32 sg32[2]; 599 struct mfi_sg64 sg64[2]; 600 } sgl; 601 } __packed; 602 603 struct mfi_stp_frame { 604 struct mfi_frame_header header; 605 uint16_t fis[10]; 606 uint32_t stp_flags; 607 union { 608 struct mfi_sg32 sg32[2]; 609 struct mfi_sg64 sg64[2]; 610 } sgl; 611 } __packed; 612 613 union mfi_frame { 614 struct mfi_frame_header header; 615 struct mfi_init_frame init; 616 /* ThunderBolt Initialization */ 617 struct mfi_io_frame io; 618 struct mfi_pass_frame pass; 619 struct mfi_dcmd_frame dcmd; 620 struct mfi_abort_frame abort; 621 struct mfi_smp_frame smp; 622 struct mfi_stp_frame stp; 623 uint8_t bytes[MFI_FRAME_SIZE]; 624 }; 625 626 #define MFI_SENSE_LEN 128 627 struct mfi_sense { 628 uint8_t data[MFI_SENSE_LEN]; 629 }; 630 631 /* The queue init structure that is passed with the init message */ 632 struct mfi_init_qinfo { 633 uint32_t flags; 634 uint32_t rq_entries; 635 uint32_t rq_addr_lo; 636 uint32_t rq_addr_hi; 637 uint32_t pi_addr_lo; 638 uint32_t pi_addr_hi; 639 uint32_t ci_addr_lo; 640 uint32_t ci_addr_hi; 641 } __packed; 642 643 /* SAS (?) controller properties, part of mfi_ctrl_info */ 644 struct mfi_ctrl_props { 645 uint16_t seq_num; 646 uint16_t pred_fail_poll_interval; 647 uint16_t intr_throttle_cnt; 648 uint16_t intr_throttle_timeout; 649 uint8_t rebuild_rate; 650 uint8_t patrol_read_rate; 651 uint8_t bgi_rate; 652 uint8_t cc_rate; 653 uint8_t recon_rate; 654 uint8_t cache_flush_interval; 655 uint8_t spinup_drv_cnt; 656 uint8_t spinup_delay; 657 uint8_t cluster_enable; 658 uint8_t coercion_mode; 659 uint8_t alarm_enable; 660 uint8_t disable_auto_rebuild; 661 uint8_t disable_battery_warn; 662 uint8_t ecc_bucket_size; 663 uint16_t ecc_bucket_leak_rate; 664 uint8_t restore_hotspare_on_insertion; 665 uint8_t expose_encl_devices; 666 uint8_t maintainPdFailHistory; 667 uint8_t disallowHostRequestReordering; 668 /* set TRUE to abort CC on detecting an inconsistency */ 669 uint8_t abortCCOnError; 670 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 671 uint8_t loadBalanceMode; 672 /* 673 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 674 * h/w mechansim like GPIO pins 675 * 1 - disable auto detect SGPIO, 676 * 2 - disable i2c SEP auto detect 677 * 3 - disable both auto detect 678 */ 679 uint8_t disableAutoDetectBackplane; 680 /* 681 * % of source LD to be reserved for a VDs snapshot in snapshot 682 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 683 */ 684 uint8_t snapVDSpace; 685 686 /* 687 * Add properties that can be controlled by a bit in the following 688 * structure. 689 */ 690 struct { 691 /* set TRUE to disable copyBack (0=copback enabled) */ 692 uint32_t copyBackDisabled :1; 693 uint32_t SMARTerEnabled :1; 694 uint32_t prCorrectUnconfiguredAreas :1; 695 uint32_t useFdeOnly :1; 696 uint32_t disableNCQ :1; 697 uint32_t SSDSMARTerEnabled :1; 698 uint32_t SSDPatrolReadEnabled :1; 699 uint32_t enableSpinDownUnconfigured :1; 700 uint32_t autoEnhancedImport :1; 701 uint32_t enableSecretKeyControl :1; 702 uint32_t disableOnlineCtrlReset :1; 703 uint32_t allowBootWithPinnedCache :1; 704 uint32_t disableSpinDownHS :1; 705 uint32_t enableJBOD :1; 706 uint32_t reserved :18; 707 } OnOffProperties; 708 /* 709 * % of source LD to be reserved for auto snapshot in snapshot 710 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on. 711 */ 712 uint8_t autoSnapVDSpace; 713 /* 714 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 715 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 716 */ 717 uint8_t viewSpace; 718 /* # of idle minutes before device is spun down (0=use FW defaults) */ 719 uint16_t spinDownTime; 720 uint8_t reserved[24]; 721 } __packed; 722 723 /* PCI information about the card. */ 724 struct mfi_info_pci { 725 uint16_t vendor; 726 uint16_t device; 727 uint16_t subvendor; 728 uint16_t subdevice; 729 uint8_t reserved[24]; 730 } __packed; 731 732 /* Host (front end) interface information */ 733 struct mfi_info_host { 734 uint8_t type; 735 #define MFI_INFO_HOST_PCIX 0x01 736 #define MFI_INFO_HOST_PCIE 0x02 737 #define MFI_INFO_HOST_ISCSI 0x04 738 #define MFI_INFO_HOST_SAS3G 0x08 739 uint8_t reserved[6]; 740 uint8_t port_count; 741 uint64_t port_addr[8]; 742 } __packed; 743 744 /* Device (back end) interface information */ 745 struct mfi_info_device { 746 uint8_t type; 747 #define MFI_INFO_DEV_SPI 0x01 748 #define MFI_INFO_DEV_SAS3G 0x02 749 #define MFI_INFO_DEV_SATA1 0x04 750 #define MFI_INFO_DEV_SATA3G 0x08 751 uint8_t reserved[6]; 752 uint8_t port_count; 753 uint64_t port_addr[8]; 754 } __packed; 755 756 /* Firmware component information */ 757 struct mfi_info_component { 758 char name[8]; 759 char version[32]; 760 char build_date[16]; 761 char build_time[16]; 762 } __packed; 763 764 /* Controller default settings */ 765 struct mfi_defaults { 766 uint64_t sas_addr; 767 uint8_t phy_polarity; 768 uint8_t background_rate; 769 uint8_t stripe_size; 770 uint8_t flush_time; 771 uint8_t write_back; 772 uint8_t read_ahead; 773 uint8_t cache_when_bbu_bad; 774 uint8_t cached_io; 775 uint8_t smart_mode; 776 uint8_t alarm_disable; 777 uint8_t coercion; 778 uint8_t zrc_config; 779 uint8_t dirty_led_shows_drive_activity; 780 uint8_t bios_continue_on_error; 781 uint8_t spindown_mode; 782 uint8_t allowed_device_types; 783 uint8_t allow_mix_in_enclosure; 784 uint8_t allow_mix_in_ld; 785 uint8_t allow_sata_in_cluster; 786 uint8_t max_chained_enclosures; 787 uint8_t disable_ctrl_r; 788 uint8_t enabel_web_bios; 789 uint8_t phy_polarity_split; 790 uint8_t direct_pd_mapping; 791 uint8_t bios_enumerate_lds; 792 uint8_t restored_hot_spare_on_insertion; 793 uint8_t expose_enclosure_devices; 794 uint8_t maintain_pd_fail_history; 795 uint8_t resv[28]; 796 } __packed; 797 798 /* Controller default settings */ 799 struct mfi_bios_data { 800 uint16_t boot_target_id; 801 uint8_t do_not_int_13; 802 uint8_t continue_on_error; 803 uint8_t verbose; 804 uint8_t geometry; 805 uint8_t expose_all_drives; 806 uint8_t reserved[56]; 807 uint8_t check_sum; 808 } __packed; 809 810 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */ 811 struct mfi_ctrl_info { 812 struct mfi_info_pci pci; 813 struct mfi_info_host host; 814 struct mfi_info_device device; 815 816 /* Firmware components that are present and active. */ 817 uint32_t image_check_word; 818 uint32_t image_component_count; 819 struct mfi_info_component image_component[8]; 820 821 /* Firmware components that have been flashed but are inactive */ 822 uint32_t pending_image_component_count; 823 struct mfi_info_component pending_image_component[8]; 824 825 uint8_t max_arms; 826 uint8_t max_spans; 827 uint8_t max_arrays; 828 uint8_t max_lds; 829 char product_name[80]; 830 char serial_number[32]; 831 uint32_t hw_present; 832 #define MFI_INFO_HW_BBU 0x01 833 #define MFI_INFO_HW_ALARM 0x02 834 #define MFI_INFO_HW_NVRAM 0x04 835 #define MFI_INFO_HW_UART 0x08 836 uint32_t current_fw_time; 837 uint16_t max_cmds; 838 uint16_t max_sg_elements; 839 uint32_t max_request_size; 840 uint16_t lds_present; 841 uint16_t lds_degraded; 842 uint16_t lds_offline; 843 uint16_t pd_present; 844 uint16_t pd_disks_present; 845 uint16_t pd_disks_pred_failure; 846 uint16_t pd_disks_failed; 847 uint16_t nvram_size; 848 uint16_t memory_size; 849 uint16_t flash_size; 850 uint16_t ram_correctable_errors; 851 uint16_t ram_uncorrectable_errors; 852 uint8_t cluster_allowed; 853 uint8_t cluster_active; 854 uint16_t max_strips_per_io; 855 856 uint32_t raid_levels; 857 #define MFI_INFO_RAID_0 0x01 858 #define MFI_INFO_RAID_1 0x02 859 #define MFI_INFO_RAID_5 0x04 860 #define MFI_INFO_RAID_1E 0x08 861 #define MFI_INFO_RAID_6 0x10 862 863 uint32_t adapter_ops; 864 #define MFI_INFO_AOPS_RBLD_RATE 0x0001 865 #define MFI_INFO_AOPS_CC_RATE 0x0002 866 #define MFI_INFO_AOPS_BGI_RATE 0x0004 867 #define MFI_INFO_AOPS_RECON_RATE 0x0008 868 #define MFI_INFO_AOPS_PATROL_RATE 0x0010 869 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 870 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 871 #define MFI_INFO_AOPS_BBU 0x0080 872 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 873 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 874 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 875 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 876 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 877 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 878 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 879 880 uint32_t ld_ops; 881 #define MFI_INFO_LDOPS_READ_POLICY 0x01 882 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02 883 #define MFI_INFO_LDOPS_IO_POLICY 0x04 884 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 885 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 886 887 struct { 888 uint8_t min; 889 uint8_t max; 890 uint8_t reserved[2]; 891 } __packed stripe_sz_ops; 892 893 uint32_t pd_ops; 894 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 895 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 896 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 897 898 uint32_t pd_mix_support; 899 #define MFI_INFO_PDMIX_SAS 0x01 900 #define MFI_INFO_PDMIX_SATA 0x02 901 #define MFI_INFO_PDMIX_ENCL 0x04 902 #define MFI_INFO_PDMIX_LD 0x08 903 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 904 905 uint8_t ecc_bucket_count; 906 uint8_t reserved2[11]; 907 struct mfi_ctrl_props properties; 908 char package_version[0x60]; 909 uint8_t pad[0x800 - 0x6a0]; 910 } __packed; 911 912 /* keep track of an event. */ 913 union mfi_evt { 914 struct { 915 uint16_t locale; 916 uint8_t reserved; 917 int8_t evt_class; 918 } members; 919 uint32_t word; 920 } __packed; 921 922 /* event log state. */ 923 struct mfi_evt_log_state { 924 uint32_t newest_seq_num; 925 uint32_t oldest_seq_num; 926 uint32_t clear_seq_num; 927 uint32_t shutdown_seq_num; 928 uint32_t boot_seq_num; 929 } __packed; 930 931 struct mfi_progress { 932 uint16_t progress; 933 uint16_t elapsed_seconds; 934 } __packed; 935 936 struct mfi_evt_ld { 937 uint16_t target_id; 938 uint8_t ld_index; 939 uint8_t reserved; 940 } __packed; 941 942 struct mfi_evt_pd { 943 uint16_t device_id; 944 uint8_t enclosure_index; 945 uint8_t slot_number; 946 } __packed; 947 948 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */ 949 struct mfi_evt_detail { 950 uint32_t seq; 951 uint32_t time; 952 uint32_t code; 953 union mfi_evt evt_class; 954 uint8_t arg_type; 955 uint8_t reserved1[15]; 956 957 union { 958 struct { 959 struct mfi_evt_pd pd; 960 uint8_t cdb_len; 961 uint8_t sense_len; 962 uint8_t reserved[2]; 963 uint8_t cdb[16]; 964 uint8_t sense[64]; 965 } cdb_sense; 966 967 struct mfi_evt_ld ld; 968 969 struct { 970 struct mfi_evt_ld ld; 971 uint64_t count; 972 } ld_count; 973 974 struct { 975 uint64_t lba; 976 struct mfi_evt_ld ld; 977 } ld_lba; 978 979 struct { 980 struct mfi_evt_ld ld; 981 uint32_t pre_owner; 982 uint32_t new_owner; 983 } ld_owner; 984 985 struct { 986 uint64_t ld_lba; 987 uint64_t pd_lba; 988 struct mfi_evt_ld ld; 989 struct mfi_evt_pd pd; 990 } ld_lba_pd_lba; 991 992 struct { 993 struct mfi_evt_ld ld; 994 struct mfi_progress prog; 995 } ld_prog; 996 997 struct { 998 struct mfi_evt_ld ld; 999 uint32_t prev_state; 1000 uint32_t new_state; 1001 } ld_state; 1002 1003 struct { 1004 uint64_t strip; 1005 struct mfi_evt_ld ld; 1006 } ld_strip; 1007 1008 struct mfi_evt_pd pd; 1009 1010 struct { 1011 struct mfi_evt_pd pd; 1012 uint32_t err; 1013 } pd_err; 1014 1015 struct { 1016 uint64_t lba; 1017 struct mfi_evt_pd pd; 1018 } pd_lba; 1019 1020 struct { 1021 uint64_t lba; 1022 struct mfi_evt_pd pd; 1023 struct mfi_evt_ld ld; 1024 } pd_lba_ld; 1025 1026 struct { 1027 struct mfi_evt_pd pd; 1028 struct mfi_progress prog; 1029 } pd_prog; 1030 1031 struct { 1032 struct mfi_evt_pd ld; 1033 uint32_t prev_state; 1034 uint32_t new_state; 1035 } pd_state; 1036 1037 struct { 1038 uint16_t venderId; 1039 uint16_t deviceId; 1040 uint16_t subVenderId; 1041 uint16_t subDeviceId; 1042 } pci; 1043 1044 uint32_t rate; 1045 1046 char str[96]; 1047 1048 struct { 1049 uint32_t rtc; 1050 uint16_t elapsedSeconds; 1051 } time; 1052 1053 struct { 1054 uint32_t ecar; 1055 uint32_t elog; 1056 char str[64]; 1057 } ecc; 1058 1059 uint8_t b[96]; 1060 uint16_t s[48]; 1061 uint32_t w[24]; 1062 uint64_t d[12]; 1063 } args; 1064 1065 char description[128]; 1066 } __packed; 1067 1068 struct mfi_evt_list { 1069 uint32_t count; 1070 uint32_t reserved; 1071 struct mfi_evt_detail event[1]; 1072 } __packed; 1073 1074 union mfi_pd_ref { 1075 struct { 1076 uint16_t device_id; 1077 uint16_t seq_num; 1078 } v; 1079 uint32_t ref; 1080 } __packed; 1081 1082 union mfi_pd_ddf_type { 1083 struct { 1084 union { 1085 struct { 1086 uint16_t forced_pd_guid : 1; 1087 uint16_t in_vd : 1; 1088 uint16_t is_global_spare : 1; 1089 uint16_t is_spare : 1; 1090 uint16_t is_foreign : 1; 1091 uint16_t reserved : 7; 1092 uint16_t intf : 4; 1093 } pd_type; 1094 uint16_t type; 1095 } v; 1096 uint16_t reserved; 1097 } ddf; 1098 struct { 1099 uint32_t reserved; 1100 } non_disk; 1101 uint32_t type; 1102 } __packed; 1103 1104 struct mfi_pd_progress { 1105 uint32_t active; 1106 #define MFI_PD_PROGRESS_REBUILD (1<<0) 1107 #define MFI_PD_PROGRESS_PATROL (1<<1) 1108 #define MFI_PD_PROGRESS_CLEAR (1<<2) 1109 struct mfi_progress rbld; 1110 struct mfi_progress patrol; 1111 struct mfi_progress clear; 1112 struct mfi_progress reserved[4]; 1113 } __packed; 1114 1115 struct mfi_pd_info { 1116 union mfi_pd_ref ref; 1117 uint8_t inquiry_data[96]; 1118 uint8_t vpd_page83[64]; 1119 uint8_t not_supported; 1120 uint8_t scsi_dev_type; 1121 uint8_t connected_port_bitmap; 1122 uint8_t device_speed; 1123 uint32_t media_err_count; 1124 uint32_t other_err_count; 1125 uint32_t pred_fail_count; 1126 uint32_t last_pred_fail_event_seq_num; 1127 uint16_t fw_state; /* MFI_PD_STATE_* */ 1128 uint8_t disabled_for_removal; 1129 uint8_t link_speed; 1130 union mfi_pd_ddf_type state; 1131 struct { 1132 uint8_t count; 1133 uint8_t is_path_broken; 1134 uint8_t reserved[6]; 1135 uint64_t sas_addr[4]; 1136 } path_info; 1137 uint64_t raw_size; 1138 uint64_t non_coerced_size; 1139 uint64_t coerced_size; 1140 uint16_t encl_device_id; 1141 uint8_t encl_index; 1142 uint8_t slot_number; 1143 struct mfi_pd_progress prog_info; 1144 uint8_t bad_block_table_full; 1145 uint8_t unusable_in_current_config; 1146 uint8_t vpd_page83_ext[64]; 1147 uint8_t reserved[512-358]; 1148 } __packed; 1149 1150 struct mfi_pd_address { 1151 uint16_t device_id; 1152 uint16_t encl_device_id; 1153 uint8_t encl_index; 1154 uint8_t slot_number; 1155 uint8_t scsi_dev_type; /* 0 = disk */ 1156 uint8_t connect_port_bitmap; 1157 uint64_t sas_addr[2]; 1158 } __packed; 1159 1160 #define MAX_SYS_PDS 240 1161 struct mfi_pd_list { 1162 uint32_t size; 1163 uint32_t count; 1164 struct mfi_pd_address addr[MAX_SYS_PDS]; 1165 } __packed; 1166 1167 enum mfi_pd_state { 1168 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1169 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 1170 MFI_PD_STATE_HOT_SPARE = 0x02, 1171 MFI_PD_STATE_OFFLINE = 0x10, 1172 MFI_PD_STATE_FAILED = 0x11, 1173 MFI_PD_STATE_REBUILD = 0x14, 1174 MFI_PD_STATE_ONLINE = 0x18, 1175 MFI_PD_STATE_COPYBACK = 0x20, 1176 MFI_PD_STATE_SYSTEM = 0x40 1177 }; 1178 1179 /* 1180 * "SYSTEM" disk appears to be "JBOD" support from the RAID controller. 1181 * Adding a #define to denote this. 1182 */ 1183 #define MFI_PD_STATE_JBOD MFI_PD_STATE_SYSTEM 1184 1185 union mfi_ld_ref { 1186 struct { 1187 uint8_t target_id; 1188 uint8_t reserved; 1189 uint16_t seq; 1190 } v; 1191 uint32_t ref; 1192 } __packed; 1193 1194 struct mfi_ld_list { 1195 uint32_t ld_count; 1196 uint32_t reserved1; 1197 struct { 1198 union mfi_ld_ref ld; 1199 uint8_t state; 1200 uint8_t reserved2[3]; 1201 uint64_t size; 1202 } ld_list[MFI_MAX_LD]; 1203 } __packed; 1204 1205 enum mfi_ld_access { 1206 MFI_LD_ACCESS_RW = 0, 1207 MFI_LD_ACCSSS_RO = 2, 1208 MFI_LD_ACCESS_BLOCKED = 3, 1209 }; 1210 #define MFI_LD_ACCESS_MASK 3 1211 1212 enum mfi_ld_state { 1213 MFI_LD_STATE_OFFLINE = 0, 1214 MFI_LD_STATE_PARTIALLY_DEGRADED = 1, 1215 MFI_LD_STATE_DEGRADED = 2, 1216 MFI_LD_STATE_OPTIMAL = 3 1217 }; 1218 1219 struct mfi_ld_props { 1220 union mfi_ld_ref ld; 1221 char name[16]; 1222 uint8_t default_cache_policy; 1223 uint8_t access_policy; 1224 uint8_t disk_cache_policy; 1225 uint8_t current_cache_policy; 1226 uint8_t no_bgi; 1227 uint8_t reserved[7]; 1228 } __packed; 1229 1230 struct mfi_ld_params { 1231 uint8_t primary_raid_level; 1232 uint8_t raid_level_qualifier; 1233 uint8_t secondary_raid_level; 1234 uint8_t stripe_size; 1235 uint8_t num_drives; 1236 uint8_t span_depth; 1237 uint8_t state; 1238 uint8_t init_state; 1239 #define MFI_LD_PARAMS_INIT_NO 0 1240 #define MFI_LD_PARAMS_INIT_QUICK 1 1241 #define MFI_LD_PARAMS_INIT_FULL 2 1242 uint8_t is_consistent; 1243 uint8_t reserved1[6]; 1244 uint8_t isSSCD; 1245 uint8_t reserved2[16]; 1246 } __packed; 1247 1248 struct mfi_ld_progress { 1249 uint32_t active; 1250 #define MFI_LD_PROGRESS_CC (1<<0) 1251 #define MFI_LD_PROGRESS_BGI (1<<1) 1252 #define MFI_LD_PROGRESS_FGI (1<<2) 1253 #define MFI_LD_PROGRESS_RECON (1<<3) 1254 struct mfi_progress cc; 1255 struct mfi_progress bgi; 1256 struct mfi_progress fgi; 1257 struct mfi_progress recon; 1258 struct mfi_progress reserved[4]; 1259 } __packed; 1260 1261 struct mfi_span { 1262 uint64_t start_block; 1263 uint64_t num_blocks; 1264 uint16_t array_ref; 1265 uint8_t reserved[6]; 1266 } __packed; 1267 1268 #define MFI_MAX_SPAN_DEPTH 8 1269 struct mfi_ld_config { 1270 struct mfi_ld_props properties; 1271 struct mfi_ld_params params; 1272 struct mfi_span span[MFI_MAX_SPAN_DEPTH]; 1273 } __packed; 1274 1275 struct mfi_ld_info { 1276 struct mfi_ld_config ld_config; 1277 uint64_t size; 1278 struct mfi_ld_progress progress; 1279 uint16_t cluster_owner; 1280 uint8_t reconstruct_active; 1281 uint8_t reserved1[1]; 1282 uint8_t vpd_page83[64]; 1283 uint8_t reserved2[16]; 1284 } __packed; 1285 1286 #define MFI_MAX_ARRAYS 16 1287 struct mfi_spare { 1288 union mfi_pd_ref ref; 1289 uint8_t spare_type; 1290 #define MFI_SPARE_DEDICATED (1 << 0) 1291 #define MFI_SPARE_REVERTIBLE (1 << 1) 1292 #define MFI_SPARE_ENCL_AFFINITY (1 << 2) 1293 uint8_t reserved[2]; 1294 uint8_t array_count; 1295 uint16_t array_ref[MFI_MAX_ARRAYS]; 1296 } __packed; 1297 1298 #define MFI_MAX_ROW_SIZE 32 1299 struct mfi_array { 1300 uint64_t size; 1301 uint8_t num_drives; 1302 uint8_t reserved; 1303 uint16_t array_ref; 1304 uint8_t pad[20]; 1305 struct { 1306 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1307 uint16_t fw_state; /* MFI_PD_STATE_* */ 1308 struct { 1309 uint8_t pd; 1310 uint8_t slot; 1311 } encl; 1312 } pd[MFI_MAX_ROW_SIZE]; 1313 } __packed; 1314 1315 struct mfi_config_data { 1316 uint32_t size; 1317 uint16_t array_count; 1318 uint16_t array_size; 1319 uint16_t log_drv_count; 1320 uint16_t log_drv_size; 1321 uint16_t spares_count; 1322 uint16_t spares_size; 1323 uint8_t reserved[16]; 1324 struct mfi_array array[0]; 1325 struct mfi_ld_config ld[0]; 1326 struct mfi_spare spare[0]; 1327 } __packed; 1328 1329 struct mfi_bbu_capacity_info { 1330 uint16_t relative_charge; 1331 uint16_t absolute_charge; 1332 uint16_t remaining_capacity; 1333 uint16_t full_charge_capacity; 1334 uint16_t run_time_to_empty; 1335 uint16_t average_time_to_empty; 1336 uint16_t average_time_to_full; 1337 uint16_t cycle_count; 1338 uint16_t max_error; 1339 uint16_t remaining_capacity_alarm; 1340 uint16_t remaining_time_alarm; 1341 uint8_t reserved[26]; 1342 } __packed; 1343 1344 struct mfi_bbu_design_info { 1345 uint32_t mfg_date; 1346 uint16_t design_capacity; 1347 uint16_t design_voltage; 1348 uint16_t spec_info; 1349 uint16_t serial_number; 1350 uint16_t pack_stat_config; 1351 uint8_t mfg_name[12]; 1352 uint8_t device_name[8]; 1353 uint8_t device_chemistry[8]; 1354 uint8_t mfg_data[8]; 1355 uint8_t reserved[17]; 1356 } __packed; 1357 1358 struct mfi_ibbu_state { 1359 uint16_t gas_guage_status; 1360 uint16_t relative_charge; 1361 uint16_t charger_system_state; 1362 uint16_t charger_system_ctrl; 1363 uint16_t charging_current; 1364 uint16_t absolute_charge; 1365 uint16_t max_error; 1366 uint8_t reserved[18]; 1367 } __packed; 1368 1369 struct mfi_bbu_state { 1370 uint16_t gas_guage_status; 1371 uint16_t relative_charge; 1372 uint16_t charger_status; 1373 uint16_t remaining_capacity; 1374 uint16_t full_charge_capacity; 1375 uint8_t is_SOH_good; 1376 uint8_t reserved[21]; 1377 } __packed; 1378 1379 struct mfi_bbu_properties { 1380 uint32_t auto_learn_period; 1381 uint32_t next_learn_time; 1382 uint8_t learn_delay_interval; 1383 uint8_t auto_learn_mode; 1384 uint8_t bbu_mode; 1385 uint8_t reserved[21]; 1386 } __packed; 1387 1388 union mfi_bbu_status_detail { 1389 struct mfi_ibbu_state ibbu; 1390 struct mfi_bbu_state bbu; 1391 }; 1392 1393 struct mfi_bbu_status { 1394 uint8_t battery_type; 1395 #define MFI_BBU_TYPE_NONE 0 1396 #define MFI_BBU_TYPE_IBBU 1 1397 #define MFI_BBU_TYPE_BBU 2 1398 uint8_t reserved; 1399 uint16_t voltage; 1400 int16_t current; 1401 uint16_t temperature; 1402 uint32_t fw_status; 1403 #define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1404 #define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1405 #define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1406 #define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1407 #define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1408 #define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1409 #define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1410 #define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1411 #define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1412 #define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1413 uint8_t pad[20]; 1414 union mfi_bbu_status_detail detail; 1415 } __packed; 1416 1417 enum mfi_pr_state { 1418 MFI_PR_STATE_STOPPED = 0, 1419 MFI_PR_STATE_READY = 1, 1420 MFI_PR_STATE_ACTIVE = 2, 1421 MFI_PR_STATE_ABORTED = 0xff 1422 }; 1423 1424 struct mfi_pr_status { 1425 uint32_t num_iteration; 1426 uint8_t state; 1427 uint8_t num_pd_done; 1428 uint8_t reserved[10]; 1429 }; 1430 1431 enum mfi_pr_opmode { 1432 MFI_PR_OPMODE_AUTO = 0, 1433 MFI_PR_OPMODE_MANUAL = 1, 1434 MFI_PR_OPMODE_DISABLED = 2 1435 }; 1436 1437 struct mfi_pr_properties { 1438 uint8_t op_mode; 1439 uint8_t max_pd; 1440 uint8_t reserved; 1441 uint8_t exclude_ld_count; 1442 uint16_t excluded_ld[MFI_MAX_LD]; 1443 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1444 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1445 uint32_t next_exec; 1446 uint32_t exec_freq; 1447 uint32_t clear_freq; 1448 }; 1449 1450 /* ThunderBolt support */ 1451 1452 /* 1453 * Raid Context structure which describes MegaRAID specific IO Paramenters 1454 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1455 */ 1456 typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE { 1457 uint16_t resvd0; /* 0x00 - 0x01 */ 1458 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1459 uint8_t regLockFlags; 1460 uint8_t armId; 1461 uint16_t TargetID; /* 0x06 - 0x07 */ 1462 1463 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1464 1465 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1466 1467 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1468 uint8_t exStatus; /* 0x16 */ 1469 uint8_t Status; /* 0x17 status */ 1470 1471 uint8_t RAIDFlags; /* 0x18 */ 1472 uint8_t numSGE; /* 0x19 numSge */ 1473 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1474 uint8_t spanArm; /* 0x1C */ 1475 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1476 } MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE; 1477 1478 /***************************************************************************** 1479 * 1480 * Message Functions 1481 * 1482 *****************************************************************************/ 1483 1484 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1485 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1486 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1487 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1488 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1489 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1490 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1491 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1492 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1493 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1494 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1495 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1496 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1497 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1498 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1499 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1500 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1501 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1502 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1503 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1504 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1505 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1506 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1507 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1508 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1509 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1510 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1511 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1512 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1513 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1514 1515 /* Doorbell functions */ 1516 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1517 #define MPI2_FUNCTION_HANDSHAKE (0x42) 1518 1519 /***************************************************************************** 1520 * 1521 * MPI Version Definitions 1522 * 1523 *****************************************************************************/ 1524 1525 #define MPI2_VERSION_MAJOR (0x02) 1526 #define MPI2_VERSION_MINOR (0x00) 1527 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 1528 #define MPI2_VERSION_MAJOR_SHIFT (8) 1529 #define MPI2_VERSION_MINOR_MASK (0x00FF) 1530 #define MPI2_VERSION_MINOR_SHIFT (0) 1531 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1532 MPI2_VERSION_MINOR) 1533 1534 #define MPI2_VERSION_02_00 (0x0200) 1535 1536 /* versioning for this MPI header set */ 1537 #define MPI2_HEADER_VERSION_UNIT (0x10) 1538 #define MPI2_HEADER_VERSION_DEV (0x00) 1539 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1540 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1541 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1542 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1543 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1544 MPI2_HEADER_VERSION_DEV) 1545 1546 1547 /* IOCInit Request message */ 1548 struct MPI2_IOC_INIT_REQUEST { 1549 uint8_t WhoInit; /* 0x00 */ 1550 uint8_t Reserved1; /* 0x01 */ 1551 uint8_t ChainOffset; /* 0x02 */ 1552 uint8_t Function; /* 0x03 */ 1553 uint16_t Reserved2; /* 0x04 */ 1554 uint8_t Reserved3; /* 0x06 */ 1555 uint8_t MsgFlags; /* 0x07 */ 1556 uint8_t VP_ID; /* 0x08 */ 1557 uint8_t VF_ID; /* 0x09 */ 1558 uint16_t Reserved4; /* 0x0A */ 1559 uint16_t MsgVersion; /* 0x0C */ 1560 uint16_t HeaderVersion; /* 0x0E */ 1561 uint32_t Reserved5; /* 0x10 */ 1562 uint16_t Reserved6; /* 0x14 */ 1563 uint8_t Reserved7; /* 0x16 */ 1564 uint8_t HostMSIxVectors; /* 0x17 */ 1565 uint16_t Reserved8; /* 0x18 */ 1566 uint16_t SystemRequestFrameSize; /* 0x1A */ 1567 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1568 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1569 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1570 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1571 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1572 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1573 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1574 uint64_t TimeStamp; /* 0x40 */ 1575 }; 1576 1577 /* WhoInit values */ 1578 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1579 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1580 #define MPI2_WHOINIT_ROM_BIOS (0x02) 1581 #define MPI2_WHOINIT_PCI_PEER (0x03) 1582 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 1583 #define MPI2_WHOINIT_MANUFACTURER (0x05) 1584 1585 struct MPI2_SGE_CHAIN_UNION { 1586 uint16_t Length; 1587 uint8_t NextChainOffset; 1588 uint8_t Flags; 1589 union { 1590 uint32_t Address32; 1591 uint64_t Address64; 1592 } u; 1593 }; 1594 1595 struct MPI2_IEEE_SGE_SIMPLE32 { 1596 uint32_t Address; 1597 uint32_t FlagsLength; 1598 }; 1599 1600 struct MPI2_IEEE_SGE_SIMPLE64 { 1601 uint64_t Address; 1602 uint32_t Length; 1603 uint16_t Reserved1; 1604 uint8_t Reserved2; 1605 uint8_t Flags; 1606 }; 1607 1608 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1609 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 1610 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 1611 } MPI2_IEEE_SGE_SIMPLE_UNION; 1612 1613 typedef struct _MPI2_SGE_SIMPLE_UNION { 1614 uint32_t FlagsLength; 1615 union { 1616 uint32_t Address32; 1617 uint64_t Address64; 1618 } u; 1619 } MPI2_SGE_SIMPLE_UNION; 1620 1621 /**************************************************************************** 1622 * IEEE SGE field definitions and masks 1623 ****************************************************************************/ 1624 1625 /* Flags field bit definitions */ 1626 1627 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1628 1629 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1630 1631 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1632 1633 /* Element Type */ 1634 1635 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1636 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1637 1638 /* Data Location Address Space */ 1639 1640 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1641 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1642 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1643 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1644 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1645 1646 /* Address Size */ 1647 1648 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1649 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1650 1651 /*******************/ 1652 /* SCSI IO Control bits */ 1653 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1654 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1655 1656 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1657 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1658 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1659 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1660 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1661 1662 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1663 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1664 1665 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1666 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1667 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1668 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1669 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1670 1671 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1672 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1673 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1674 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1675 1676 /*******************/ 1677 1678 typedef struct { 1679 uint8_t CDB[20]; /* 0x00 */ 1680 uint32_t PrimaryReferenceTag; /* 0x14 */ 1681 uint16_t PrimaryApplicationTag; /* 0x18 */ 1682 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1683 uint32_t TransferLength; /* 0x1C */ 1684 } MPI2_SCSI_IO_CDB_EEDP32; 1685 1686 1687 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1688 struct MPI2_IEEE_SGE_SIMPLE32 Chain32; 1689 struct MPI2_IEEE_SGE_SIMPLE64 Chain64; 1690 } MPI2_IEEE_SGE_CHAIN_UNION; 1691 1692 typedef union _MPI2_SIMPLE_SGE_UNION { 1693 MPI2_SGE_SIMPLE_UNION MpiSimple; 1694 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1695 } MPI2_SIMPLE_SGE_UNION; 1696 1697 typedef union _MPI2_SGE_IO_UNION { 1698 MPI2_SGE_SIMPLE_UNION MpiSimple; 1699 struct MPI2_SGE_CHAIN_UNION MpiChain; 1700 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1701 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1702 } MPI2_SGE_IO_UNION; 1703 1704 typedef union { 1705 uint8_t CDB32[32]; 1706 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 1707 MPI2_SGE_SIMPLE_UNION SGE; 1708 } MPI2_SCSI_IO_CDB_UNION; 1709 1710 1711 /* MPI 2.5 SGLs */ 1712 1713 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1714 1715 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1716 uint64_t Address; 1717 uint32_t Length; 1718 uint16_t Reserved1; 1719 uint8_t NextChainOffset; 1720 uint8_t Flags; 1721 } MPI25_IEEE_SGE_CHAIN64, *pMpi25IeeeSgeChain64_t; 1722 1723 /* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1724 1725 1726 /********/ 1727 1728 /* 1729 * RAID SCSI IO Request Message 1730 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1731 */ 1732 struct mfi_mpi2_request_raid_scsi_io { 1733 uint16_t DevHandle; /* 0x00 */ 1734 uint8_t ChainOffset; /* 0x02 */ 1735 uint8_t Function; /* 0x03 */ 1736 uint16_t Reserved1; /* 0x04 */ 1737 uint8_t Reserved2; /* 0x06 */ 1738 uint8_t MsgFlags; /* 0x07 */ 1739 uint8_t VP_ID; /* 0x08 */ 1740 uint8_t VF_ID; /* 0x09 */ 1741 uint16_t Reserved3; /* 0x0A */ 1742 uint32_t SenseBufferLowAddress; /* 0x0C */ 1743 uint16_t SGLFlags; /* 0x10 */ 1744 uint8_t SenseBufferLength; /* 0x12 */ 1745 uint8_t Reserved4; /* 0x13 */ 1746 uint8_t SGLOffset0; /* 0x14 */ 1747 uint8_t SGLOffset1; /* 0x15 */ 1748 uint8_t SGLOffset2; /* 0x16 */ 1749 uint8_t SGLOffset3; /* 0x17 */ 1750 uint32_t SkipCount; /* 0x18 */ 1751 uint32_t DataLength; /* 0x1C */ 1752 uint32_t BidirectionalDataLength; /* 0x20 */ 1753 uint16_t IoFlags; /* 0x24 */ 1754 uint16_t EEDPFlags; /* 0x26 */ 1755 uint32_t EEDPBlockSize; /* 0x28 */ 1756 uint32_t SecondaryReferenceTag; /* 0x2C */ 1757 uint16_t SecondaryApplicationTag; /* 0x30 */ 1758 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1759 uint8_t LUN[8]; /* 0x34 */ 1760 uint32_t Control; /* 0x3C */ 1761 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 1762 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */ 1763 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 1764 } __packed; 1765 1766 /* 1767 * MPT RAID MFA IO Descriptor. 1768 */ 1769 typedef struct _MFI_RAID_MFA_IO_DESCRIPTOR { 1770 uint32_t RequestFlags : 8; 1771 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1772 uint32_t MessageAddress2; /* bits 61:32 */ 1773 } MFI_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMFI_RAID_MFA_IO_REQUEST_DESCRIPTOR; 1774 1775 struct mfi_mpi2_request_header { 1776 uint8_t RequestFlags; /* 0x00 */ 1777 uint8_t MSIxIndex; /* 0x01 */ 1778 uint16_t SMID; /* 0x02 */ 1779 uint16_t LMID; /* 0x04 */ 1780 }; 1781 1782 /* defines for the RequestFlags field */ 1783 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1784 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1785 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1786 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1787 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1788 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1789 1790 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1791 1792 struct mfi_mpi2_request_high_priority { 1793 struct mfi_mpi2_request_header header; 1794 uint16_t reserved; 1795 }; 1796 1797 struct mfi_mpi2_request_scsi_io { 1798 struct mfi_mpi2_request_header header; 1799 uint16_t scsi_io_dev_handle; 1800 }; 1801 1802 struct mfi_mpi2_request_scsi_target { 1803 struct mfi_mpi2_request_header header; 1804 uint16_t scsi_target_io_index; 1805 }; 1806 1807 /* Request Descriptors */ 1808 union mfi_mpi2_request_descriptor { 1809 struct mfi_mpi2_request_header header; 1810 struct mfi_mpi2_request_high_priority high_priority; 1811 struct mfi_mpi2_request_scsi_io scsi_io; 1812 struct mfi_mpi2_request_scsi_target scsi_target; 1813 uint64_t words; 1814 }; 1815 1816 1817 struct mfi_mpi2_reply_header { 1818 uint8_t ReplyFlags; /* 0x00 */ 1819 uint8_t MSIxIndex; /* 0x01 */ 1820 uint16_t SMID; /* 0x02 */ 1821 }; 1822 1823 /* defines for the ReplyFlags field */ 1824 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1825 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1826 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1827 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1828 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1829 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1830 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1831 1832 /* values for marking a reply descriptor as unused */ 1833 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1834 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1835 1836 struct mfi_mpi2_reply_default { 1837 struct mfi_mpi2_reply_header header; 1838 uint32_t DescriptorTypeDependent2; 1839 }; 1840 1841 struct mfi_mpi2_reply_address { 1842 struct mfi_mpi2_reply_header header; 1843 uint32_t ReplyFrameAddress; 1844 }; 1845 1846 struct mfi_mpi2_reply_scsi_io { 1847 struct mfi_mpi2_reply_header header; 1848 uint16_t TaskTag; /* 0x04 */ 1849 uint16_t Reserved1; /* 0x06 */ 1850 }; 1851 1852 struct mfi_mpi2_reply_target_assist { 1853 struct mfi_mpi2_reply_header header; 1854 uint8_t SequenceNumber; /* 0x04 */ 1855 uint8_t Reserved1; /* 0x04 */ 1856 uint16_t IoIndex; /* 0x06 */ 1857 }; 1858 1859 struct mfi_mpi2_reply_target_cmd_buffer { 1860 struct mfi_mpi2_reply_header header; 1861 uint8_t SequenceNumber; /* 0x04 */ 1862 uint8_t Flags; /* 0x04 */ 1863 uint16_t InitiatorDevHandle; /* 0x06 */ 1864 uint16_t IoIndex; /* 0x06 */ 1865 }; 1866 1867 struct mfi_mpi2_reply_raid_accel { 1868 struct mfi_mpi2_reply_header header; 1869 uint8_t SequenceNumber; /* 0x04 */ 1870 uint32_t Reserved; /* 0x04 */ 1871 }; 1872 1873 /* union of Reply Descriptors */ 1874 union mfi_mpi2_reply_descriptor { 1875 struct mfi_mpi2_reply_header header; 1876 struct mfi_mpi2_reply_scsi_io scsi_io; 1877 struct mfi_mpi2_reply_target_assist target_assist; 1878 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1879 struct mfi_mpi2_reply_raid_accel raid_accel; 1880 struct mfi_mpi2_reply_default reply_default; 1881 uint64_t words; 1882 }; 1883 1884 struct IO_REQUEST_INFO { 1885 uint64_t ldStartBlock; 1886 uint32_t numBlocks; 1887 uint16_t ldTgtId; 1888 uint8_t isRead; 1889 uint16_t devHandle; 1890 uint64_t pdBlock; 1891 uint8_t fpOkForIo; 1892 }; 1893 1894 #define MFI_SCSI_MAX_TARGETS 128 1895 #define MFI_SCSI_MAX_LUNS 8 1896 #define MFI_SCSI_INITIATOR_ID 255 1897 #define MFI_SCSI_MAX_CMDS 8 1898 #define MFI_SCSI_MAX_CDB_LEN 16 1899 1900 #endif /* _MFIREG_H */ 1901