1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Microsoft Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _MANA_H 33 #define _MANA_H 34 35 #include <sys/types.h> 36 #include <sys/proc.h> 37 #include <sys/socket.h> 38 #include <sys/sysctl.h> 39 #include <sys/taskqueue.h> 40 #include <sys/counter.h> 41 42 #include <net/ethernet.h> 43 #include <net/if.h> 44 #include <net/if_media.h> 45 #include <netinet/tcp_lro.h> 46 47 #include "gdma.h" 48 #include "hw_channel.h" 49 50 51 /* Microsoft Azure Network Adapter (MANA)'s definitions 52 * 53 * Structures labeled with "HW DATA" are exchanged with the hardware. All of 54 * them are naturally aligned and hence don't need __packed. 55 */ 56 /* MANA protocol version */ 57 #define MANA_MAJOR_VERSION 0 58 #define MANA_MINOR_VERSION 1 59 #define MANA_MICRO_VERSION 1 60 61 #define DRV_MODULE_NAME "mana" 62 63 #ifndef DRV_MODULE_VERSION 64 #define DRV_MODULE_VERSION \ 65 __XSTRING(MANA_MAJOR_VERSION) "." \ 66 __XSTRING(MANA_MINOR_VERSION) "." \ 67 __XSTRING(MANA_MICRO_VERSION) 68 #endif 69 #define DEVICE_NAME "Microsoft Azure Network Adapter (MANA)" 70 #define DEVICE_DESC "MANA adapter" 71 72 /* 73 * Supported PCI vendor and devices IDs 74 */ 75 #ifndef PCI_VENDOR_ID_MICROSOFT 76 #define PCI_VENDOR_ID_MICROSOFT 0x1414 77 #endif 78 79 #define PCI_DEV_ID_MANA_VF 0x00ba 80 81 typedef struct _mana_vendor_id_t { 82 uint16_t vendor_id; 83 uint16_t device_id; 84 } mana_vendor_id_t; 85 86 typedef uint64_t mana_handle_t; 87 #define INVALID_MANA_HANDLE ((mana_handle_t)-1) 88 89 enum TRI_STATE { 90 TRI_STATE_UNKNOWN = -1, 91 TRI_STATE_FALSE = 0, 92 TRI_STATE_TRUE = 1 93 }; 94 95 /* Number of entries for hardware indirection table must be in power of 2 */ 96 #define MANA_INDIRECT_TABLE_SIZE 64 97 #define MANA_INDIRECT_TABLE_MASK (MANA_INDIRECT_TABLE_SIZE - 1) 98 99 /* The Toeplitz hash key's length in bytes: should be multiple of 8 */ 100 #define MANA_HASH_KEY_SIZE 40 101 102 #define COMP_ENTRY_SIZE 64 103 104 #define MIN_FRAME_SIZE 146 105 #define ADAPTER_MTU_SIZE 1500 106 #define DEFAULT_FRAME_SIZE (ADAPTER_MTU_SIZE + 14) 107 #define MAX_FRAME_SIZE 4096 108 109 #define RX_BUFFERS_PER_QUEUE 512 110 111 #define MAX_SEND_BUFFERS_PER_QUEUE 256 112 113 #define EQ_SIZE (8 * PAGE_SIZE) 114 #define LOG2_EQ_THROTTLE 3 115 116 #define MAX_PORTS_IN_MANA_DEV 8 117 118 struct mana_send_buf_info { 119 struct mbuf *mbuf; 120 bus_dmamap_t dma_map; 121 122 /* Required to store the result of mana_gd_post_work_request. 123 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 124 * work queue when the WQE is consumed. 125 */ 126 struct gdma_posted_wqe_info wqe_inf; 127 }; 128 129 struct mana_stats { 130 counter_u64_t packets; /* rx, tx */ 131 counter_u64_t bytes; /* rx, tx */ 132 counter_u64_t stop; /* tx */ 133 counter_u64_t wakeup; /* tx */ 134 counter_u64_t collapse; /* tx */ 135 counter_u64_t collapse_err; /* tx */ 136 counter_u64_t dma_mapping_err; /* rx, tx */ 137 counter_u64_t mbuf_alloc_fail; /* rx */ 138 counter_u64_t alt_chg; /* tx */ 139 counter_u64_t alt_reset; /* tx */ 140 }; 141 142 struct mana_txq { 143 struct gdma_queue *gdma_sq; 144 145 union { 146 uint32_t gdma_txq_id; 147 struct { 148 uint32_t reserved1 :10; 149 uint32_t vsq_frame :14; 150 uint32_t reserved2 :8; 151 }; 152 }; 153 154 uint16_t vp_offset; 155 156 if_t ndev; 157 /* Store index to the array of tx_qp in port structure */ 158 int idx; 159 /* The alternative txq idx when this txq is under heavy load */ 160 int alt_txq_idx; 161 162 /* The mbufs are sent to the HW and we are waiting for the CQEs. */ 163 struct mana_send_buf_info *tx_buf_info; 164 uint16_t next_to_use; 165 uint16_t next_to_complete; 166 167 atomic_t pending_sends; 168 169 struct buf_ring *txq_br; 170 struct mtx txq_mtx; 171 char txq_mtx_name[16]; 172 173 struct task enqueue_task; 174 struct taskqueue *enqueue_tq; 175 176 struct mana_stats stats; 177 }; 178 179 180 /* 181 * Max WQE size is 512B. The first 8B is for GDMA Out of Band (OOB), 182 * next is the Client OOB can be either 8B or 24B. Thus, the max 183 * space for SGL entries in a singel WQE is 512 - 8 - 8 = 496B. Since each 184 * SGL is 16B in size, the max number of SGLs in a WQE is 496/16 = 31. 185 * Save one for emergency use, set the MAX_MBUF_FRAGS allowed to 30. 186 */ 187 #define MAX_MBUF_FRAGS 30 188 #define MANA_TSO_MAXSEG_SZ PAGE_SIZE 189 #define MANA_TSO_MAX_SZ IP_MAXPACKET 190 191 /* mbuf data and frags dma mappings */ 192 struct mana_mbuf_head { 193 bus_addr_t dma_handle[MAX_MBUF_FRAGS + 1]; 194 195 uint32_t size[MAX_MBUF_FRAGS + 1]; 196 }; 197 198 #define MANA_HEADROOM sizeof(struct mana_mbuf_head) 199 200 enum mana_tx_pkt_format { 201 MANA_SHORT_PKT_FMT = 0, 202 MANA_LONG_PKT_FMT = 1, 203 }; 204 205 struct mana_tx_short_oob { 206 uint32_t pkt_fmt :2; 207 uint32_t is_outer_ipv4 :1; 208 uint32_t is_outer_ipv6 :1; 209 uint32_t comp_iphdr_csum :1; 210 uint32_t comp_tcp_csum :1; 211 uint32_t comp_udp_csum :1; 212 uint32_t supress_txcqe_gen :1; 213 uint32_t vcq_num :24; 214 215 uint32_t trans_off :10; /* Transport header offset */ 216 uint32_t vsq_frame :14; 217 uint32_t short_vp_offset :8; 218 }; /* HW DATA */ 219 220 struct mana_tx_long_oob { 221 uint32_t is_encap :1; 222 uint32_t inner_is_ipv6 :1; 223 uint32_t inner_tcp_opt :1; 224 uint32_t inject_vlan_pri_tag :1; 225 uint32_t reserved1 :12; 226 uint32_t pcp :3; /* 802.1Q */ 227 uint32_t dei :1; /* 802.1Q */ 228 uint32_t vlan_id :12; /* 802.1Q */ 229 230 uint32_t inner_frame_offset :10; 231 uint32_t inner_ip_rel_offset :6; 232 uint32_t long_vp_offset :12; 233 uint32_t reserved2 :4; 234 235 uint32_t reserved3; 236 uint32_t reserved4; 237 }; /* HW DATA */ 238 239 struct mana_tx_oob { 240 struct mana_tx_short_oob s_oob; 241 struct mana_tx_long_oob l_oob; 242 }; /* HW DATA */ 243 244 enum mana_cq_type { 245 MANA_CQ_TYPE_RX, 246 MANA_CQ_TYPE_TX, 247 }; 248 249 enum mana_cqe_type { 250 CQE_INVALID = 0, 251 CQE_RX_OKAY = 1, 252 CQE_RX_COALESCED_4 = 2, 253 CQE_RX_OBJECT_FENCE = 3, 254 CQE_RX_TRUNCATED = 4, 255 256 CQE_TX_OKAY = 32, 257 CQE_TX_SA_DROP = 33, 258 CQE_TX_MTU_DROP = 34, 259 CQE_TX_INVALID_OOB = 35, 260 CQE_TX_INVALID_ETH_TYPE = 36, 261 CQE_TX_HDR_PROCESSING_ERROR = 37, 262 CQE_TX_VF_DISABLED = 38, 263 CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39, 264 CQE_TX_VPORT_DISABLED = 40, 265 CQE_TX_VLAN_TAGGING_VIOLATION = 41, 266 }; 267 268 #define MANA_CQE_COMPLETION 1 269 270 struct mana_cqe_header { 271 uint32_t cqe_type :6; 272 uint32_t client_type :2; 273 uint32_t vendor_err :24; 274 }; /* HW DATA */ 275 276 /* NDIS HASH Types */ 277 #define NDIS_HASH_IPV4 BIT(0) 278 #define NDIS_HASH_TCP_IPV4 BIT(1) 279 #define NDIS_HASH_UDP_IPV4 BIT(2) 280 #define NDIS_HASH_IPV6 BIT(3) 281 #define NDIS_HASH_TCP_IPV6 BIT(4) 282 #define NDIS_HASH_UDP_IPV6 BIT(5) 283 #define NDIS_HASH_IPV6_EX BIT(6) 284 #define NDIS_HASH_TCP_IPV6_EX BIT(7) 285 #define NDIS_HASH_UDP_IPV6_EX BIT(8) 286 287 #define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 288 #define MANA_HASH_L4 \ 289 (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \ 290 NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 291 292 #define NDIS_HASH_IPV4_L3_MASK (NDIS_HASH_IPV4) 293 #define NDIS_HASH_IPV4_L4_MASK (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4) 294 #define NDIS_HASH_IPV6_L3_MASK (NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 295 #define NDIS_HASH_IPV6_L4_MASK \ 296 (NDIS_HASH_TCP_IPV6 | NDIS_HASH_UDP_IPV6 | \ 297 NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 298 #define NDIS_HASH_IPV4_MASK \ 299 (NDIS_HASH_IPV4_L3_MASK | NDIS_HASH_IPV4_L4_MASK) 300 #define NDIS_HASH_IPV6_MASK \ 301 (NDIS_HASH_IPV6_L3_MASK | NDIS_HASH_IPV6_L4_MASK) 302 303 304 struct mana_rxcomp_perpkt_info { 305 uint32_t pkt_len :16; 306 uint32_t reserved1 :16; 307 uint32_t reserved2; 308 uint32_t pkt_hash; 309 }; /* HW DATA */ 310 311 #define MANA_RXCOMP_OOB_NUM_PPI 4 312 313 /* Receive completion OOB */ 314 struct mana_rxcomp_oob { 315 struct mana_cqe_header cqe_hdr; 316 317 uint32_t rx_vlan_id :12; 318 uint32_t rx_vlantag_present :1; 319 uint32_t rx_outer_iphdr_csum_succeed :1; 320 uint32_t rx_outer_iphdr_csum_fail :1; 321 uint32_t reserved1 :1; 322 uint32_t rx_hashtype :9; 323 uint32_t rx_iphdr_csum_succeed :1; 324 uint32_t rx_iphdr_csum_fail :1; 325 uint32_t rx_tcp_csum_succeed :1; 326 uint32_t rx_tcp_csum_fail :1; 327 uint32_t rx_udp_csum_succeed :1; 328 uint32_t rx_udp_csum_fail :1; 329 uint32_t reserved2 :1; 330 331 struct mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI]; 332 333 uint32_t rx_wqe_offset; 334 }; /* HW DATA */ 335 336 struct mana_tx_comp_oob { 337 struct mana_cqe_header cqe_hdr; 338 339 uint32_t tx_data_offset; 340 341 uint32_t tx_sgl_offset :5; 342 uint32_t tx_wqe_offset :27; 343 344 uint32_t reserved[12]; 345 }; /* HW DATA */ 346 347 struct mana_rxq; 348 349 #define CQE_POLLING_BUFFER 512 350 351 struct mana_cq { 352 struct gdma_queue *gdma_cq; 353 354 /* Cache the CQ id (used to verify if each CQE comes to the right CQ. */ 355 uint32_t gdma_id; 356 357 /* Type of the CQ: TX or RX */ 358 enum mana_cq_type type; 359 360 /* Pointer to the mana_rxq that is pushing RX CQEs to the queue. 361 * Only and must be non-NULL if type is MANA_CQ_TYPE_RX. 362 */ 363 struct mana_rxq *rxq; 364 365 /* Pointer to the mana_txq that is pushing TX CQEs to the queue. 366 * Only and must be non-NULL if type is MANA_CQ_TYPE_TX. 367 */ 368 struct mana_txq *txq; 369 370 /* Taskqueue and related structs */ 371 struct task cleanup_task; 372 struct taskqueue *cleanup_tq; 373 int cpu; 374 bool do_not_ring_db; 375 376 /* Budget for one cleanup task */ 377 int work_done; 378 int budget; 379 380 /* Buffer which the CQ handler can copy the CQE's into. */ 381 struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER]; 382 }; 383 384 struct mana_recv_buf_oob { 385 /* A valid GDMA work request representing the data buffer. */ 386 struct gdma_wqe_request wqe_req; 387 388 struct mbuf *mbuf; 389 bus_dmamap_t dma_map; 390 391 /* SGL of the buffer going to be sent as part of the work request. */ 392 uint32_t num_sge; 393 struct gdma_sge sgl[MAX_RX_WQE_SGL_ENTRIES]; 394 395 /* Required to store the result of mana_gd_post_work_request. 396 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 397 * work queue when the WQE is consumed. 398 */ 399 struct gdma_posted_wqe_info wqe_inf; 400 }; 401 402 struct mana_rxq { 403 struct gdma_queue *gdma_rq; 404 /* Cache the gdma receive queue id */ 405 uint32_t gdma_id; 406 407 /* Index of RQ in the vPort, not gdma receive queue id */ 408 uint32_t rxq_idx; 409 410 uint32_t datasize; 411 412 mana_handle_t rxobj; 413 414 struct completion fence_event; 415 416 struct mana_cq rx_cq; 417 418 if_t ndev; 419 struct lro_ctrl lro; 420 421 /* Total number of receive buffers to be allocated */ 422 uint32_t num_rx_buf; 423 424 uint32_t buf_index; 425 426 struct mana_stats stats; 427 428 /* MUST BE THE LAST MEMBER: 429 * Each receive buffer has an associated mana_recv_buf_oob. 430 */ 431 struct mana_recv_buf_oob rx_oobs[]; 432 }; 433 434 struct mana_tx_qp { 435 struct mana_txq txq; 436 437 struct mana_cq tx_cq; 438 439 mana_handle_t tx_object; 440 }; 441 442 struct mana_port_stats { 443 counter_u64_t rx_packets; 444 counter_u64_t tx_packets; 445 446 counter_u64_t rx_bytes; 447 counter_u64_t tx_bytes; 448 449 counter_u64_t rx_drops; 450 counter_u64_t tx_drops; 451 452 counter_u64_t stop_queue; 453 counter_u64_t wake_queue; 454 }; 455 456 struct mana_context { 457 struct gdma_dev *gdma_dev; 458 459 uint16_t num_ports; 460 461 struct mana_eq *eqs; 462 463 if_t ports[MAX_PORTS_IN_MANA_DEV]; 464 }; 465 466 struct mana_port_context { 467 struct mana_context *ac; 468 if_t ndev; 469 struct ifmedia media; 470 471 struct sx apc_lock; 472 473 /* DMA tag used for queue bufs of the entire port */ 474 bus_dma_tag_t rx_buf_tag; 475 bus_dma_tag_t tx_buf_tag; 476 477 uint8_t mac_addr[ETHER_ADDR_LEN]; 478 479 enum TRI_STATE rss_state; 480 481 mana_handle_t default_rxobj; 482 bool tx_shortform_allowed; 483 uint16_t tx_vp_offset; 484 485 struct mana_tx_qp *tx_qp; 486 487 /* Indirection Table for RX & TX. The values are queue indexes */ 488 uint32_t indir_table[MANA_INDIRECT_TABLE_SIZE]; 489 490 /* Indirection table containing RxObject Handles */ 491 mana_handle_t rxobj_table[MANA_INDIRECT_TABLE_SIZE]; 492 493 /* Hash key used by the NIC */ 494 uint8_t hashkey[MANA_HASH_KEY_SIZE]; 495 496 /* This points to an array of num_queues of RQ pointers. */ 497 struct mana_rxq **rxqs; 498 499 /* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */ 500 unsigned int max_queues; 501 unsigned int num_queues; 502 503 mana_handle_t port_handle; 504 505 int vport_use_count; 506 507 uint16_t port_idx; 508 509 uint16_t frame_size; 510 511 bool port_is_up; 512 bool port_st_save; /* Saved port state */ 513 514 bool enable_tx_altq; 515 516 bool bind_cleanup_thread_cpu; 517 int last_tx_cq_bind_cpu; 518 int last_rx_cq_bind_cpu; 519 520 struct mana_port_stats port_stats; 521 522 struct sysctl_oid_list *port_list; 523 struct sysctl_ctx_list que_sysctl_ctx; 524 }; 525 526 #define MANA_APC_LOCK_INIT(apc) \ 527 sx_init(&(apc)->apc_lock, "MANA port lock") 528 #define MANA_APC_LOCK_DESTROY(apc) sx_destroy(&(apc)->apc_lock) 529 #define MANA_APC_LOCK_LOCK(apc) sx_xlock(&(apc)->apc_lock) 530 #define MANA_APC_LOCK_UNLOCK(apc) sx_unlock(&(apc)->apc_lock) 531 532 int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx, 533 bool update_hash, bool update_tab); 534 535 int mana_alloc_queues(if_t ndev); 536 int mana_attach(if_t ndev); 537 int mana_detach(if_t ndev); 538 539 int mana_probe(struct gdma_dev *gd); 540 void mana_remove(struct gdma_dev *gd); 541 542 struct mana_obj_spec { 543 uint32_t queue_index; 544 uint64_t gdma_region; 545 uint32_t queue_size; 546 uint32_t attached_eq; 547 uint32_t modr_ctx_id; 548 }; 549 550 enum mana_command_code { 551 MANA_QUERY_DEV_CONFIG = 0x20001, 552 MANA_QUERY_GF_STAT = 0x20002, 553 MANA_CONFIG_VPORT_TX = 0x20003, 554 MANA_CREATE_WQ_OBJ = 0x20004, 555 MANA_DESTROY_WQ_OBJ = 0x20005, 556 MANA_FENCE_RQ = 0x20006, 557 MANA_CONFIG_VPORT_RX = 0x20007, 558 MANA_QUERY_VPORT_CONFIG = 0x20008, 559 }; 560 561 /* Query Device Configuration */ 562 struct mana_query_device_cfg_req { 563 struct gdma_req_hdr hdr; 564 565 /* Driver Capability flags */ 566 uint64_t drv_cap_flags1; 567 uint64_t drv_cap_flags2; 568 uint64_t drv_cap_flags3; 569 uint64_t drv_cap_flags4; 570 571 uint32_t proto_major_ver; 572 uint32_t proto_minor_ver; 573 uint32_t proto_micro_ver; 574 575 uint32_t reserved; 576 }; /* HW DATA */ 577 578 struct mana_query_device_cfg_resp { 579 struct gdma_resp_hdr hdr; 580 581 uint64_t pf_cap_flags1; 582 uint64_t pf_cap_flags2; 583 uint64_t pf_cap_flags3; 584 uint64_t pf_cap_flags4; 585 586 uint16_t max_num_vports; 587 uint16_t reserved; 588 uint32_t max_num_eqs; 589 }; /* HW DATA */ 590 591 /* Query vPort Configuration */ 592 struct mana_query_vport_cfg_req { 593 struct gdma_req_hdr hdr; 594 uint32_t vport_index; 595 }; /* HW DATA */ 596 597 struct mana_query_vport_cfg_resp { 598 struct gdma_resp_hdr hdr; 599 uint32_t max_num_sq; 600 uint32_t max_num_rq; 601 uint32_t num_indirection_ent; 602 uint32_t reserved1; 603 uint8_t mac_addr[6]; 604 uint8_t reserved2[2]; 605 mana_handle_t vport; 606 }; /* HW DATA */ 607 608 /* Configure vPort */ 609 struct mana_config_vport_req { 610 struct gdma_req_hdr hdr; 611 mana_handle_t vport; 612 uint32_t pdid; 613 uint32_t doorbell_pageid; 614 }; /* HW DATA */ 615 616 struct mana_config_vport_resp { 617 struct gdma_resp_hdr hdr; 618 uint16_t tx_vport_offset; 619 uint8_t short_form_allowed; 620 uint8_t reserved; 621 }; /* HW DATA */ 622 623 /* Create WQ Object */ 624 struct mana_create_wqobj_req { 625 struct gdma_req_hdr hdr; 626 mana_handle_t vport; 627 uint32_t wq_type; 628 uint32_t reserved; 629 uint64_t wq_gdma_region; 630 uint64_t cq_gdma_region; 631 uint32_t wq_size; 632 uint32_t cq_size; 633 uint32_t cq_moderation_ctx_id; 634 uint32_t cq_parent_qid; 635 }; /* HW DATA */ 636 637 struct mana_create_wqobj_resp { 638 struct gdma_resp_hdr hdr; 639 uint32_t wq_id; 640 uint32_t cq_id; 641 mana_handle_t wq_obj; 642 }; /* HW DATA */ 643 644 /* Destroy WQ Object */ 645 struct mana_destroy_wqobj_req { 646 struct gdma_req_hdr hdr; 647 uint32_t wq_type; 648 uint32_t reserved; 649 mana_handle_t wq_obj_handle; 650 }; /* HW DATA */ 651 652 struct mana_destroy_wqobj_resp { 653 struct gdma_resp_hdr hdr; 654 }; /* HW DATA */ 655 656 /* Fence RQ */ 657 struct mana_fence_rq_req { 658 struct gdma_req_hdr hdr; 659 mana_handle_t wq_obj_handle; 660 }; /* HW DATA */ 661 662 struct mana_fence_rq_resp { 663 struct gdma_resp_hdr hdr; 664 }; /* HW DATA */ 665 666 /* Configure vPort Rx Steering */ 667 struct mana_cfg_rx_steer_req { 668 struct gdma_req_hdr hdr; 669 mana_handle_t vport; 670 uint16_t num_indir_entries; 671 uint16_t indir_tab_offset; 672 uint32_t rx_enable; 673 uint32_t rss_enable; 674 uint8_t update_default_rxobj; 675 uint8_t update_hashkey; 676 uint8_t update_indir_tab; 677 uint8_t reserved; 678 mana_handle_t default_rxobj; 679 uint8_t hashkey[MANA_HASH_KEY_SIZE]; 680 }; /* HW DATA */ 681 682 struct mana_cfg_rx_steer_resp { 683 struct gdma_resp_hdr hdr; 684 }; /* HW DATA */ 685 686 #define MANA_MAX_NUM_QUEUES 16 687 688 #define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1) 689 690 struct mana_tx_package { 691 struct gdma_wqe_request wqe_req; 692 struct gdma_sge sgl_array[MAX_MBUF_FRAGS]; 693 694 struct mana_tx_oob tx_oob; 695 696 struct gdma_posted_wqe_info wqe_info; 697 }; 698 699 int mana_restart(struct mana_port_context *apc); 700 701 int mana_create_wq_obj(struct mana_port_context *apc, 702 mana_handle_t vport, 703 uint32_t wq_type, struct mana_obj_spec *wq_spec, 704 struct mana_obj_spec *cq_spec, 705 mana_handle_t *wq_obj); 706 707 void mana_destroy_wq_obj(struct mana_port_context *apc, uint32_t wq_type, 708 mana_handle_t wq_obj); 709 710 int mana_cfg_vport(struct mana_port_context *apc, uint32_t protection_dom_id, 711 uint32_t doorbell_pg_id); 712 713 void mana_uncfg_vport(struct mana_port_context *apc); 714 #endif /* _MANA_H */ 715