1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Microsoft Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _MANA_H 33 #define _MANA_H 34 35 #include <sys/types.h> 36 #include <sys/proc.h> 37 #include <sys/socket.h> 38 #include <sys/sysctl.h> 39 #include <sys/taskqueue.h> 40 #include <sys/counter.h> 41 42 #include <net/ethernet.h> 43 #include <net/if.h> 44 #include <net/if_media.h> 45 #include <netinet/tcp_lro.h> 46 47 #include "gdma.h" 48 #include "hw_channel.h" 49 50 51 /* Microsoft Azure Network Adapter (MANA)'s definitions 52 * 53 * Structures labeled with "HW DATA" are exchanged with the hardware. All of 54 * them are naturally aligned and hence don't need __packed. 55 */ 56 /* MANA protocol version */ 57 #define MANA_MAJOR_VERSION 0 58 #define MANA_MINOR_VERSION 1 59 #define MANA_MICRO_VERSION 1 60 61 #define DRV_MODULE_NAME "mana" 62 63 #ifndef DRV_MODULE_VERSION 64 #define DRV_MODULE_VERSION \ 65 __XSTRING(MANA_MAJOR_VERSION) "." \ 66 __XSTRING(MANA_MINOR_VERSION) "." \ 67 __XSTRING(MANA_MICRO_VERSION) 68 #endif 69 #define DEVICE_NAME "Microsoft Azure Network Adapter (MANA)" 70 #define DEVICE_DESC "MANA adapter" 71 72 /* 73 * Supported PCI vendor and devices IDs 74 */ 75 #ifndef PCI_VENDOR_ID_MICROSOFT 76 #define PCI_VENDOR_ID_MICROSOFT 0x1414 77 #endif 78 79 #define PCI_DEV_ID_MANA_VF 0x00ba 80 81 typedef struct _mana_vendor_id_t { 82 uint16_t vendor_id; 83 uint16_t device_id; 84 } mana_vendor_id_t; 85 86 typedef uint64_t mana_handle_t; 87 #define INVALID_MANA_HANDLE ((mana_handle_t)-1) 88 89 enum TRI_STATE { 90 TRI_STATE_UNKNOWN = -1, 91 TRI_STATE_FALSE = 0, 92 TRI_STATE_TRUE = 1 93 }; 94 95 /* Number of entries for hardware indirection table must be in power of 2 */ 96 #define MANA_INDIRECT_TABLE_SIZE 64 97 #define MANA_INDIRECT_TABLE_MASK (MANA_INDIRECT_TABLE_SIZE - 1) 98 99 /* The Toeplitz hash key's length in bytes: should be multiple of 8 */ 100 #define MANA_HASH_KEY_SIZE 40 101 102 #define COMP_ENTRY_SIZE 64 103 104 #define MIN_FRAME_SIZE 146 105 #define ADAPTER_MTU_SIZE 1500 106 #define DEFAULT_FRAME_SIZE (ADAPTER_MTU_SIZE + 14) 107 #define MAX_FRAME_SIZE 4096 108 109 #define RX_BUFFERS_PER_QUEUE 512 110 111 #define MAX_SEND_BUFFERS_PER_QUEUE 256 112 113 #define EQ_SIZE (8 * PAGE_SIZE) 114 #define LOG2_EQ_THROTTLE 3 115 116 #define MAX_PORTS_IN_MANA_DEV 8 117 118 struct mana_send_buf_info { 119 struct mbuf *mbuf; 120 bus_dmamap_t dma_map; 121 122 /* Required to store the result of mana_gd_post_work_request. 123 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 124 * work queue when the WQE is consumed. 125 */ 126 struct gdma_posted_wqe_info wqe_inf; 127 }; 128 129 struct mana_stats { 130 counter_u64_t packets; /* rx, tx */ 131 counter_u64_t bytes; /* rx, tx */ 132 counter_u64_t stop; /* tx */ 133 counter_u64_t wakeup; /* tx */ 134 counter_u64_t collapse; /* tx */ 135 counter_u64_t collapse_err; /* tx */ 136 counter_u64_t dma_mapping_err; /* rx, tx */ 137 counter_u64_t mbuf_alloc_fail; /* rx */ 138 counter_u64_t alt_chg; /* tx */ 139 counter_u64_t alt_reset; /* tx */ 140 }; 141 142 struct mana_txq { 143 struct gdma_queue *gdma_sq; 144 145 union { 146 uint32_t gdma_txq_id; 147 struct { 148 uint32_t reserved1 :10; 149 uint32_t vsq_frame :14; 150 uint32_t reserved2 :8; 151 }; 152 }; 153 154 uint16_t vp_offset; 155 156 if_t ndev; 157 /* Store index to the array of tx_qp in port structure */ 158 int idx; 159 /* The alternative txq idx when this txq is under heavy load */ 160 int alt_txq_idx; 161 162 /* The mbufs are sent to the HW and we are waiting for the CQEs. */ 163 struct mana_send_buf_info *tx_buf_info; 164 uint16_t next_to_use; 165 uint16_t next_to_complete; 166 167 atomic_t pending_sends; 168 169 struct buf_ring *txq_br; 170 struct mtx txq_mtx; 171 char txq_mtx_name[16]; 172 173 struct task enqueue_task; 174 struct taskqueue *enqueue_tq; 175 176 struct mana_stats stats; 177 }; 178 179 180 /* 181 * Max WQE size is 512B. The first 8B is for GDMA Out of Band (OOB), 182 * next is the Client OOB can be either 8B or 24B. Thus, the max 183 * space for SGL entries in a singel WQE is 512 - 8 - 8 = 496B. Since each 184 * SGL is 16B in size, the max number of SGLs in a WQE is 496/16 = 31. 185 * Save one for emergency use, set the MAX_MBUF_FRAGS allowed to 30. 186 */ 187 #define MAX_MBUF_FRAGS 30 188 #define MANA_TSO_MAXSEG_SZ PAGE_SIZE 189 190 /* mbuf data and frags dma mappings */ 191 struct mana_mbuf_head { 192 bus_addr_t dma_handle[MAX_MBUF_FRAGS + 1]; 193 194 uint32_t size[MAX_MBUF_FRAGS + 1]; 195 }; 196 197 #define MANA_HEADROOM sizeof(struct mana_mbuf_head) 198 199 enum mana_tx_pkt_format { 200 MANA_SHORT_PKT_FMT = 0, 201 MANA_LONG_PKT_FMT = 1, 202 }; 203 204 struct mana_tx_short_oob { 205 uint32_t pkt_fmt :2; 206 uint32_t is_outer_ipv4 :1; 207 uint32_t is_outer_ipv6 :1; 208 uint32_t comp_iphdr_csum :1; 209 uint32_t comp_tcp_csum :1; 210 uint32_t comp_udp_csum :1; 211 uint32_t supress_txcqe_gen :1; 212 uint32_t vcq_num :24; 213 214 uint32_t trans_off :10; /* Transport header offset */ 215 uint32_t vsq_frame :14; 216 uint32_t short_vp_offset :8; 217 }; /* HW DATA */ 218 219 struct mana_tx_long_oob { 220 uint32_t is_encap :1; 221 uint32_t inner_is_ipv6 :1; 222 uint32_t inner_tcp_opt :1; 223 uint32_t inject_vlan_pri_tag :1; 224 uint32_t reserved1 :12; 225 uint32_t pcp :3; /* 802.1Q */ 226 uint32_t dei :1; /* 802.1Q */ 227 uint32_t vlan_id :12; /* 802.1Q */ 228 229 uint32_t inner_frame_offset :10; 230 uint32_t inner_ip_rel_offset :6; 231 uint32_t long_vp_offset :12; 232 uint32_t reserved2 :4; 233 234 uint32_t reserved3; 235 uint32_t reserved4; 236 }; /* HW DATA */ 237 238 struct mana_tx_oob { 239 struct mana_tx_short_oob s_oob; 240 struct mana_tx_long_oob l_oob; 241 }; /* HW DATA */ 242 243 enum mana_cq_type { 244 MANA_CQ_TYPE_RX, 245 MANA_CQ_TYPE_TX, 246 }; 247 248 enum mana_cqe_type { 249 CQE_INVALID = 0, 250 CQE_RX_OKAY = 1, 251 CQE_RX_COALESCED_4 = 2, 252 CQE_RX_OBJECT_FENCE = 3, 253 CQE_RX_TRUNCATED = 4, 254 255 CQE_TX_OKAY = 32, 256 CQE_TX_SA_DROP = 33, 257 CQE_TX_MTU_DROP = 34, 258 CQE_TX_INVALID_OOB = 35, 259 CQE_TX_INVALID_ETH_TYPE = 36, 260 CQE_TX_HDR_PROCESSING_ERROR = 37, 261 CQE_TX_VF_DISABLED = 38, 262 CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39, 263 CQE_TX_VPORT_DISABLED = 40, 264 CQE_TX_VLAN_TAGGING_VIOLATION = 41, 265 }; 266 267 #define MANA_CQE_COMPLETION 1 268 269 struct mana_cqe_header { 270 uint32_t cqe_type :6; 271 uint32_t client_type :2; 272 uint32_t vendor_err :24; 273 }; /* HW DATA */ 274 275 /* NDIS HASH Types */ 276 #define NDIS_HASH_IPV4 BIT(0) 277 #define NDIS_HASH_TCP_IPV4 BIT(1) 278 #define NDIS_HASH_UDP_IPV4 BIT(2) 279 #define NDIS_HASH_IPV6 BIT(3) 280 #define NDIS_HASH_TCP_IPV6 BIT(4) 281 #define NDIS_HASH_UDP_IPV6 BIT(5) 282 #define NDIS_HASH_IPV6_EX BIT(6) 283 #define NDIS_HASH_TCP_IPV6_EX BIT(7) 284 #define NDIS_HASH_UDP_IPV6_EX BIT(8) 285 286 #define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 287 #define MANA_HASH_L4 \ 288 (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \ 289 NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 290 291 #define NDIS_HASH_IPV4_L3_MASK (NDIS_HASH_IPV4) 292 #define NDIS_HASH_IPV4_L4_MASK (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4) 293 #define NDIS_HASH_IPV6_L3_MASK (NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 294 #define NDIS_HASH_IPV6_L4_MASK \ 295 (NDIS_HASH_TCP_IPV6 | NDIS_HASH_UDP_IPV6 | \ 296 NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 297 #define NDIS_HASH_IPV4_MASK \ 298 (NDIS_HASH_IPV4_L3_MASK | NDIS_HASH_IPV4_L4_MASK) 299 #define NDIS_HASH_IPV6_MASK \ 300 (NDIS_HASH_IPV6_L3_MASK | NDIS_HASH_IPV6_L4_MASK) 301 302 303 struct mana_rxcomp_perpkt_info { 304 uint32_t pkt_len :16; 305 uint32_t reserved1 :16; 306 uint32_t reserved2; 307 uint32_t pkt_hash; 308 }; /* HW DATA */ 309 310 #define MANA_RXCOMP_OOB_NUM_PPI 4 311 312 /* Receive completion OOB */ 313 struct mana_rxcomp_oob { 314 struct mana_cqe_header cqe_hdr; 315 316 uint32_t rx_vlan_id :12; 317 uint32_t rx_vlantag_present :1; 318 uint32_t rx_outer_iphdr_csum_succeed :1; 319 uint32_t rx_outer_iphdr_csum_fail :1; 320 uint32_t reserved1 :1; 321 uint32_t rx_hashtype :9; 322 uint32_t rx_iphdr_csum_succeed :1; 323 uint32_t rx_iphdr_csum_fail :1; 324 uint32_t rx_tcp_csum_succeed :1; 325 uint32_t rx_tcp_csum_fail :1; 326 uint32_t rx_udp_csum_succeed :1; 327 uint32_t rx_udp_csum_fail :1; 328 uint32_t reserved2 :1; 329 330 struct mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI]; 331 332 uint32_t rx_wqe_offset; 333 }; /* HW DATA */ 334 335 struct mana_tx_comp_oob { 336 struct mana_cqe_header cqe_hdr; 337 338 uint32_t tx_data_offset; 339 340 uint32_t tx_sgl_offset :5; 341 uint32_t tx_wqe_offset :27; 342 343 uint32_t reserved[12]; 344 }; /* HW DATA */ 345 346 struct mana_rxq; 347 348 #define CQE_POLLING_BUFFER 512 349 350 struct mana_cq { 351 struct gdma_queue *gdma_cq; 352 353 /* Cache the CQ id (used to verify if each CQE comes to the right CQ. */ 354 uint32_t gdma_id; 355 356 /* Type of the CQ: TX or RX */ 357 enum mana_cq_type type; 358 359 /* Pointer to the mana_rxq that is pushing RX CQEs to the queue. 360 * Only and must be non-NULL if type is MANA_CQ_TYPE_RX. 361 */ 362 struct mana_rxq *rxq; 363 364 /* Pointer to the mana_txq that is pushing TX CQEs to the queue. 365 * Only and must be non-NULL if type is MANA_CQ_TYPE_TX. 366 */ 367 struct mana_txq *txq; 368 369 /* Taskqueue and related structs */ 370 struct task cleanup_task; 371 struct taskqueue *cleanup_tq; 372 int cpu; 373 bool do_not_ring_db; 374 375 /* Budget for one cleanup task */ 376 int work_done; 377 int budget; 378 379 /* Buffer which the CQ handler can copy the CQE's into. */ 380 struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER]; 381 }; 382 383 struct mana_recv_buf_oob { 384 /* A valid GDMA work request representing the data buffer. */ 385 struct gdma_wqe_request wqe_req; 386 387 struct mbuf *mbuf; 388 bus_dmamap_t dma_map; 389 390 /* SGL of the buffer going to be sent as part of the work request. */ 391 uint32_t num_sge; 392 struct gdma_sge sgl[MAX_RX_WQE_SGL_ENTRIES]; 393 394 /* Required to store the result of mana_gd_post_work_request. 395 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 396 * work queue when the WQE is consumed. 397 */ 398 struct gdma_posted_wqe_info wqe_inf; 399 }; 400 401 struct mana_rxq { 402 struct gdma_queue *gdma_rq; 403 /* Cache the gdma receive queue id */ 404 uint32_t gdma_id; 405 406 /* Index of RQ in the vPort, not gdma receive queue id */ 407 uint32_t rxq_idx; 408 409 uint32_t datasize; 410 411 mana_handle_t rxobj; 412 413 struct completion fence_event; 414 415 struct mana_cq rx_cq; 416 417 if_t ndev; 418 struct lro_ctrl lro; 419 420 /* Total number of receive buffers to be allocated */ 421 uint32_t num_rx_buf; 422 423 uint32_t buf_index; 424 425 struct mana_stats stats; 426 427 /* MUST BE THE LAST MEMBER: 428 * Each receive buffer has an associated mana_recv_buf_oob. 429 */ 430 struct mana_recv_buf_oob rx_oobs[]; 431 }; 432 433 struct mana_tx_qp { 434 struct mana_txq txq; 435 436 struct mana_cq tx_cq; 437 438 mana_handle_t tx_object; 439 }; 440 441 struct mana_port_stats { 442 counter_u64_t rx_packets; 443 counter_u64_t tx_packets; 444 445 counter_u64_t rx_bytes; 446 counter_u64_t tx_bytes; 447 448 counter_u64_t rx_drops; 449 counter_u64_t tx_drops; 450 451 counter_u64_t stop_queue; 452 counter_u64_t wake_queue; 453 }; 454 455 struct mana_context { 456 struct gdma_dev *gdma_dev; 457 458 uint16_t num_ports; 459 460 struct mana_eq *eqs; 461 462 if_t ports[MAX_PORTS_IN_MANA_DEV]; 463 }; 464 465 struct mana_port_context { 466 struct mana_context *ac; 467 if_t ndev; 468 struct ifmedia media; 469 470 struct sx apc_lock; 471 472 /* DMA tag used for queue bufs of the entire port */ 473 bus_dma_tag_t rx_buf_tag; 474 bus_dma_tag_t tx_buf_tag; 475 476 uint8_t mac_addr[ETHER_ADDR_LEN]; 477 478 enum TRI_STATE rss_state; 479 480 mana_handle_t default_rxobj; 481 bool tx_shortform_allowed; 482 uint16_t tx_vp_offset; 483 484 struct mana_tx_qp *tx_qp; 485 486 /* Indirection Table for RX & TX. The values are queue indexes */ 487 uint32_t indir_table[MANA_INDIRECT_TABLE_SIZE]; 488 489 /* Indirection table containing RxObject Handles */ 490 mana_handle_t rxobj_table[MANA_INDIRECT_TABLE_SIZE]; 491 492 /* Hash key used by the NIC */ 493 uint8_t hashkey[MANA_HASH_KEY_SIZE]; 494 495 /* This points to an array of num_queues of RQ pointers. */ 496 struct mana_rxq **rxqs; 497 498 /* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */ 499 unsigned int max_queues; 500 unsigned int num_queues; 501 502 mana_handle_t port_handle; 503 504 int vport_use_count; 505 506 uint16_t port_idx; 507 508 uint16_t frame_size; 509 510 bool port_is_up; 511 bool port_st_save; /* Saved port state */ 512 513 bool enable_tx_altq; 514 515 bool bind_cleanup_thread_cpu; 516 int last_tx_cq_bind_cpu; 517 int last_rx_cq_bind_cpu; 518 519 struct mana_port_stats port_stats; 520 521 struct sysctl_oid_list *port_list; 522 struct sysctl_ctx_list que_sysctl_ctx; 523 }; 524 525 #define MANA_APC_LOCK_INIT(apc) \ 526 sx_init(&(apc)->apc_lock, "MANA port lock") 527 #define MANA_APC_LOCK_DESTROY(apc) sx_destroy(&(apc)->apc_lock) 528 #define MANA_APC_LOCK_LOCK(apc) sx_xlock(&(apc)->apc_lock) 529 #define MANA_APC_LOCK_UNLOCK(apc) sx_unlock(&(apc)->apc_lock) 530 531 int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx, 532 bool update_hash, bool update_tab); 533 534 int mana_alloc_queues(if_t ndev); 535 int mana_attach(if_t ndev); 536 int mana_detach(if_t ndev); 537 538 int mana_probe(struct gdma_dev *gd); 539 void mana_remove(struct gdma_dev *gd); 540 541 struct mana_obj_spec { 542 uint32_t queue_index; 543 uint64_t gdma_region; 544 uint32_t queue_size; 545 uint32_t attached_eq; 546 uint32_t modr_ctx_id; 547 }; 548 549 enum mana_command_code { 550 MANA_QUERY_DEV_CONFIG = 0x20001, 551 MANA_QUERY_GF_STAT = 0x20002, 552 MANA_CONFIG_VPORT_TX = 0x20003, 553 MANA_CREATE_WQ_OBJ = 0x20004, 554 MANA_DESTROY_WQ_OBJ = 0x20005, 555 MANA_FENCE_RQ = 0x20006, 556 MANA_CONFIG_VPORT_RX = 0x20007, 557 MANA_QUERY_VPORT_CONFIG = 0x20008, 558 }; 559 560 /* Query Device Configuration */ 561 struct mana_query_device_cfg_req { 562 struct gdma_req_hdr hdr; 563 564 /* Driver Capability flags */ 565 uint64_t drv_cap_flags1; 566 uint64_t drv_cap_flags2; 567 uint64_t drv_cap_flags3; 568 uint64_t drv_cap_flags4; 569 570 uint32_t proto_major_ver; 571 uint32_t proto_minor_ver; 572 uint32_t proto_micro_ver; 573 574 uint32_t reserved; 575 }; /* HW DATA */ 576 577 struct mana_query_device_cfg_resp { 578 struct gdma_resp_hdr hdr; 579 580 uint64_t pf_cap_flags1; 581 uint64_t pf_cap_flags2; 582 uint64_t pf_cap_flags3; 583 uint64_t pf_cap_flags4; 584 585 uint16_t max_num_vports; 586 uint16_t reserved; 587 uint32_t max_num_eqs; 588 }; /* HW DATA */ 589 590 /* Query vPort Configuration */ 591 struct mana_query_vport_cfg_req { 592 struct gdma_req_hdr hdr; 593 uint32_t vport_index; 594 }; /* HW DATA */ 595 596 struct mana_query_vport_cfg_resp { 597 struct gdma_resp_hdr hdr; 598 uint32_t max_num_sq; 599 uint32_t max_num_rq; 600 uint32_t num_indirection_ent; 601 uint32_t reserved1; 602 uint8_t mac_addr[6]; 603 uint8_t reserved2[2]; 604 mana_handle_t vport; 605 }; /* HW DATA */ 606 607 /* Configure vPort */ 608 struct mana_config_vport_req { 609 struct gdma_req_hdr hdr; 610 mana_handle_t vport; 611 uint32_t pdid; 612 uint32_t doorbell_pageid; 613 }; /* HW DATA */ 614 615 struct mana_config_vport_resp { 616 struct gdma_resp_hdr hdr; 617 uint16_t tx_vport_offset; 618 uint8_t short_form_allowed; 619 uint8_t reserved; 620 }; /* HW DATA */ 621 622 /* Create WQ Object */ 623 struct mana_create_wqobj_req { 624 struct gdma_req_hdr hdr; 625 mana_handle_t vport; 626 uint32_t wq_type; 627 uint32_t reserved; 628 uint64_t wq_gdma_region; 629 uint64_t cq_gdma_region; 630 uint32_t wq_size; 631 uint32_t cq_size; 632 uint32_t cq_moderation_ctx_id; 633 uint32_t cq_parent_qid; 634 }; /* HW DATA */ 635 636 struct mana_create_wqobj_resp { 637 struct gdma_resp_hdr hdr; 638 uint32_t wq_id; 639 uint32_t cq_id; 640 mana_handle_t wq_obj; 641 }; /* HW DATA */ 642 643 /* Destroy WQ Object */ 644 struct mana_destroy_wqobj_req { 645 struct gdma_req_hdr hdr; 646 uint32_t wq_type; 647 uint32_t reserved; 648 mana_handle_t wq_obj_handle; 649 }; /* HW DATA */ 650 651 struct mana_destroy_wqobj_resp { 652 struct gdma_resp_hdr hdr; 653 }; /* HW DATA */ 654 655 /* Fence RQ */ 656 struct mana_fence_rq_req { 657 struct gdma_req_hdr hdr; 658 mana_handle_t wq_obj_handle; 659 }; /* HW DATA */ 660 661 struct mana_fence_rq_resp { 662 struct gdma_resp_hdr hdr; 663 }; /* HW DATA */ 664 665 /* Configure vPort Rx Steering */ 666 struct mana_cfg_rx_steer_req { 667 struct gdma_req_hdr hdr; 668 mana_handle_t vport; 669 uint16_t num_indir_entries; 670 uint16_t indir_tab_offset; 671 uint32_t rx_enable; 672 uint32_t rss_enable; 673 uint8_t update_default_rxobj; 674 uint8_t update_hashkey; 675 uint8_t update_indir_tab; 676 uint8_t reserved; 677 mana_handle_t default_rxobj; 678 uint8_t hashkey[MANA_HASH_KEY_SIZE]; 679 }; /* HW DATA */ 680 681 struct mana_cfg_rx_steer_resp { 682 struct gdma_resp_hdr hdr; 683 }; /* HW DATA */ 684 685 #define MANA_MAX_NUM_QUEUES 16 686 687 #define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1) 688 689 struct mana_tx_package { 690 struct gdma_wqe_request wqe_req; 691 struct gdma_sge sgl_array[MAX_MBUF_FRAGS]; 692 693 struct mana_tx_oob tx_oob; 694 695 struct gdma_posted_wqe_info wqe_info; 696 }; 697 698 int mana_restart(struct mana_port_context *apc); 699 700 int mana_create_wq_obj(struct mana_port_context *apc, 701 mana_handle_t vport, 702 uint32_t wq_type, struct mana_obj_spec *wq_spec, 703 struct mana_obj_spec *cq_spec, 704 mana_handle_t *wq_obj); 705 706 void mana_destroy_wq_obj(struct mana_port_context *apc, uint32_t wq_type, 707 mana_handle_t wq_obj); 708 709 int mana_cfg_vport(struct mana_port_context *apc, uint32_t protection_dom_id, 710 uint32_t doorbell_pg_id); 711 712 void mana_uncfg_vport(struct mana_port_context *apc); 713 #endif /* _MANA_H */ 714