1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Microsoft Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _MANA_H 33 #define _MANA_H 34 35 #include <sys/types.h> 36 #include <sys/proc.h> 37 #include <sys/socket.h> 38 #include <sys/sysctl.h> 39 #include <sys/taskqueue.h> 40 #include <sys/counter.h> 41 42 #include <net/ethernet.h> 43 #include <net/if.h> 44 #include <net/if_media.h> 45 #include <netinet/tcp_lro.h> 46 47 #include "gdma.h" 48 #include "hw_channel.h" 49 50 51 /* Microsoft Azure Network Adapter (MANA)'s definitions 52 * 53 * Structures labeled with "HW DATA" are exchanged with the hardware. All of 54 * them are naturally aligned and hence don't need __packed. 55 */ 56 /* MANA protocol version */ 57 #define MANA_MAJOR_VERSION 0 58 #define MANA_MINOR_VERSION 1 59 #define MANA_MICRO_VERSION 1 60 61 #define DRV_MODULE_NAME "mana" 62 63 #ifndef DRV_MODULE_VERSION 64 #define DRV_MODULE_VERSION \ 65 __XSTRING(MANA_MAJOR_VERSION) "." \ 66 __XSTRING(MANA_MINOR_VERSION) "." \ 67 __XSTRING(MANA_MICRO_VERSION) 68 #endif 69 #define DEVICE_NAME "Microsoft Azure Network Adapter (MANA)" 70 #define DEVICE_DESC "MANA adapter" 71 72 /* 73 * Supported PCI vendor and devices IDs 74 */ 75 #ifndef PCI_VENDOR_ID_MICROSOFT 76 #define PCI_VENDOR_ID_MICROSOFT 0x1414 77 #endif 78 79 #define PCI_DEV_ID_MANA_VF 0x00ba 80 81 typedef struct _mana_vendor_id_t { 82 uint16_t vendor_id; 83 uint16_t device_id; 84 } mana_vendor_id_t; 85 86 typedef uint64_t mana_handle_t; 87 #define INVALID_MANA_HANDLE ((mana_handle_t)-1) 88 89 enum TRI_STATE { 90 TRI_STATE_UNKNOWN = -1, 91 TRI_STATE_FALSE = 0, 92 TRI_STATE_TRUE = 1 93 }; 94 95 /* Number of entries for hardware indirection table must be in power of 2 */ 96 #define MANA_INDIRECT_TABLE_SIZE 64 97 #define MANA_INDIRECT_TABLE_MASK (MANA_INDIRECT_TABLE_SIZE - 1) 98 99 /* The Toeplitz hash key's length in bytes: should be multiple of 8 */ 100 #define MANA_HASH_KEY_SIZE 40 101 102 #define COMP_ENTRY_SIZE 64 103 104 #define MIN_FRAME_SIZE 146 105 #define ADAPTER_MTU_SIZE 1500 106 #define DEFAULT_FRAME_SIZE (ADAPTER_MTU_SIZE + 14) 107 #define MAX_FRAME_SIZE 4096 108 109 #define RX_BUFFERS_PER_QUEUE 512 110 111 #define MAX_SEND_BUFFERS_PER_QUEUE 256 112 113 #define EQ_SIZE (8 * PAGE_SIZE) 114 #define LOG2_EQ_THROTTLE 3 115 116 #define MAX_PORTS_IN_MANA_DEV 8 117 118 struct mana_send_buf_info { 119 struct mbuf *mbuf; 120 bus_dmamap_t dma_map; 121 122 /* Required to store the result of mana_gd_post_work_request. 123 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 124 * work queue when the WQE is consumed. 125 */ 126 struct gdma_posted_wqe_info wqe_inf; 127 }; 128 129 struct mana_stats { 130 counter_u64_t packets; /* rx, tx */ 131 counter_u64_t bytes; /* rx, tx */ 132 counter_u64_t stop; /* tx */ 133 counter_u64_t wakeup; /* tx */ 134 counter_u64_t collapse; /* tx */ 135 counter_u64_t collapse_err; /* tx */ 136 counter_u64_t dma_mapping_err; /* rx, tx */ 137 counter_u64_t mbuf_alloc_fail; /* rx */ 138 counter_u64_t alt_chg; /* tx */ 139 counter_u64_t alt_reset; /* tx */ 140 }; 141 142 struct mana_txq { 143 struct gdma_queue *gdma_sq; 144 145 union { 146 uint32_t gdma_txq_id; 147 struct { 148 uint32_t reserved1 :10; 149 uint32_t vsq_frame :14; 150 uint32_t reserved2 :8; 151 }; 152 }; 153 154 uint16_t vp_offset; 155 156 if_t ndev; 157 /* Store index to the array of tx_qp in port structure */ 158 int idx; 159 /* The alternative txq idx when this txq is under heavy load */ 160 int alt_txq_idx; 161 162 /* The mbufs are sent to the HW and we are waiting for the CQEs. */ 163 struct mana_send_buf_info *tx_buf_info; 164 uint16_t next_to_use; 165 uint16_t next_to_complete; 166 167 atomic_t pending_sends; 168 169 struct buf_ring *txq_br; 170 struct mtx txq_mtx; 171 char txq_mtx_name[16]; 172 173 uint64_t tso_pkts; 174 uint64_t tso_bytes; 175 176 struct task enqueue_task; 177 struct taskqueue *enqueue_tq; 178 179 struct mana_stats stats; 180 }; 181 182 183 /* 184 * Max WQE size is 512B. The first 8B is for GDMA Out of Band (OOB), 185 * next is the Client OOB can be either 8B or 24B. Thus, the max 186 * space for SGL entries in a singel WQE is 512 - 8 - 8 = 496B. Since each 187 * SGL is 16B in size, the max number of SGLs in a WQE is 496/16 = 31. 188 * Save one for emergency use, set the MAX_MBUF_FRAGS allowed to 30. 189 */ 190 #define MAX_MBUF_FRAGS 30 191 #define MANA_TSO_MAXSEG_SZ PAGE_SIZE 192 #define MANA_TSO_MAX_SZ IP_MAXPACKET 193 194 /* mbuf data and frags dma mappings */ 195 struct mana_mbuf_head { 196 bus_addr_t dma_handle[MAX_MBUF_FRAGS + 1]; 197 198 uint32_t size[MAX_MBUF_FRAGS + 1]; 199 }; 200 201 #define MANA_HEADROOM sizeof(struct mana_mbuf_head) 202 203 enum mana_tx_pkt_format { 204 MANA_SHORT_PKT_FMT = 0, 205 MANA_LONG_PKT_FMT = 1, 206 }; 207 208 struct mana_tx_short_oob { 209 uint32_t pkt_fmt :2; 210 uint32_t is_outer_ipv4 :1; 211 uint32_t is_outer_ipv6 :1; 212 uint32_t comp_iphdr_csum :1; 213 uint32_t comp_tcp_csum :1; 214 uint32_t comp_udp_csum :1; 215 uint32_t supress_txcqe_gen :1; 216 uint32_t vcq_num :24; 217 218 uint32_t trans_off :10; /* Transport header offset */ 219 uint32_t vsq_frame :14; 220 uint32_t short_vp_offset :8; 221 }; /* HW DATA */ 222 223 struct mana_tx_long_oob { 224 uint32_t is_encap :1; 225 uint32_t inner_is_ipv6 :1; 226 uint32_t inner_tcp_opt :1; 227 uint32_t inject_vlan_pri_tag :1; 228 uint32_t reserved1 :12; 229 uint32_t pcp :3; /* 802.1Q */ 230 uint32_t dei :1; /* 802.1Q */ 231 uint32_t vlan_id :12; /* 802.1Q */ 232 233 uint32_t inner_frame_offset :10; 234 uint32_t inner_ip_rel_offset :6; 235 uint32_t long_vp_offset :12; 236 uint32_t reserved2 :4; 237 238 uint32_t reserved3; 239 uint32_t reserved4; 240 }; /* HW DATA */ 241 242 struct mana_tx_oob { 243 struct mana_tx_short_oob s_oob; 244 struct mana_tx_long_oob l_oob; 245 }; /* HW DATA */ 246 247 enum mana_cq_type { 248 MANA_CQ_TYPE_RX, 249 MANA_CQ_TYPE_TX, 250 }; 251 252 enum mana_cqe_type { 253 CQE_INVALID = 0, 254 CQE_RX_OKAY = 1, 255 CQE_RX_COALESCED_4 = 2, 256 CQE_RX_OBJECT_FENCE = 3, 257 CQE_RX_TRUNCATED = 4, 258 259 CQE_TX_OKAY = 32, 260 CQE_TX_SA_DROP = 33, 261 CQE_TX_MTU_DROP = 34, 262 CQE_TX_INVALID_OOB = 35, 263 CQE_TX_INVALID_ETH_TYPE = 36, 264 CQE_TX_HDR_PROCESSING_ERROR = 37, 265 CQE_TX_VF_DISABLED = 38, 266 CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39, 267 CQE_TX_VPORT_DISABLED = 40, 268 CQE_TX_VLAN_TAGGING_VIOLATION = 41, 269 }; 270 271 #define MANA_CQE_COMPLETION 1 272 273 struct mana_cqe_header { 274 uint32_t cqe_type :6; 275 uint32_t client_type :2; 276 uint32_t vendor_err :24; 277 }; /* HW DATA */ 278 279 /* NDIS HASH Types */ 280 #define NDIS_HASH_IPV4 BIT(0) 281 #define NDIS_HASH_TCP_IPV4 BIT(1) 282 #define NDIS_HASH_UDP_IPV4 BIT(2) 283 #define NDIS_HASH_IPV6 BIT(3) 284 #define NDIS_HASH_TCP_IPV6 BIT(4) 285 #define NDIS_HASH_UDP_IPV6 BIT(5) 286 #define NDIS_HASH_IPV6_EX BIT(6) 287 #define NDIS_HASH_TCP_IPV6_EX BIT(7) 288 #define NDIS_HASH_UDP_IPV6_EX BIT(8) 289 290 #define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 291 #define MANA_HASH_L4 \ 292 (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \ 293 NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 294 295 #define NDIS_HASH_IPV4_L3_MASK (NDIS_HASH_IPV4) 296 #define NDIS_HASH_IPV4_L4_MASK (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4) 297 #define NDIS_HASH_IPV6_L3_MASK (NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 298 #define NDIS_HASH_IPV6_L4_MASK \ 299 (NDIS_HASH_TCP_IPV6 | NDIS_HASH_UDP_IPV6 | \ 300 NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 301 #define NDIS_HASH_IPV4_MASK \ 302 (NDIS_HASH_IPV4_L3_MASK | NDIS_HASH_IPV4_L4_MASK) 303 #define NDIS_HASH_IPV6_MASK \ 304 (NDIS_HASH_IPV6_L3_MASK | NDIS_HASH_IPV6_L4_MASK) 305 306 307 struct mana_rxcomp_perpkt_info { 308 uint32_t pkt_len :16; 309 uint32_t reserved1 :16; 310 uint32_t reserved2; 311 uint32_t pkt_hash; 312 }; /* HW DATA */ 313 314 #define MANA_RXCOMP_OOB_NUM_PPI 4 315 316 /* Receive completion OOB */ 317 struct mana_rxcomp_oob { 318 struct mana_cqe_header cqe_hdr; 319 320 uint32_t rx_vlan_id :12; 321 uint32_t rx_vlantag_present :1; 322 uint32_t rx_outer_iphdr_csum_succeed :1; 323 uint32_t rx_outer_iphdr_csum_fail :1; 324 uint32_t reserved1 :1; 325 uint32_t rx_hashtype :9; 326 uint32_t rx_iphdr_csum_succeed :1; 327 uint32_t rx_iphdr_csum_fail :1; 328 uint32_t rx_tcp_csum_succeed :1; 329 uint32_t rx_tcp_csum_fail :1; 330 uint32_t rx_udp_csum_succeed :1; 331 uint32_t rx_udp_csum_fail :1; 332 uint32_t reserved2 :1; 333 334 struct mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI]; 335 336 uint32_t rx_wqe_offset; 337 }; /* HW DATA */ 338 339 struct mana_tx_comp_oob { 340 struct mana_cqe_header cqe_hdr; 341 342 uint32_t tx_data_offset; 343 344 uint32_t tx_sgl_offset :5; 345 uint32_t tx_wqe_offset :27; 346 347 uint32_t reserved[12]; 348 }; /* HW DATA */ 349 350 struct mana_rxq; 351 352 #define CQE_POLLING_BUFFER 512 353 354 struct mana_cq { 355 struct gdma_queue *gdma_cq; 356 357 /* Cache the CQ id (used to verify if each CQE comes to the right CQ. */ 358 uint32_t gdma_id; 359 360 /* Type of the CQ: TX or RX */ 361 enum mana_cq_type type; 362 363 /* Pointer to the mana_rxq that is pushing RX CQEs to the queue. 364 * Only and must be non-NULL if type is MANA_CQ_TYPE_RX. 365 */ 366 struct mana_rxq *rxq; 367 368 /* Pointer to the mana_txq that is pushing TX CQEs to the queue. 369 * Only and must be non-NULL if type is MANA_CQ_TYPE_TX. 370 */ 371 struct mana_txq *txq; 372 373 /* Taskqueue and related structs */ 374 struct task cleanup_task; 375 struct taskqueue *cleanup_tq; 376 int cpu; 377 bool do_not_ring_db; 378 379 /* Budget for one cleanup task */ 380 int work_done; 381 int budget; 382 383 /* Buffer which the CQ handler can copy the CQE's into. */ 384 struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER]; 385 }; 386 387 struct mana_recv_buf_oob { 388 /* A valid GDMA work request representing the data buffer. */ 389 struct gdma_wqe_request wqe_req; 390 391 struct mbuf *mbuf; 392 bus_dmamap_t dma_map; 393 394 /* SGL of the buffer going to be sent as part of the work request. */ 395 uint32_t num_sge; 396 struct gdma_sge sgl[MAX_RX_WQE_SGL_ENTRIES]; 397 398 /* Required to store the result of mana_gd_post_work_request. 399 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 400 * work queue when the WQE is consumed. 401 */ 402 struct gdma_posted_wqe_info wqe_inf; 403 }; 404 405 struct mana_rxq { 406 struct gdma_queue *gdma_rq; 407 /* Cache the gdma receive queue id */ 408 uint32_t gdma_id; 409 410 /* Index of RQ in the vPort, not gdma receive queue id */ 411 uint32_t rxq_idx; 412 413 uint32_t datasize; 414 415 mana_handle_t rxobj; 416 417 struct completion fence_event; 418 419 struct mana_cq rx_cq; 420 421 if_t ndev; 422 struct lro_ctrl lro; 423 424 /* Total number of receive buffers to be allocated */ 425 uint32_t num_rx_buf; 426 427 uint32_t buf_index; 428 429 uint64_t lro_tried; 430 uint64_t lro_failed; 431 struct mana_stats stats; 432 433 /* MUST BE THE LAST MEMBER: 434 * Each receive buffer has an associated mana_recv_buf_oob. 435 */ 436 struct mana_recv_buf_oob rx_oobs[]; 437 }; 438 439 struct mana_tx_qp { 440 struct mana_txq txq; 441 442 struct mana_cq tx_cq; 443 444 mana_handle_t tx_object; 445 }; 446 447 struct mana_port_stats { 448 counter_u64_t rx_packets; 449 counter_u64_t tx_packets; 450 451 counter_u64_t rx_bytes; 452 counter_u64_t tx_bytes; 453 454 counter_u64_t rx_drops; 455 counter_u64_t tx_drops; 456 457 counter_u64_t stop_queue; 458 counter_u64_t wake_queue; 459 }; 460 461 struct mana_context { 462 struct gdma_dev *gdma_dev; 463 464 uint16_t num_ports; 465 466 struct mana_eq *eqs; 467 468 if_t ports[MAX_PORTS_IN_MANA_DEV]; 469 }; 470 471 struct mana_port_context { 472 struct mana_context *ac; 473 if_t ndev; 474 struct ifmedia media; 475 476 struct sx apc_lock; 477 478 /* DMA tag used for queue bufs of the entire port */ 479 bus_dma_tag_t rx_buf_tag; 480 bus_dma_tag_t tx_buf_tag; 481 482 uint8_t mac_addr[ETHER_ADDR_LEN]; 483 484 enum TRI_STATE rss_state; 485 486 mana_handle_t default_rxobj; 487 bool tx_shortform_allowed; 488 uint16_t tx_vp_offset; 489 490 struct mana_tx_qp *tx_qp; 491 492 /* Indirection Table for RX & TX. The values are queue indexes */ 493 uint32_t indir_table[MANA_INDIRECT_TABLE_SIZE]; 494 495 /* Indirection table containing RxObject Handles */ 496 mana_handle_t rxobj_table[MANA_INDIRECT_TABLE_SIZE]; 497 498 /* Hash key used by the NIC */ 499 uint8_t hashkey[MANA_HASH_KEY_SIZE]; 500 501 /* This points to an array of num_queues of RQ pointers. */ 502 struct mana_rxq **rxqs; 503 504 /* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */ 505 unsigned int max_queues; 506 unsigned int num_queues; 507 508 mana_handle_t port_handle; 509 510 int vport_use_count; 511 512 uint16_t port_idx; 513 514 uint16_t frame_size; 515 516 bool port_is_up; 517 bool port_st_save; /* Saved port state */ 518 519 bool enable_tx_altq; 520 521 bool bind_cleanup_thread_cpu; 522 int last_tx_cq_bind_cpu; 523 int last_rx_cq_bind_cpu; 524 525 struct mana_port_stats port_stats; 526 527 struct sysctl_oid_list *port_list; 528 struct sysctl_ctx_list que_sysctl_ctx; 529 }; 530 531 #define MANA_APC_LOCK_INIT(apc) \ 532 sx_init(&(apc)->apc_lock, "MANA port lock") 533 #define MANA_APC_LOCK_DESTROY(apc) sx_destroy(&(apc)->apc_lock) 534 #define MANA_APC_LOCK_LOCK(apc) sx_xlock(&(apc)->apc_lock) 535 #define MANA_APC_LOCK_UNLOCK(apc) sx_unlock(&(apc)->apc_lock) 536 537 int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx, 538 bool update_hash, bool update_tab); 539 540 int mana_alloc_queues(if_t ndev); 541 int mana_attach(if_t ndev); 542 int mana_detach(if_t ndev); 543 544 int mana_probe(struct gdma_dev *gd); 545 void mana_remove(struct gdma_dev *gd); 546 547 struct mana_obj_spec { 548 uint32_t queue_index; 549 uint64_t gdma_region; 550 uint32_t queue_size; 551 uint32_t attached_eq; 552 uint32_t modr_ctx_id; 553 }; 554 555 enum mana_command_code { 556 MANA_QUERY_DEV_CONFIG = 0x20001, 557 MANA_QUERY_GF_STAT = 0x20002, 558 MANA_CONFIG_VPORT_TX = 0x20003, 559 MANA_CREATE_WQ_OBJ = 0x20004, 560 MANA_DESTROY_WQ_OBJ = 0x20005, 561 MANA_FENCE_RQ = 0x20006, 562 MANA_CONFIG_VPORT_RX = 0x20007, 563 MANA_QUERY_VPORT_CONFIG = 0x20008, 564 }; 565 566 /* Query Device Configuration */ 567 struct mana_query_device_cfg_req { 568 struct gdma_req_hdr hdr; 569 570 /* Driver Capability flags */ 571 uint64_t drv_cap_flags1; 572 uint64_t drv_cap_flags2; 573 uint64_t drv_cap_flags3; 574 uint64_t drv_cap_flags4; 575 576 uint32_t proto_major_ver; 577 uint32_t proto_minor_ver; 578 uint32_t proto_micro_ver; 579 580 uint32_t reserved; 581 }; /* HW DATA */ 582 583 struct mana_query_device_cfg_resp { 584 struct gdma_resp_hdr hdr; 585 586 uint64_t pf_cap_flags1; 587 uint64_t pf_cap_flags2; 588 uint64_t pf_cap_flags3; 589 uint64_t pf_cap_flags4; 590 591 uint16_t max_num_vports; 592 uint16_t reserved; 593 uint32_t max_num_eqs; 594 }; /* HW DATA */ 595 596 /* Query vPort Configuration */ 597 struct mana_query_vport_cfg_req { 598 struct gdma_req_hdr hdr; 599 uint32_t vport_index; 600 }; /* HW DATA */ 601 602 struct mana_query_vport_cfg_resp { 603 struct gdma_resp_hdr hdr; 604 uint32_t max_num_sq; 605 uint32_t max_num_rq; 606 uint32_t num_indirection_ent; 607 uint32_t reserved1; 608 uint8_t mac_addr[6]; 609 uint8_t reserved2[2]; 610 mana_handle_t vport; 611 }; /* HW DATA */ 612 613 /* Configure vPort */ 614 struct mana_config_vport_req { 615 struct gdma_req_hdr hdr; 616 mana_handle_t vport; 617 uint32_t pdid; 618 uint32_t doorbell_pageid; 619 }; /* HW DATA */ 620 621 struct mana_config_vport_resp { 622 struct gdma_resp_hdr hdr; 623 uint16_t tx_vport_offset; 624 uint8_t short_form_allowed; 625 uint8_t reserved; 626 }; /* HW DATA */ 627 628 /* Create WQ Object */ 629 struct mana_create_wqobj_req { 630 struct gdma_req_hdr hdr; 631 mana_handle_t vport; 632 uint32_t wq_type; 633 uint32_t reserved; 634 uint64_t wq_gdma_region; 635 uint64_t cq_gdma_region; 636 uint32_t wq_size; 637 uint32_t cq_size; 638 uint32_t cq_moderation_ctx_id; 639 uint32_t cq_parent_qid; 640 }; /* HW DATA */ 641 642 struct mana_create_wqobj_resp { 643 struct gdma_resp_hdr hdr; 644 uint32_t wq_id; 645 uint32_t cq_id; 646 mana_handle_t wq_obj; 647 }; /* HW DATA */ 648 649 /* Destroy WQ Object */ 650 struct mana_destroy_wqobj_req { 651 struct gdma_req_hdr hdr; 652 uint32_t wq_type; 653 uint32_t reserved; 654 mana_handle_t wq_obj_handle; 655 }; /* HW DATA */ 656 657 struct mana_destroy_wqobj_resp { 658 struct gdma_resp_hdr hdr; 659 }; /* HW DATA */ 660 661 /* Fence RQ */ 662 struct mana_fence_rq_req { 663 struct gdma_req_hdr hdr; 664 mana_handle_t wq_obj_handle; 665 }; /* HW DATA */ 666 667 struct mana_fence_rq_resp { 668 struct gdma_resp_hdr hdr; 669 }; /* HW DATA */ 670 671 /* Configure vPort Rx Steering */ 672 struct mana_cfg_rx_steer_req { 673 struct gdma_req_hdr hdr; 674 mana_handle_t vport; 675 uint16_t num_indir_entries; 676 uint16_t indir_tab_offset; 677 uint32_t rx_enable; 678 uint32_t rss_enable; 679 uint8_t update_default_rxobj; 680 uint8_t update_hashkey; 681 uint8_t update_indir_tab; 682 uint8_t reserved; 683 mana_handle_t default_rxobj; 684 uint8_t hashkey[MANA_HASH_KEY_SIZE]; 685 }; /* HW DATA */ 686 687 struct mana_cfg_rx_steer_resp { 688 struct gdma_resp_hdr hdr; 689 }; /* HW DATA */ 690 691 #define MANA_MAX_NUM_QUEUES 16 692 693 #define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1) 694 695 struct mana_tx_package { 696 struct gdma_wqe_request wqe_req; 697 struct gdma_sge sgl_array[MAX_MBUF_FRAGS]; 698 699 struct mana_tx_oob tx_oob; 700 701 struct gdma_posted_wqe_info wqe_info; 702 }; 703 704 int mana_restart(struct mana_port_context *apc); 705 706 int mana_create_wq_obj(struct mana_port_context *apc, 707 mana_handle_t vport, 708 uint32_t wq_type, struct mana_obj_spec *wq_spec, 709 struct mana_obj_spec *cq_spec, 710 mana_handle_t *wq_obj); 711 712 void mana_destroy_wq_obj(struct mana_port_context *apc, uint32_t wq_type, 713 mana_handle_t wq_obj); 714 715 int mana_cfg_vport(struct mana_port_context *apc, uint32_t protection_dom_id, 716 uint32_t doorbell_pg_id); 717 718 void mana_uncfg_vport(struct mana_port_context *apc); 719 #endif /* _MANA_H */ 720