1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Microsoft Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _HW_CHANNEL_H 33 #define _HW_CHANNEL_H 34 35 #include <sys/sema.h> 36 37 #define DEFAULT_LOG2_THROTTLING_FOR_ERROR_EQ 4 38 39 #define HW_CHANNEL_MAX_REQUEST_SIZE 0x1000 40 #define HW_CHANNEL_MAX_RESPONSE_SIZE 0x1000 41 42 #define HW_CHANNEL_VF_BOOTSTRAP_QUEUE_DEPTH 1 43 44 #define HWC_INIT_DATA_CQID 1 45 #define HWC_INIT_DATA_RQID 2 46 #define HWC_INIT_DATA_SQID 3 47 #define HWC_INIT_DATA_QUEUE_DEPTH 4 48 #define HWC_INIT_DATA_MAX_REQUEST 5 49 #define HWC_INIT_DATA_MAX_RESPONSE 6 50 #define HWC_INIT_DATA_MAX_NUM_CQS 7 51 #define HWC_INIT_DATA_PDID 8 52 #define HWC_INIT_DATA_GPA_MKEY 9 53 54 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 55 * them are naturally aligned and hence don't need __packed. 56 */ 57 58 union hwc_init_eq_id_db { 59 uint32_t as_uint32; 60 61 struct { 62 uint32_t eq_id : 16; 63 uint32_t doorbell: 16; 64 }; 65 }; /* HW DATA */ 66 67 union hwc_init_type_data { 68 uint32_t as_uint32; 69 70 struct { 71 uint32_t value : 24; 72 uint32_t type : 8; 73 }; 74 }; /* HW DATA */ 75 76 struct hwc_rx_oob { 77 uint32_t type : 6; 78 uint32_t eom : 1; 79 uint32_t som : 1; 80 uint32_t vendor_err : 8; 81 uint32_t reserved1 : 16; 82 83 uint32_t src_virt_wq : 24; 84 uint32_t src_vfid : 8; 85 86 uint32_t reserved2; 87 88 union { 89 uint32_t wqe_addr_low; 90 uint32_t wqe_offset; 91 }; 92 93 uint32_t wqe_addr_high; 94 95 uint32_t client_data_unit : 14; 96 uint32_t reserved3 : 18; 97 98 uint32_t tx_oob_data_size; 99 100 uint32_t chunk_offset : 21; 101 uint32_t reserved4 : 11; 102 }; /* HW DATA */ 103 104 struct hwc_tx_oob { 105 uint32_t reserved1; 106 107 uint32_t reserved2; 108 109 uint32_t vrq_id : 24; 110 uint32_t dest_vfid : 8; 111 112 uint32_t vrcq_id : 24; 113 uint32_t reserved3 : 8; 114 115 uint32_t vscq_id : 24; 116 uint32_t loopback : 1; 117 uint32_t lso_override: 1; 118 uint32_t dest_pf : 1; 119 uint32_t reserved4 : 5; 120 121 uint32_t vsq_id : 24; 122 uint32_t reserved5 : 8; 123 }; /* HW DATA */ 124 125 struct hwc_work_request { 126 void *buf_va; 127 void *buf_sge_addr; 128 uint32_t buf_len; 129 uint32_t msg_size; 130 131 struct gdma_wqe_request wqe_req; 132 struct hwc_tx_oob tx_oob; 133 134 struct gdma_sge sge; 135 }; 136 137 /* hwc_dma_buf represents the array of in-flight WQEs. 138 * mem_info as know as the GDMA mapped memory is partitioned and used by 139 * in-flight WQEs. 140 * The number of WQEs is determined by the number of in-flight messages. 141 */ 142 struct hwc_dma_buf { 143 struct gdma_mem_info mem_info; 144 145 uint32_t gpa_mkey; 146 147 uint32_t num_reqs; 148 struct hwc_work_request reqs[]; 149 }; 150 151 typedef void hwc_rx_event_handler_t(void *ctx, uint32_t gdma_rxq_id, 152 const struct hwc_rx_oob *rx_oob); 153 154 typedef void hwc_tx_event_handler_t(void *ctx, uint32_t gdma_txq_id, 155 const struct hwc_rx_oob *rx_oob); 156 157 struct hwc_cq { 158 struct hw_channel_context *hwc; 159 160 struct gdma_queue *gdma_cq; 161 struct gdma_queue *gdma_eq; 162 struct gdma_comp *comp_buf; 163 uint16_t queue_depth; 164 165 hwc_rx_event_handler_t *rx_event_handler; 166 void *rx_event_ctx; 167 168 hwc_tx_event_handler_t *tx_event_handler; 169 void *tx_event_ctx; 170 }; 171 172 struct hwc_wq { 173 struct hw_channel_context *hwc; 174 175 struct gdma_queue *gdma_wq; 176 struct hwc_dma_buf *msg_buf; 177 uint16_t queue_depth; 178 179 struct hwc_cq *hwc_cq; 180 }; 181 182 struct hwc_caller_ctx { 183 struct completion comp_event; 184 void *output_buf; 185 uint32_t output_buflen; 186 187 uint32_t error; /* Error code */ 188 uint32_t status_code; 189 }; 190 191 struct hw_channel_context { 192 struct gdma_dev *gdma_dev; 193 device_t dev; 194 195 uint16_t num_inflight_msg; 196 uint32_t max_req_msg_size; 197 198 uint16_t hwc_init_q_depth_max; 199 uint32_t hwc_init_max_req_msg_size; 200 uint32_t hwc_init_max_resp_msg_size; 201 202 struct completion hwc_init_eqe_comp; 203 204 struct hwc_wq *rxq; 205 struct hwc_wq *txq; 206 struct hwc_cq *cq; 207 208 struct sema sema; 209 struct gdma_resource inflight_msg_res; 210 211 struct hwc_caller_ctx *caller_ctx; 212 }; 213 214 int mana_hwc_create_channel(struct gdma_context *gc); 215 void mana_hwc_destroy_channel(struct gdma_context *gc); 216 217 int mana_hwc_send_request(struct hw_channel_context *hwc, uint32_t req_len, 218 const void *req, uint32_t resp_len, void *resp); 219 220 #endif /* _HW_CHANNEL_H */ 221