1*ce110ea1SWei Hu /*- 2*ce110ea1SWei Hu * SPDX-License-Identifier: BSD-2-Clause 3*ce110ea1SWei Hu * 4*ce110ea1SWei Hu * Copyright (c) 2021 Microsoft Corp. 5*ce110ea1SWei Hu * All rights reserved. 6*ce110ea1SWei Hu * 7*ce110ea1SWei Hu * Redistribution and use in source and binary forms, with or without 8*ce110ea1SWei Hu * modification, are permitted provided that the following conditions 9*ce110ea1SWei Hu * are met: 10*ce110ea1SWei Hu * 11*ce110ea1SWei Hu * 1. Redistributions of source code must retain the above copyright 12*ce110ea1SWei Hu * notice, this list of conditions and the following disclaimer. 13*ce110ea1SWei Hu * 14*ce110ea1SWei Hu * 2. Redistributions in binary form must reproduce the above copyright 15*ce110ea1SWei Hu * notice, this list of conditions and the following disclaimer in the 16*ce110ea1SWei Hu * documentation and/or other materials provided with the distribution. 17*ce110ea1SWei Hu * 18*ce110ea1SWei Hu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19*ce110ea1SWei Hu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20*ce110ea1SWei Hu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21*ce110ea1SWei Hu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22*ce110ea1SWei Hu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23*ce110ea1SWei Hu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24*ce110ea1SWei Hu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25*ce110ea1SWei Hu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26*ce110ea1SWei Hu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27*ce110ea1SWei Hu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28*ce110ea1SWei Hu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29*ce110ea1SWei Hu * 30*ce110ea1SWei Hu */ 31*ce110ea1SWei Hu 32*ce110ea1SWei Hu #ifndef _HW_CHANNEL_H 33*ce110ea1SWei Hu #define _HW_CHANNEL_H 34*ce110ea1SWei Hu 35*ce110ea1SWei Hu #include <sys/sema.h> 36*ce110ea1SWei Hu 37*ce110ea1SWei Hu #define DEFAULT_LOG2_THROTTLING_FOR_ERROR_EQ 4 38*ce110ea1SWei Hu 39*ce110ea1SWei Hu #define HW_CHANNEL_MAX_REQUEST_SIZE 0x1000 40*ce110ea1SWei Hu #define HW_CHANNEL_MAX_RESPONSE_SIZE 0x1000 41*ce110ea1SWei Hu 42*ce110ea1SWei Hu #define HW_CHANNEL_VF_BOOTSTRAP_QUEUE_DEPTH 1 43*ce110ea1SWei Hu 44*ce110ea1SWei Hu #define HWC_INIT_DATA_CQID 1 45*ce110ea1SWei Hu #define HWC_INIT_DATA_RQID 2 46*ce110ea1SWei Hu #define HWC_INIT_DATA_SQID 3 47*ce110ea1SWei Hu #define HWC_INIT_DATA_QUEUE_DEPTH 4 48*ce110ea1SWei Hu #define HWC_INIT_DATA_MAX_REQUEST 5 49*ce110ea1SWei Hu #define HWC_INIT_DATA_MAX_RESPONSE 6 50*ce110ea1SWei Hu #define HWC_INIT_DATA_MAX_NUM_CQS 7 51*ce110ea1SWei Hu #define HWC_INIT_DATA_PDID 8 52*ce110ea1SWei Hu #define HWC_INIT_DATA_GPA_MKEY 9 53*ce110ea1SWei Hu 54*ce110ea1SWei Hu /* Structures labeled with "HW DATA" are exchanged with the hardware. All of 55*ce110ea1SWei Hu * them are naturally aligned and hence don't need __packed. 56*ce110ea1SWei Hu */ 57*ce110ea1SWei Hu 58*ce110ea1SWei Hu union hwc_init_eq_id_db { 59*ce110ea1SWei Hu uint32_t as_uint32; 60*ce110ea1SWei Hu 61*ce110ea1SWei Hu struct { 62*ce110ea1SWei Hu uint32_t eq_id : 16; 63*ce110ea1SWei Hu uint32_t doorbell: 16; 64*ce110ea1SWei Hu }; 65*ce110ea1SWei Hu }; /* HW DATA */ 66*ce110ea1SWei Hu 67*ce110ea1SWei Hu union hwc_init_type_data { 68*ce110ea1SWei Hu uint32_t as_uint32; 69*ce110ea1SWei Hu 70*ce110ea1SWei Hu struct { 71*ce110ea1SWei Hu uint32_t value : 24; 72*ce110ea1SWei Hu uint32_t type : 8; 73*ce110ea1SWei Hu }; 74*ce110ea1SWei Hu }; /* HW DATA */ 75*ce110ea1SWei Hu 76*ce110ea1SWei Hu struct hwc_rx_oob { 77*ce110ea1SWei Hu uint32_t type : 6; 78*ce110ea1SWei Hu uint32_t eom : 1; 79*ce110ea1SWei Hu uint32_t som : 1; 80*ce110ea1SWei Hu uint32_t vendor_err : 8; 81*ce110ea1SWei Hu uint32_t reserved1 : 16; 82*ce110ea1SWei Hu 83*ce110ea1SWei Hu uint32_t src_virt_wq : 24; 84*ce110ea1SWei Hu uint32_t src_vfid : 8; 85*ce110ea1SWei Hu 86*ce110ea1SWei Hu uint32_t reserved2; 87*ce110ea1SWei Hu 88*ce110ea1SWei Hu union { 89*ce110ea1SWei Hu uint32_t wqe_addr_low; 90*ce110ea1SWei Hu uint32_t wqe_offset; 91*ce110ea1SWei Hu }; 92*ce110ea1SWei Hu 93*ce110ea1SWei Hu uint32_t wqe_addr_high; 94*ce110ea1SWei Hu 95*ce110ea1SWei Hu uint32_t client_data_unit : 14; 96*ce110ea1SWei Hu uint32_t reserved3 : 18; 97*ce110ea1SWei Hu 98*ce110ea1SWei Hu uint32_t tx_oob_data_size; 99*ce110ea1SWei Hu 100*ce110ea1SWei Hu uint32_t chunk_offset : 21; 101*ce110ea1SWei Hu uint32_t reserved4 : 11; 102*ce110ea1SWei Hu }; /* HW DATA */ 103*ce110ea1SWei Hu 104*ce110ea1SWei Hu struct hwc_tx_oob { 105*ce110ea1SWei Hu uint32_t reserved1; 106*ce110ea1SWei Hu 107*ce110ea1SWei Hu uint32_t reserved2; 108*ce110ea1SWei Hu 109*ce110ea1SWei Hu uint32_t vrq_id : 24; 110*ce110ea1SWei Hu uint32_t dest_vfid : 8; 111*ce110ea1SWei Hu 112*ce110ea1SWei Hu uint32_t vrcq_id : 24; 113*ce110ea1SWei Hu uint32_t reserved3 : 8; 114*ce110ea1SWei Hu 115*ce110ea1SWei Hu uint32_t vscq_id : 24; 116*ce110ea1SWei Hu uint32_t loopback : 1; 117*ce110ea1SWei Hu uint32_t lso_override: 1; 118*ce110ea1SWei Hu uint32_t dest_pf : 1; 119*ce110ea1SWei Hu uint32_t reserved4 : 5; 120*ce110ea1SWei Hu 121*ce110ea1SWei Hu uint32_t vsq_id : 24; 122*ce110ea1SWei Hu uint32_t reserved5 : 8; 123*ce110ea1SWei Hu }; /* HW DATA */ 124*ce110ea1SWei Hu 125*ce110ea1SWei Hu struct hwc_work_request { 126*ce110ea1SWei Hu void *buf_va; 127*ce110ea1SWei Hu void *buf_sge_addr; 128*ce110ea1SWei Hu uint32_t buf_len; 129*ce110ea1SWei Hu uint32_t msg_size; 130*ce110ea1SWei Hu 131*ce110ea1SWei Hu struct gdma_wqe_request wqe_req; 132*ce110ea1SWei Hu struct hwc_tx_oob tx_oob; 133*ce110ea1SWei Hu 134*ce110ea1SWei Hu struct gdma_sge sge; 135*ce110ea1SWei Hu }; 136*ce110ea1SWei Hu 137*ce110ea1SWei Hu /* hwc_dma_buf represents the array of in-flight WQEs. 138*ce110ea1SWei Hu * mem_info as know as the GDMA mapped memory is partitioned and used by 139*ce110ea1SWei Hu * in-flight WQEs. 140*ce110ea1SWei Hu * The number of WQEs is determined by the number of in-flight messages. 141*ce110ea1SWei Hu */ 142*ce110ea1SWei Hu struct hwc_dma_buf { 143*ce110ea1SWei Hu struct gdma_mem_info mem_info; 144*ce110ea1SWei Hu 145*ce110ea1SWei Hu uint32_t gpa_mkey; 146*ce110ea1SWei Hu 147*ce110ea1SWei Hu uint32_t num_reqs; 148*ce110ea1SWei Hu struct hwc_work_request reqs[]; 149*ce110ea1SWei Hu }; 150*ce110ea1SWei Hu 151*ce110ea1SWei Hu typedef void hwc_rx_event_handler_t(void *ctx, uint32_t gdma_rxq_id, 152*ce110ea1SWei Hu const struct hwc_rx_oob *rx_oob); 153*ce110ea1SWei Hu 154*ce110ea1SWei Hu typedef void hwc_tx_event_handler_t(void *ctx, uint32_t gdma_txq_id, 155*ce110ea1SWei Hu const struct hwc_rx_oob *rx_oob); 156*ce110ea1SWei Hu 157*ce110ea1SWei Hu struct hwc_cq { 158*ce110ea1SWei Hu struct hw_channel_context *hwc; 159*ce110ea1SWei Hu 160*ce110ea1SWei Hu struct gdma_queue *gdma_cq; 161*ce110ea1SWei Hu struct gdma_queue *gdma_eq; 162*ce110ea1SWei Hu struct gdma_comp *comp_buf; 163*ce110ea1SWei Hu uint16_t queue_depth; 164*ce110ea1SWei Hu 165*ce110ea1SWei Hu hwc_rx_event_handler_t *rx_event_handler; 166*ce110ea1SWei Hu void *rx_event_ctx; 167*ce110ea1SWei Hu 168*ce110ea1SWei Hu hwc_tx_event_handler_t *tx_event_handler; 169*ce110ea1SWei Hu void *tx_event_ctx; 170*ce110ea1SWei Hu }; 171*ce110ea1SWei Hu 172*ce110ea1SWei Hu struct hwc_wq { 173*ce110ea1SWei Hu struct hw_channel_context *hwc; 174*ce110ea1SWei Hu 175*ce110ea1SWei Hu struct gdma_queue *gdma_wq; 176*ce110ea1SWei Hu struct hwc_dma_buf *msg_buf; 177*ce110ea1SWei Hu uint16_t queue_depth; 178*ce110ea1SWei Hu 179*ce110ea1SWei Hu struct hwc_cq *hwc_cq; 180*ce110ea1SWei Hu }; 181*ce110ea1SWei Hu 182*ce110ea1SWei Hu struct hwc_caller_ctx { 183*ce110ea1SWei Hu struct completion comp_event; 184*ce110ea1SWei Hu void *output_buf; 185*ce110ea1SWei Hu uint32_t output_buflen; 186*ce110ea1SWei Hu 187*ce110ea1SWei Hu uint32_t error; /* Error code */ 188*ce110ea1SWei Hu uint32_t status_code; 189*ce110ea1SWei Hu }; 190*ce110ea1SWei Hu 191*ce110ea1SWei Hu struct hw_channel_context { 192*ce110ea1SWei Hu struct gdma_dev *gdma_dev; 193*ce110ea1SWei Hu device_t dev; 194*ce110ea1SWei Hu 195*ce110ea1SWei Hu uint16_t num_inflight_msg; 196*ce110ea1SWei Hu uint32_t max_req_msg_size; 197*ce110ea1SWei Hu 198*ce110ea1SWei Hu uint16_t hwc_init_q_depth_max; 199*ce110ea1SWei Hu uint32_t hwc_init_max_req_msg_size; 200*ce110ea1SWei Hu uint32_t hwc_init_max_resp_msg_size; 201*ce110ea1SWei Hu 202*ce110ea1SWei Hu struct completion hwc_init_eqe_comp; 203*ce110ea1SWei Hu 204*ce110ea1SWei Hu struct hwc_wq *rxq; 205*ce110ea1SWei Hu struct hwc_wq *txq; 206*ce110ea1SWei Hu struct hwc_cq *cq; 207*ce110ea1SWei Hu 208*ce110ea1SWei Hu struct sema sema; 209*ce110ea1SWei Hu struct gdma_resource inflight_msg_res; 210*ce110ea1SWei Hu 211*ce110ea1SWei Hu struct hwc_caller_ctx *caller_ctx; 212*ce110ea1SWei Hu }; 213*ce110ea1SWei Hu 214*ce110ea1SWei Hu int mana_hwc_create_channel(struct gdma_context *gc); 215*ce110ea1SWei Hu void mana_hwc_destroy_channel(struct gdma_context *gc); 216*ce110ea1SWei Hu 217*ce110ea1SWei Hu int mana_hwc_send_request(struct hw_channel_context *hwc, uint32_t req_len, 218*ce110ea1SWei Hu const void *req, uint32_t resp_len, void *resp); 219*ce110ea1SWei Hu 220*ce110ea1SWei Hu #endif /* _HW_CHANNEL_H */ 221