1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Microsoft Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/kthread.h> 36 #include <sys/malloc.h> 37 #include <sys/mbuf.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/smp.h> 41 #include <sys/socket.h> 42 #include <sys/sysctl.h> 43 #include <sys/taskqueue.h> 44 #include <sys/time.h> 45 #include <sys/eventhandler.h> 46 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 #include <machine/in_cksum.h> 50 51 #include <net/if.h> 52 #include <net/if_var.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 57 #include "gdma_util.h" 58 #include "mana.h" 59 60 61 static mana_vendor_id_t mana_id_table[] = { 62 { PCI_VENDOR_ID_MICROSOFT, PCI_DEV_ID_MANA_VF}, 63 /* Last entry */ 64 { 0, 0} 65 }; 66 67 static inline uint32_t 68 mana_gd_r32(struct gdma_context *g, uint64_t offset) 69 { 70 uint32_t v = bus_space_read_4(g->gd_bus.bar0_t, 71 g->gd_bus.bar0_h, offset); 72 rmb(); 73 return (v); 74 } 75 76 #if defined(__amd64__) 77 static inline uint64_t 78 mana_gd_r64(struct gdma_context *g, uint64_t offset) 79 { 80 uint64_t v = bus_space_read_8(g->gd_bus.bar0_t, 81 g->gd_bus.bar0_h, offset); 82 rmb(); 83 return (v); 84 } 85 #else 86 static inline uint64_t 87 mana_gd_r64(struct gdma_context *g, uint64_t offset) 88 { 89 uint64_t v; 90 uint32_t *vp = (uint32_t *)&v; 91 92 *vp = mana_gd_r32(g, offset); 93 *(vp + 1) = mana_gd_r32(g, offset + 4); 94 rmb(); 95 return (v); 96 } 97 #endif 98 99 static int 100 mana_gd_query_max_resources(device_t dev) 101 { 102 struct gdma_context *gc = device_get_softc(dev); 103 struct gdma_query_max_resources_resp resp = {}; 104 struct gdma_general_req req = {}; 105 int err; 106 107 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 108 sizeof(req), sizeof(resp)); 109 110 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 111 if (err || resp.hdr.status) { 112 device_printf(gc->dev, 113 "Failed to query resource info: %d, 0x%x\n", 114 err, resp.hdr.status); 115 return err ? err : EPROTO; 116 } 117 118 mana_dbg(NULL, "max_msix %u, max_eq %u, max_cq %u, " 119 "max_sq %u, max_rq %u\n", 120 resp.max_msix, resp.max_eq, resp.max_cq, 121 resp.max_sq, resp.max_rq); 122 123 if (gc->num_msix_usable > resp.max_msix) 124 gc->num_msix_usable = resp.max_msix; 125 126 if (gc->num_msix_usable <= 1) 127 return ENOSPC; 128 129 gc->max_num_queues = mp_ncpus; 130 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 131 gc->max_num_queues = MANA_MAX_NUM_QUEUES; 132 133 if (gc->max_num_queues > resp.max_eq) 134 gc->max_num_queues = resp.max_eq; 135 136 if (gc->max_num_queues > resp.max_cq) 137 gc->max_num_queues = resp.max_cq; 138 139 if (gc->max_num_queues > resp.max_sq) 140 gc->max_num_queues = resp.max_sq; 141 142 if (gc->max_num_queues > resp.max_rq) 143 gc->max_num_queues = resp.max_rq; 144 145 return 0; 146 } 147 148 static int 149 mana_gd_detect_devices(device_t dev) 150 { 151 struct gdma_context *gc = device_get_softc(dev); 152 struct gdma_list_devices_resp resp = {}; 153 struct gdma_general_req req = {}; 154 struct gdma_dev_id gd_dev; 155 uint32_t i, max_num_devs; 156 uint16_t dev_type; 157 int err; 158 159 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 160 sizeof(resp)); 161 162 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 163 if (err || resp.hdr.status) { 164 device_printf(gc->dev, 165 "Failed to detect devices: %d, 0x%x\n", err, 166 resp.hdr.status); 167 return err ? err : EPROTO; 168 } 169 170 max_num_devs = min_t(uint32_t, MAX_NUM_GDMA_DEVICES, resp.num_of_devs); 171 172 for (i = 0; i < max_num_devs; i++) { 173 gd_dev = resp.devs[i]; 174 dev_type = gd_dev.type; 175 176 mana_dbg(NULL, "gdma dev %d, type %u\n", 177 i, dev_type); 178 179 /* HWC is already detected in mana_hwc_create_channel(). */ 180 if (dev_type == GDMA_DEVICE_HWC) 181 continue; 182 183 if (dev_type == GDMA_DEVICE_MANA) { 184 gc->mana.gdma_context = gc; 185 gc->mana.dev_id = gd_dev; 186 } 187 } 188 189 return gc->mana.dev_id.type == 0 ? ENODEV : 0; 190 } 191 192 int 193 mana_gd_send_request(struct gdma_context *gc, uint32_t req_len, 194 const void *req, uint32_t resp_len, void *resp) 195 { 196 struct hw_channel_context *hwc = gc->hwc.driver_data; 197 198 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 199 } 200 201 void 202 mana_gd_dma_map_paddr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 203 { 204 bus_addr_t *paddr = arg; 205 206 if (error) 207 return; 208 209 KASSERT(nseg == 1, ("too many segments %d!", nseg)); 210 *paddr = segs->ds_addr; 211 } 212 213 int 214 mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 215 struct gdma_mem_info *gmi) 216 { 217 bus_addr_t dma_handle; 218 void *buf; 219 int err; 220 221 if (!gc || !gmi) 222 return EINVAL; 223 224 if (length < PAGE_SIZE || !powerof2(length)) 225 return EINVAL; 226 227 err = bus_dma_tag_create(bus_get_dma_tag(gc->dev), /* parent */ 228 PAGE_SIZE, 0, /* alignment, boundary */ 229 BUS_SPACE_MAXADDR, /* lowaddr */ 230 BUS_SPACE_MAXADDR, /* highaddr */ 231 NULL, NULL, /* filter, filterarg */ 232 length, /* maxsize */ 233 1, /* nsegments */ 234 length, /* maxsegsize */ 235 0, /* flags */ 236 NULL, NULL, /* lockfunc, lockfuncarg*/ 237 &gmi->dma_tag); 238 if (err) { 239 device_printf(gc->dev, 240 "failed to create dma tag, err: %d\n", err); 241 return (err); 242 } 243 244 /* 245 * Must have BUS_DMA_ZERO flag to clear the dma memory. 246 * Otherwise the queue overflow detection mechanism does 247 * not work. 248 */ 249 err = bus_dmamem_alloc(gmi->dma_tag, &buf, 250 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &gmi->dma_map); 251 if (err) { 252 device_printf(gc->dev, 253 "failed to alloc dma mem, err: %d\n", err); 254 bus_dma_tag_destroy(gmi->dma_tag); 255 return (err); 256 } 257 258 err = bus_dmamap_load(gmi->dma_tag, gmi->dma_map, buf, 259 length, mana_gd_dma_map_paddr, &dma_handle, BUS_DMA_NOWAIT); 260 if (err) { 261 device_printf(gc->dev, 262 "failed to load dma mem, err: %d\n", err); 263 bus_dmamem_free(gmi->dma_tag, buf, gmi->dma_map); 264 bus_dma_tag_destroy(gmi->dma_tag); 265 return (err); 266 } 267 268 gmi->dev = gc->dev; 269 gmi->dma_handle = dma_handle; 270 gmi->virt_addr = buf; 271 gmi->length = length; 272 273 return 0; 274 } 275 276 void 277 mana_gd_free_memory(struct gdma_mem_info *gmi) 278 { 279 bus_dmamap_unload(gmi->dma_tag, gmi->dma_map); 280 bus_dmamem_free(gmi->dma_tag, gmi->virt_addr, gmi->dma_map); 281 bus_dma_tag_destroy(gmi->dma_tag); 282 } 283 284 int 285 mana_gd_destroy_doorbell_page(struct gdma_context *gc, int doorbell_page) 286 { 287 struct gdma_destroy_resource_range_req req = {}; 288 struct gdma_resp_hdr resp = {}; 289 int err; 290 291 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_RESOURCE_RANGE, 292 sizeof(req), sizeof(resp)); 293 294 req.resource_type = GDMA_RESOURCE_DOORBELL_PAGE; 295 req.num_resources = 1; 296 req.allocated_resources = doorbell_page; 297 298 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 299 if (err || resp.status) { 300 device_printf(gc->dev, 301 "Failed to destroy doorbell page: ret %d, 0x%x\n", 302 err, resp.status); 303 return err ? err : EPROTO; 304 } 305 306 return 0; 307 } 308 309 int 310 mana_gd_allocate_doorbell_page(struct gdma_context *gc, int *doorbell_page) 311 { 312 struct gdma_allocate_resource_range_req req = {}; 313 struct gdma_allocate_resource_range_resp resp = {}; 314 int err; 315 316 mana_gd_init_req_hdr(&req.hdr, GDMA_ALLOCATE_RESOURCE_RANGE, 317 sizeof(req), sizeof(resp)); 318 319 req.resource_type = GDMA_RESOURCE_DOORBELL_PAGE; 320 req.num_resources = 1; 321 req.alignment = 1; 322 323 /* Have GDMA start searching from 0 */ 324 req.allocated_resources = 0; 325 326 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 327 if (err || resp.hdr.status) { 328 device_printf(gc->dev, 329 "Failed to allocate doorbell page: ret %d, 0x%x\n", 330 err, resp.hdr.status); 331 return err ? err : EPROTO; 332 } 333 334 *doorbell_page = resp.allocated_resources; 335 336 return 0; 337 } 338 339 static int 340 mana_gd_create_hw_eq(struct gdma_context *gc, 341 struct gdma_queue *queue) 342 { 343 struct gdma_create_queue_resp resp = {}; 344 struct gdma_create_queue_req req = {}; 345 int err; 346 347 if (queue->type != GDMA_EQ) 348 return EINVAL; 349 350 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 351 sizeof(req), sizeof(resp)); 352 353 req.hdr.dev_id = queue->gdma_dev->dev_id; 354 req.type = queue->type; 355 req.pdid = queue->gdma_dev->pdid; 356 req.doolbell_id = queue->gdma_dev->doorbell; 357 req.gdma_region = queue->mem_info.dma_region_handle; 358 req.queue_size = queue->queue_size; 359 req.log2_throttle_limit = queue->eq.log2_throttle_limit; 360 req.eq_pci_msix_index = queue->eq.msix_index; 361 362 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 363 if (err || resp.hdr.status) { 364 device_printf(gc->dev, 365 "Failed to create queue: %d, 0x%x\n", 366 err, resp.hdr.status); 367 return err ? err : EPROTO; 368 } 369 370 queue->id = resp.queue_index; 371 queue->eq.disable_needed = true; 372 queue->mem_info.dma_region_handle = GDMA_INVALID_DMA_REGION; 373 return 0; 374 } 375 376 static 377 int mana_gd_disable_queue(struct gdma_queue *queue) 378 { 379 struct gdma_context *gc = queue->gdma_dev->gdma_context; 380 struct gdma_disable_queue_req req = {}; 381 struct gdma_general_resp resp = {}; 382 int err; 383 384 if (queue->type != GDMA_EQ) 385 mana_warn(NULL, "Not event queue type 0x%x\n", 386 queue->type); 387 388 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 389 sizeof(req), sizeof(resp)); 390 391 req.hdr.dev_id = queue->gdma_dev->dev_id; 392 req.type = queue->type; 393 req.queue_index = queue->id; 394 req.alloc_res_id_on_creation = 1; 395 396 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 397 if (err || resp.hdr.status) { 398 device_printf(gc->dev, 399 "Failed to disable queue: %d, 0x%x\n", err, 400 resp.hdr.status); 401 return err ? err : EPROTO; 402 } 403 404 return 0; 405 } 406 407 #define DOORBELL_OFFSET_SQ 0x0 408 #define DOORBELL_OFFSET_RQ 0x400 409 #define DOORBELL_OFFSET_CQ 0x800 410 #define DOORBELL_OFFSET_EQ 0xFF8 411 412 static void 413 mana_gd_ring_doorbell(struct gdma_context *gc, uint32_t db_index, 414 enum gdma_queue_type q_type, uint32_t qid, 415 uint32_t tail_ptr, uint8_t num_req) 416 { 417 union gdma_doorbell_entry e = {}; 418 void __iomem *addr; 419 420 addr = (char *)gc->db_page_base + gc->db_page_size * db_index; 421 switch (q_type) { 422 case GDMA_EQ: 423 e.eq.id = qid; 424 e.eq.tail_ptr = tail_ptr; 425 e.eq.arm = num_req; 426 427 addr = (char *)addr + DOORBELL_OFFSET_EQ; 428 break; 429 430 case GDMA_CQ: 431 e.cq.id = qid; 432 e.cq.tail_ptr = tail_ptr; 433 e.cq.arm = num_req; 434 435 addr = (char *)addr + DOORBELL_OFFSET_CQ; 436 break; 437 438 case GDMA_RQ: 439 e.rq.id = qid; 440 e.rq.tail_ptr = tail_ptr; 441 e.rq.wqe_cnt = num_req; 442 443 addr = (char *)addr + DOORBELL_OFFSET_RQ; 444 break; 445 446 case GDMA_SQ: 447 e.sq.id = qid; 448 e.sq.tail_ptr = tail_ptr; 449 450 addr = (char *)addr + DOORBELL_OFFSET_SQ; 451 break; 452 453 default: 454 mana_warn(NULL, "Invalid queue type 0x%x\n", q_type); 455 return; 456 } 457 458 /* Ensure all writes are done before ring doorbell */ 459 wmb(); 460 461 #if defined(__amd64__) 462 writeq(addr, e.as_uint64); 463 #else 464 uint32_t *p = (uint32_t *)&e.as_uint64; 465 writel(addr, *p); 466 writel((char *)addr + 4, *(p + 1)); 467 #endif 468 } 469 470 void 471 mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 472 { 473 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 474 queue->id, queue->head * GDMA_WQE_BU_SIZE, 0); 475 } 476 477 void 478 mana_gd_ring_cq(struct gdma_queue *cq, uint8_t arm_bit) 479 { 480 struct gdma_context *gc = cq->gdma_dev->gdma_context; 481 482 uint32_t num_cqe = cq->queue_size / GDMA_CQE_SIZE; 483 484 uint32_t head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 485 486 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 487 head, arm_bit); 488 } 489 490 static void 491 mana_gd_process_eqe(struct gdma_queue *eq) 492 { 493 uint32_t head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 494 struct gdma_context *gc = eq->gdma_dev->gdma_context; 495 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 496 union gdma_eqe_info eqe_info; 497 enum gdma_eqe_type type; 498 struct gdma_event event; 499 struct gdma_queue *cq; 500 struct gdma_eqe *eqe; 501 uint32_t cq_id; 502 503 eqe = &eq_eqe_ptr[head]; 504 eqe_info.as_uint32 = eqe->eqe_info; 505 type = eqe_info.type; 506 507 switch (type) { 508 case GDMA_EQE_COMPLETION: 509 cq_id = eqe->details[0] & 0xFFFFFF; 510 if (cq_id >= gc->max_num_cqs) { 511 mana_warn(NULL, 512 "failed: cq_id %u > max_num_cqs %u\n", 513 cq_id, gc->max_num_cqs); 514 break; 515 } 516 517 cq = gc->cq_table[cq_id]; 518 if (!cq || cq->type != GDMA_CQ || cq->id != cq_id) { 519 mana_warn(NULL, 520 "failed: invalid cq_id %u\n", cq_id); 521 break; 522 } 523 524 if (cq->cq.callback) 525 cq->cq.callback(cq->cq.context, cq); 526 527 break; 528 529 case GDMA_EQE_TEST_EVENT: 530 gc->test_event_eq_id = eq->id; 531 532 mana_dbg(NULL, 533 "EQE TEST EVENT received for EQ %u\n", eq->id); 534 535 complete(&gc->eq_test_event); 536 break; 537 538 case GDMA_EQE_HWC_INIT_EQ_ID_DB: 539 case GDMA_EQE_HWC_INIT_DATA: 540 case GDMA_EQE_HWC_INIT_DONE: 541 if (!eq->eq.callback) 542 break; 543 544 event.type = type; 545 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 546 eq->eq.callback(eq->eq.context, eq, &event); 547 break; 548 549 default: 550 break; 551 } 552 } 553 554 static void 555 mana_gd_process_eq_events(void *arg) 556 { 557 uint32_t owner_bits, new_bits, old_bits; 558 union gdma_eqe_info eqe_info; 559 struct gdma_eqe *eq_eqe_ptr; 560 struct gdma_queue *eq = arg; 561 struct gdma_context *gc; 562 uint32_t head, num_eqe; 563 struct gdma_eqe *eqe; 564 int i, j; 565 566 gc = eq->gdma_dev->gdma_context; 567 568 num_eqe = eq->queue_size / GDMA_EQE_SIZE; 569 eq_eqe_ptr = eq->queue_mem_ptr; 570 571 bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 572 BUS_DMASYNC_POSTREAD); 573 574 /* Process up to 5 EQEs at a time, and update the HW head. */ 575 for (i = 0; i < 5; i++) { 576 eqe = &eq_eqe_ptr[eq->head % num_eqe]; 577 eqe_info.as_uint32 = eqe->eqe_info; 578 owner_bits = eqe_info.owner_bits; 579 580 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 581 582 /* No more entries */ 583 if (owner_bits == old_bits) 584 break; 585 586 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 587 if (owner_bits != new_bits) { 588 /* Something wrong. Log for debugging purpose */ 589 device_printf(gc->dev, 590 "EQ %d: overflow detected, " 591 "i = %d, eq->head = %u " 592 "got owner_bits = %u, new_bits = %u " 593 "eqe addr %p, eqe->eqe_info 0x%x, " 594 "eqe type = %x, reserved1 = %x, client_id = %x, " 595 "reserved2 = %x, owner_bits = %x\n", 596 eq->id, i, eq->head, 597 owner_bits, new_bits, 598 eqe, eqe->eqe_info, 599 eqe_info.type, eqe_info.reserved1, 600 eqe_info.client_id, eqe_info.reserved2, 601 eqe_info.owner_bits); 602 603 uint32_t *eqe_dump = (uint32_t *) eq_eqe_ptr; 604 for (j = 0; j < 20; j++) { 605 device_printf(gc->dev, "%p: %x\t%x\t%x\t%x\n", 606 &eqe_dump[j * 4], eqe_dump[j * 4], eqe_dump[j * 4 + 1], 607 eqe_dump[j * 4 + 2], eqe_dump[j * 4 + 3]); 608 } 609 break; 610 } 611 612 rmb(); 613 614 mana_gd_process_eqe(eq); 615 616 eq->head++; 617 } 618 619 bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 620 BUS_DMASYNC_PREREAD); 621 622 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 623 624 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 625 head, SET_ARM_BIT); 626 } 627 628 static int 629 mana_gd_register_irq(struct gdma_queue *queue, 630 const struct gdma_queue_spec *spec) 631 { 632 struct gdma_dev *gd = queue->gdma_dev; 633 struct gdma_irq_context *gic; 634 struct gdma_context *gc; 635 struct gdma_resource *r; 636 unsigned int msi_index; 637 int err; 638 639 gc = gd->gdma_context; 640 r = &gc->msix_resource; 641 642 mtx_lock_spin(&r->lock_spin); 643 644 msi_index = find_first_zero_bit(r->map, r->size); 645 if (msi_index >= r->size) { 646 err = ENOSPC; 647 } else { 648 bitmap_set(r->map, msi_index, 1); 649 queue->eq.msix_index = msi_index; 650 err = 0; 651 } 652 653 mtx_unlock_spin(&r->lock_spin); 654 655 if (err) 656 return err; 657 658 if (unlikely(msi_index >= gc->num_msix_usable)) { 659 device_printf(gc->dev, 660 "chose an invalid msix index %d, usable %d\n", 661 msi_index, gc->num_msix_usable); 662 return ENOSPC; 663 } 664 665 gic = &gc->irq_contexts[msi_index]; 666 667 if (unlikely(gic->handler || gic->arg)) { 668 device_printf(gc->dev, 669 "interrupt handler or arg already assigned, " 670 "msix index: %d\n", msi_index); 671 } 672 673 gic->arg = queue; 674 675 gic->handler = mana_gd_process_eq_events; 676 677 mana_dbg(NULL, "registered msix index %d vector %d irq %ju\n", 678 msi_index, gic->msix_e.vector, rman_get_start(gic->res)); 679 680 return 0; 681 } 682 683 static void 684 mana_gd_deregiser_irq(struct gdma_queue *queue) 685 { 686 struct gdma_dev *gd = queue->gdma_dev; 687 struct gdma_irq_context *gic; 688 struct gdma_context *gc; 689 struct gdma_resource *r; 690 unsigned int msix_index; 691 692 gc = gd->gdma_context; 693 r = &gc->msix_resource; 694 695 /* At most num_online_cpus() + 1 interrupts are used. */ 696 msix_index = queue->eq.msix_index; 697 if (unlikely(msix_index >= gc->num_msix_usable)) 698 return; 699 700 gic = &gc->irq_contexts[msix_index]; 701 gic->handler = NULL; 702 gic->arg = NULL; 703 704 mtx_lock_spin(&r->lock_spin); 705 bitmap_clear(r->map, msix_index, 1); 706 mtx_unlock_spin(&r->lock_spin); 707 708 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 709 710 mana_dbg(NULL, "deregistered msix index %d vector %d irq %ju\n", 711 msix_index, gic->msix_e.vector, rman_get_start(gic->res)); 712 } 713 714 int 715 mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 716 { 717 struct gdma_generate_test_event_req req = {}; 718 struct gdma_general_resp resp = {}; 719 device_t dev = gc->dev; 720 int err; 721 722 sx_xlock(&gc->eq_test_event_sx); 723 724 init_completion(&gc->eq_test_event); 725 gc->test_event_eq_id = INVALID_QUEUE_ID; 726 727 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 728 sizeof(req), sizeof(resp)); 729 730 req.hdr.dev_id = eq->gdma_dev->dev_id; 731 req.queue_index = eq->id; 732 733 err = mana_gd_send_request(gc, sizeof(req), &req, 734 sizeof(resp), &resp); 735 if (err) { 736 device_printf(dev, "test_eq failed: %d\n", err); 737 goto out; 738 } 739 740 err = EPROTO; 741 742 if (resp.hdr.status) { 743 device_printf(dev, "test_eq failed: 0x%x\n", 744 resp.hdr.status); 745 goto out; 746 } 747 748 if (wait_for_completion_timeout(&gc->eq_test_event, 30 * hz)) { 749 device_printf(dev, "test_eq timed out on queue %d\n", 750 eq->id); 751 goto out; 752 } 753 754 if (eq->id != gc->test_event_eq_id) { 755 device_printf(dev, 756 "test_eq got an event on wrong queue %d (%d)\n", 757 gc->test_event_eq_id, eq->id); 758 goto out; 759 } 760 761 err = 0; 762 out: 763 sx_xunlock(&gc->eq_test_event_sx); 764 return err; 765 } 766 767 static void 768 mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 769 struct gdma_queue *queue) 770 { 771 int err; 772 773 if (flush_evenets) { 774 err = mana_gd_test_eq(gc, queue); 775 if (err) 776 device_printf(gc->dev, 777 "Failed to flush EQ: %d\n", err); 778 } 779 780 mana_gd_deregiser_irq(queue); 781 782 if (queue->eq.disable_needed) 783 mana_gd_disable_queue(queue); 784 } 785 786 static int mana_gd_create_eq(struct gdma_dev *gd, 787 const struct gdma_queue_spec *spec, 788 bool create_hwq, struct gdma_queue *queue) 789 { 790 struct gdma_context *gc = gd->gdma_context; 791 device_t dev = gc->dev; 792 uint32_t log2_num_entries; 793 int err; 794 795 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 796 797 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 798 799 if (spec->eq.log2_throttle_limit > log2_num_entries) { 800 device_printf(dev, 801 "EQ throttling limit (%lu) > maximum EQE (%u)\n", 802 spec->eq.log2_throttle_limit, log2_num_entries); 803 return EINVAL; 804 } 805 806 err = mana_gd_register_irq(queue, spec); 807 if (err) { 808 device_printf(dev, "Failed to register irq: %d\n", err); 809 return err; 810 } 811 812 queue->eq.callback = spec->eq.callback; 813 queue->eq.context = spec->eq.context; 814 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 815 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 816 817 if (create_hwq) { 818 err = mana_gd_create_hw_eq(gc, queue); 819 if (err) 820 goto out; 821 822 err = mana_gd_test_eq(gc, queue); 823 if (err) 824 goto out; 825 } 826 827 return 0; 828 out: 829 device_printf(dev, "Failed to create EQ: %d\n", err); 830 mana_gd_destroy_eq(gc, false, queue); 831 return err; 832 } 833 834 static void 835 mana_gd_create_cq(const struct gdma_queue_spec *spec, 836 struct gdma_queue *queue) 837 { 838 uint32_t log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 839 840 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 841 queue->cq.parent = spec->cq.parent_eq; 842 queue->cq.context = spec->cq.context; 843 queue->cq.callback = spec->cq.callback; 844 } 845 846 static void 847 mana_gd_destroy_cq(struct gdma_context *gc, 848 struct gdma_queue *queue) 849 { 850 uint32_t id = queue->id; 851 852 if (id >= gc->max_num_cqs) 853 return; 854 855 if (!gc->cq_table[id]) 856 return; 857 858 gc->cq_table[id] = NULL; 859 } 860 861 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 862 const struct gdma_queue_spec *spec, 863 struct gdma_queue **queue_ptr) 864 { 865 struct gdma_context *gc = gd->gdma_context; 866 struct gdma_mem_info *gmi; 867 struct gdma_queue *queue; 868 int err; 869 870 queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 871 gmi = &queue->mem_info; 872 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 873 if (err) 874 goto free_q; 875 876 queue->head = 0; 877 queue->tail = 0; 878 queue->queue_mem_ptr = gmi->virt_addr; 879 queue->queue_size = spec->queue_size; 880 queue->monitor_avl_buf = spec->monitor_avl_buf; 881 queue->type = spec->type; 882 queue->gdma_dev = gd; 883 884 if (spec->type == GDMA_EQ) 885 err = mana_gd_create_eq(gd, spec, false, queue); 886 else if (spec->type == GDMA_CQ) 887 mana_gd_create_cq(spec, queue); 888 889 if (err) 890 goto out; 891 892 *queue_ptr = queue; 893 return 0; 894 out: 895 mana_gd_free_memory(gmi); 896 free_q: 897 free(queue, M_DEVBUF); 898 return err; 899 } 900 901 int 902 mana_gd_destroy_dma_region(struct gdma_context *gc, 903 gdma_obj_handle_t dma_region_handle) 904 { 905 struct gdma_destroy_dma_region_req req = {}; 906 struct gdma_general_resp resp = {}; 907 int err; 908 909 if (dma_region_handle == GDMA_INVALID_DMA_REGION) 910 return 0; 911 912 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 913 sizeof(resp)); 914 req.dma_region_handle = dma_region_handle; 915 916 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), 917 &resp); 918 if (err || resp.hdr.status) { 919 device_printf(gc->dev, 920 "Failed to destroy DMA region: %d, 0x%x\n", 921 err, resp.hdr.status); 922 return EPROTO; 923 } 924 925 return 0; 926 } 927 928 static int 929 mana_gd_create_dma_region(struct gdma_dev *gd, 930 struct gdma_mem_info *gmi) 931 { 932 unsigned int num_page = gmi->length / PAGE_SIZE; 933 struct gdma_create_dma_region_req *req = NULL; 934 struct gdma_create_dma_region_resp resp = {}; 935 struct gdma_context *gc = gd->gdma_context; 936 struct hw_channel_context *hwc; 937 uint32_t length = gmi->length; 938 uint32_t req_msg_size; 939 int err; 940 int i; 941 942 if (length < PAGE_SIZE || !powerof2(length)) { 943 mana_err(NULL, "gmi size incorrect: %u\n", length); 944 return EINVAL; 945 } 946 947 if (offset_in_page((uintptr_t)gmi->virt_addr) != 0) { 948 mana_err(NULL, "gmi not page aligned: %p\n", 949 gmi->virt_addr); 950 return EINVAL; 951 } 952 953 hwc = gc->hwc.driver_data; 954 req_msg_size = sizeof(*req) + num_page * sizeof(uint64_t); 955 if (req_msg_size > hwc->max_req_msg_size) { 956 mana_err(NULL, "req msg size too large: %u, %u\n", 957 req_msg_size, hwc->max_req_msg_size); 958 return EINVAL; 959 } 960 961 req = malloc(req_msg_size, M_DEVBUF, M_WAITOK | M_ZERO); 962 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 963 req_msg_size, sizeof(resp)); 964 req->length = length; 965 req->offset_in_page = 0; 966 req->gdma_page_type = GDMA_PAGE_TYPE_4K; 967 req->page_count = num_page; 968 req->page_addr_list_len = num_page; 969 970 for (i = 0; i < num_page; i++) 971 req->page_addr_list[i] = gmi->dma_handle + i * PAGE_SIZE; 972 973 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 974 if (err) 975 goto out; 976 977 if (resp.hdr.status || 978 resp.dma_region_handle == GDMA_INVALID_DMA_REGION) { 979 device_printf(gc->dev, "Failed to create DMA region: 0x%x\n", 980 resp.hdr.status); 981 err = EPROTO; 982 goto out; 983 } 984 985 gmi->dma_region_handle = resp.dma_region_handle; 986 out: 987 free(req, M_DEVBUF); 988 return err; 989 } 990 991 int 992 mana_gd_create_mana_eq(struct gdma_dev *gd, 993 const struct gdma_queue_spec *spec, 994 struct gdma_queue **queue_ptr) 995 { 996 struct gdma_context *gc = gd->gdma_context; 997 struct gdma_mem_info *gmi; 998 struct gdma_queue *queue; 999 int err; 1000 1001 if (spec->type != GDMA_EQ) 1002 return EINVAL; 1003 1004 queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 1005 gmi = &queue->mem_info; 1006 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 1007 if (err) 1008 goto free_q; 1009 1010 err = mana_gd_create_dma_region(gd, gmi); 1011 if (err) 1012 goto out; 1013 1014 queue->head = 0; 1015 queue->tail = 0; 1016 queue->queue_mem_ptr = gmi->virt_addr; 1017 queue->queue_size = spec->queue_size; 1018 queue->monitor_avl_buf = spec->monitor_avl_buf; 1019 queue->type = spec->type; 1020 queue->gdma_dev = gd; 1021 1022 err = mana_gd_create_eq(gd, spec, true, queue); 1023 if (err) 1024 goto out; 1025 1026 *queue_ptr = queue; 1027 return 0; 1028 1029 out: 1030 mana_gd_free_memory(gmi); 1031 free_q: 1032 free(queue, M_DEVBUF); 1033 return err; 1034 } 1035 1036 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 1037 const struct gdma_queue_spec *spec, 1038 struct gdma_queue **queue_ptr) 1039 { 1040 struct gdma_context *gc = gd->gdma_context; 1041 struct gdma_mem_info *gmi; 1042 struct gdma_queue *queue; 1043 int err; 1044 1045 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 1046 spec->type != GDMA_RQ) 1047 return EINVAL; 1048 1049 queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 1050 gmi = &queue->mem_info; 1051 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 1052 if (err) 1053 goto free_q; 1054 1055 err = mana_gd_create_dma_region(gd, gmi); 1056 if (err) 1057 goto out; 1058 1059 queue->head = 0; 1060 queue->tail = 0; 1061 queue->queue_mem_ptr = gmi->virt_addr; 1062 queue->queue_size = spec->queue_size; 1063 queue->monitor_avl_buf = spec->monitor_avl_buf; 1064 queue->type = spec->type; 1065 queue->gdma_dev = gd; 1066 1067 if (spec->type == GDMA_CQ) 1068 mana_gd_create_cq(spec, queue); 1069 1070 *queue_ptr = queue; 1071 return 0; 1072 1073 out: 1074 mana_gd_free_memory(gmi); 1075 free_q: 1076 free(queue, M_DEVBUF); 1077 return err; 1078 } 1079 1080 void 1081 mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 1082 { 1083 struct gdma_mem_info *gmi = &queue->mem_info; 1084 1085 switch (queue->type) { 1086 case GDMA_EQ: 1087 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 1088 break; 1089 1090 case GDMA_CQ: 1091 mana_gd_destroy_cq(gc, queue); 1092 break; 1093 1094 case GDMA_RQ: 1095 break; 1096 1097 case GDMA_SQ: 1098 break; 1099 1100 default: 1101 device_printf(gc->dev, 1102 "Can't destroy unknown queue: type = %d\n", 1103 queue->type); 1104 return; 1105 } 1106 1107 mana_gd_destroy_dma_region(gc, gmi->dma_region_handle); 1108 mana_gd_free_memory(gmi); 1109 free(queue, M_DEVBUF); 1110 } 1111 1112 #define OS_MAJOR_DIV 100000 1113 #define OS_BUILD_MOD 1000 1114 1115 int 1116 mana_gd_verify_vf_version(device_t dev) 1117 { 1118 struct gdma_context *gc = device_get_softc(dev); 1119 struct gdma_verify_ver_resp resp = {}; 1120 struct gdma_verify_ver_req req = {}; 1121 int err; 1122 1123 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 1124 sizeof(req), sizeof(resp)); 1125 1126 req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 1127 req.protocol_ver_max = GDMA_PROTOCOL_LAST; 1128 1129 req.drv_ver = 0; /* Unused */ 1130 req.os_type = 0x30; /* Other */ 1131 req.os_ver_major = osreldate / OS_MAJOR_DIV; 1132 req.os_ver_minor = (osreldate % OS_MAJOR_DIV) / OS_BUILD_MOD; 1133 req.os_ver_build = osreldate % OS_BUILD_MOD; 1134 strncpy(req.os_ver_str1, ostype, sizeof(req.os_ver_str1) - 1); 1135 strncpy(req.os_ver_str2, osrelease, sizeof(req.os_ver_str2) - 1); 1136 1137 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1138 if (err || resp.hdr.status) { 1139 device_printf(gc->dev, 1140 "VfVerifyVersionOutput: %d, status=0x%x\n", 1141 err, resp.hdr.status); 1142 return err ? err : EPROTO; 1143 } 1144 1145 return 0; 1146 } 1147 1148 int 1149 mana_gd_register_device(struct gdma_dev *gd) 1150 { 1151 struct gdma_context *gc = gd->gdma_context; 1152 struct gdma_register_device_resp resp = {}; 1153 struct gdma_general_req req = {}; 1154 int err; 1155 1156 gd->pdid = INVALID_PDID; 1157 gd->doorbell = INVALID_DOORBELL; 1158 gd->gpa_mkey = INVALID_MEM_KEY; 1159 1160 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 1161 sizeof(resp)); 1162 1163 req.hdr.dev_id = gd->dev_id; 1164 1165 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1166 if (err || resp.hdr.status) { 1167 device_printf(gc->dev, 1168 "gdma_register_device_resp failed: %d, 0x%x\n", 1169 err, resp.hdr.status); 1170 return err ? err : -EPROTO; 1171 } 1172 1173 gd->pdid = resp.pdid; 1174 gd->gpa_mkey = resp.gpa_mkey; 1175 gd->doorbell = resp.db_id; 1176 1177 mana_dbg(NULL, "mana device pdid %u, gpa_mkey %u, doorbell %u \n", 1178 gd->pdid, gd->gpa_mkey, gd->doorbell); 1179 1180 return 0; 1181 } 1182 1183 int 1184 mana_gd_deregister_device(struct gdma_dev *gd) 1185 { 1186 struct gdma_context *gc = gd->gdma_context; 1187 struct gdma_general_resp resp = {}; 1188 struct gdma_general_req req = {}; 1189 int err; 1190 1191 if (gd->pdid == INVALID_PDID) 1192 return EINVAL; 1193 1194 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 1195 sizeof(resp)); 1196 1197 req.hdr.dev_id = gd->dev_id; 1198 1199 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1200 if (err || resp.hdr.status) { 1201 device_printf(gc->dev, 1202 "Failed to deregister device: %d, 0x%x\n", 1203 err, resp.hdr.status); 1204 if (!err) 1205 err = EPROTO; 1206 } 1207 1208 gd->pdid = INVALID_PDID; 1209 gd->doorbell = INVALID_DOORBELL; 1210 gd->gpa_mkey = INVALID_MEM_KEY; 1211 1212 return err; 1213 } 1214 1215 uint32_t 1216 mana_gd_wq_avail_space(struct gdma_queue *wq) 1217 { 1218 uint32_t used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 1219 uint32_t wq_size = wq->queue_size; 1220 1221 if (used_space > wq_size) { 1222 mana_warn(NULL, "failed: used space %u > queue size %u\n", 1223 used_space, wq_size); 1224 } 1225 1226 return wq_size - used_space; 1227 } 1228 1229 uint8_t * 1230 mana_gd_get_wqe_ptr(const struct gdma_queue *wq, uint32_t wqe_offset) 1231 { 1232 uint32_t offset = 1233 (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 1234 1235 if ((offset + GDMA_WQE_BU_SIZE) > wq->queue_size) { 1236 mana_warn(NULL, "failed: write end out of queue bound %u, " 1237 "queue size %u\n", 1238 offset + GDMA_WQE_BU_SIZE, wq->queue_size); 1239 } 1240 1241 return (uint8_t *)wq->queue_mem_ptr + offset; 1242 } 1243 1244 static uint32_t 1245 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 1246 enum gdma_queue_type q_type, 1247 uint32_t client_oob_size, uint32_t sgl_data_size, 1248 uint8_t *wqe_ptr) 1249 { 1250 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 1251 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 1252 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 1253 uint8_t *ptr; 1254 1255 memset(header, 0, sizeof(struct gdma_wqe)); 1256 header->num_sge = wqe_req->num_sge; 1257 header->inline_oob_size_div4 = client_oob_size / sizeof(uint32_t); 1258 1259 if (oob_in_sgl) { 1260 if (!pad_data || wqe_req->num_sge < 2) { 1261 mana_warn(NULL, "no pad_data or num_sge < 2\n"); 1262 } 1263 1264 header->client_oob_in_sgl = 1; 1265 1266 if (pad_data) 1267 header->last_vbytes = wqe_req->sgl[0].size; 1268 } 1269 1270 if (q_type == GDMA_SQ) 1271 header->client_data_unit = wqe_req->client_data_unit; 1272 1273 /* 1274 * The size of gdma_wqe + client_oob_size must be less than or equal 1275 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1276 * the queue memory buffer boundary. 1277 */ 1278 ptr = wqe_ptr + sizeof(header); 1279 1280 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1281 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1282 1283 if (client_oob_size > wqe_req->inline_oob_size) 1284 memset(ptr + wqe_req->inline_oob_size, 0, 1285 client_oob_size - wqe_req->inline_oob_size); 1286 } 1287 1288 return sizeof(header) + client_oob_size; 1289 } 1290 1291 static void 1292 mana_gd_write_sgl(struct gdma_queue *wq, uint8_t *wqe_ptr, 1293 const struct gdma_wqe_request *wqe_req) 1294 { 1295 uint32_t sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1296 const uint8_t *address = (uint8_t *)wqe_req->sgl; 1297 uint8_t *base_ptr, *end_ptr; 1298 uint32_t size_to_end; 1299 1300 base_ptr = wq->queue_mem_ptr; 1301 end_ptr = base_ptr + wq->queue_size; 1302 size_to_end = (uint32_t)(end_ptr - wqe_ptr); 1303 1304 if (size_to_end < sgl_size) { 1305 memcpy(wqe_ptr, address, size_to_end); 1306 1307 wqe_ptr = base_ptr; 1308 address += size_to_end; 1309 sgl_size -= size_to_end; 1310 } 1311 1312 memcpy(wqe_ptr, address, sgl_size); 1313 } 1314 1315 int 1316 mana_gd_post_work_request(struct gdma_queue *wq, 1317 const struct gdma_wqe_request *wqe_req, 1318 struct gdma_posted_wqe_info *wqe_info) 1319 { 1320 uint32_t client_oob_size = wqe_req->inline_oob_size; 1321 struct gdma_context *gc; 1322 uint32_t sgl_data_size; 1323 uint32_t max_wqe_size; 1324 uint32_t wqe_size; 1325 uint8_t *wqe_ptr; 1326 1327 if (wqe_req->num_sge == 0) 1328 return EINVAL; 1329 1330 if (wq->type == GDMA_RQ) { 1331 if (client_oob_size != 0) 1332 return EINVAL; 1333 1334 client_oob_size = INLINE_OOB_SMALL_SIZE; 1335 1336 max_wqe_size = GDMA_MAX_RQE_SIZE; 1337 } else { 1338 if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1339 client_oob_size != INLINE_OOB_LARGE_SIZE) 1340 return EINVAL; 1341 1342 max_wqe_size = GDMA_MAX_SQE_SIZE; 1343 } 1344 1345 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1346 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1347 sgl_data_size, GDMA_WQE_BU_SIZE); 1348 if (wqe_size > max_wqe_size) 1349 return EINVAL; 1350 1351 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1352 gc = wq->gdma_dev->gdma_context; 1353 device_printf(gc->dev, "unsuccessful flow control!\n"); 1354 return ENOSPC; 1355 } 1356 1357 if (wqe_info) 1358 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1359 1360 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1361 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1362 sgl_data_size, wqe_ptr); 1363 if (wqe_ptr >= (uint8_t *)wq->queue_mem_ptr + wq->queue_size) 1364 wqe_ptr -= wq->queue_size; 1365 1366 mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1367 1368 wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1369 1370 bus_dmamap_sync(wq->mem_info.dma_tag, wq->mem_info.dma_map, 1371 BUS_DMASYNC_PREWRITE); 1372 1373 return 0; 1374 } 1375 1376 int 1377 mana_gd_post_and_ring(struct gdma_queue *queue, 1378 const struct gdma_wqe_request *wqe_req, 1379 struct gdma_posted_wqe_info *wqe_info) 1380 { 1381 struct gdma_context *gc = queue->gdma_dev->gdma_context; 1382 int err; 1383 1384 err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1385 if (err) 1386 return err; 1387 1388 mana_gd_wq_ring_doorbell(gc, queue); 1389 1390 return 0; 1391 } 1392 1393 static int 1394 mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1395 { 1396 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1397 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1398 uint32_t owner_bits, new_bits, old_bits; 1399 struct gdma_cqe *cqe; 1400 1401 cqe = &cq_cqe[cq->head % num_cqe]; 1402 owner_bits = cqe->cqe_info.owner_bits; 1403 1404 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1405 /* Return 0 if no more entries. */ 1406 if (owner_bits == old_bits) 1407 return 0; 1408 1409 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1410 /* Return -1 if overflow detected. */ 1411 if (owner_bits != new_bits) { 1412 mana_warn(NULL, 1413 "overflow detected! owner_bits %u != new_bits %u\n", 1414 owner_bits, new_bits); 1415 return -1; 1416 } 1417 1418 rmb(); 1419 1420 comp->wq_num = cqe->cqe_info.wq_num; 1421 comp->is_sq = cqe->cqe_info.is_sq; 1422 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1423 1424 return 1; 1425 } 1426 1427 int 1428 mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1429 { 1430 int cqe_idx; 1431 int ret; 1432 1433 bus_dmamap_sync(cq->mem_info.dma_tag, cq->mem_info.dma_map, 1434 BUS_DMASYNC_POSTREAD); 1435 1436 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1437 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1438 1439 if (ret < 0) { 1440 cq->head -= cqe_idx; 1441 return ret; 1442 } 1443 1444 if (ret == 0) 1445 break; 1446 1447 cq->head++; 1448 } 1449 1450 return cqe_idx; 1451 } 1452 1453 static void 1454 mana_gd_intr(void *arg) 1455 { 1456 struct gdma_irq_context *gic = arg; 1457 1458 if (gic->handler) { 1459 gic->handler(gic->arg); 1460 } 1461 } 1462 1463 int 1464 mana_gd_alloc_res_map(uint32_t res_avail, 1465 struct gdma_resource *r, const char *lock_name) 1466 { 1467 int n = howmany(res_avail, BITS_PER_LONG); 1468 1469 r->map = 1470 malloc(n * sizeof(unsigned long), M_DEVBUF, M_WAITOK | M_ZERO); 1471 r->size = res_avail; 1472 mtx_init(&r->lock_spin, lock_name, NULL, MTX_SPIN); 1473 1474 mana_dbg(NULL, 1475 "total res %u, total number of unsigned longs %u\n", 1476 r->size, n); 1477 return (0); 1478 } 1479 1480 void 1481 mana_gd_free_res_map(struct gdma_resource *r) 1482 { 1483 if (!r || !r->map) 1484 return; 1485 1486 free(r->map, M_DEVBUF); 1487 r->map = NULL; 1488 r->size = 0; 1489 } 1490 1491 static void 1492 mana_gd_init_registers(struct gdma_context *gc) 1493 { 1494 uintptr_t bar0_va = rman_get_bushandle(gc->bar0); 1495 vm_paddr_t bar0_pa = rman_get_start(gc->bar0); 1496 1497 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 1498 1499 gc->db_page_base = 1500 (void *)(bar0_va + (size_t)mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET)); 1501 1502 gc->phys_db_page_base = 1503 bar0_pa + mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 1504 1505 gc->shm_base = 1506 (void *)(bar0_va + (size_t)mana_gd_r64(gc, GDMA_REG_SHM_OFFSET)); 1507 1508 mana_dbg(NULL, "db_page_size 0x%xx, db_page_base %p," 1509 " shm_base %p\n", 1510 gc->db_page_size, gc->db_page_base, gc->shm_base); 1511 } 1512 1513 static struct resource * 1514 mana_gd_alloc_bar(device_t dev, int bar) 1515 { 1516 struct resource *res = NULL; 1517 struct pci_map *pm; 1518 int rid, type; 1519 1520 if (bar < 0 || bar > PCIR_MAX_BAR_0) 1521 goto alloc_bar_out; 1522 1523 pm = pci_find_bar(dev, PCIR_BAR(bar)); 1524 if (!pm) 1525 goto alloc_bar_out; 1526 1527 if (PCI_BAR_IO(pm->pm_value)) 1528 type = SYS_RES_IOPORT; 1529 else 1530 type = SYS_RES_MEMORY; 1531 if (type < 0) 1532 goto alloc_bar_out; 1533 1534 rid = PCIR_BAR(bar); 1535 res = bus_alloc_resource_any(dev, type, &rid, RF_ACTIVE); 1536 #if defined(__amd64__) 1537 if (res) 1538 mana_dbg(NULL, "bar %d: rid 0x%x, type 0x%jx," 1539 " handle 0x%jx\n", 1540 bar, rid, res->r_bustag, res->r_bushandle); 1541 #endif 1542 1543 alloc_bar_out: 1544 return (res); 1545 } 1546 1547 static void 1548 mana_gd_free_pci_res(struct gdma_context *gc) 1549 { 1550 if (!gc || !gc->dev) 1551 return; 1552 1553 if (gc->bar0 != NULL) { 1554 bus_release_resource(gc->dev, SYS_RES_MEMORY, 1555 PCIR_BAR(GDMA_BAR0), gc->bar0); 1556 } 1557 1558 if (gc->msix != NULL) { 1559 bus_release_resource(gc->dev, SYS_RES_MEMORY, 1560 gc->msix_rid, gc->msix); 1561 } 1562 } 1563 1564 static int 1565 mana_gd_setup_irqs(device_t dev) 1566 { 1567 unsigned int max_queues_per_port = mp_ncpus; 1568 struct gdma_context *gc = device_get_softc(dev); 1569 struct gdma_irq_context *gic; 1570 unsigned int max_irqs; 1571 int nvec; 1572 int rc, rcc, i; 1573 1574 if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1575 max_queues_per_port = MANA_MAX_NUM_QUEUES; 1576 1577 /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 1578 max_irqs = max_queues_per_port + 1; 1579 1580 nvec = max_irqs; 1581 rc = pci_alloc_msix(dev, &nvec); 1582 if (unlikely(rc != 0)) { 1583 device_printf(dev, 1584 "Failed to allocate MSIX, vectors %d, error: %d\n", 1585 nvec, rc); 1586 rc = ENOSPC; 1587 goto err_setup_irq_alloc; 1588 } 1589 1590 if (nvec != max_irqs) { 1591 if (nvec == 1) { 1592 device_printf(dev, 1593 "Not enough number of MSI-x allocated: %d\n", 1594 nvec); 1595 rc = ENOSPC; 1596 goto err_setup_irq_release; 1597 } 1598 device_printf(dev, "Allocated only %d MSI-x (%d requested)\n", 1599 nvec, max_irqs); 1600 } 1601 1602 gc->irq_contexts = malloc(nvec * sizeof(struct gdma_irq_context), 1603 M_DEVBUF, M_WAITOK | M_ZERO); 1604 1605 for (i = 0; i < nvec; i++) { 1606 gic = &gc->irq_contexts[i]; 1607 gic->msix_e.entry = i; 1608 /* Vector starts from 1. */ 1609 gic->msix_e.vector = i + 1; 1610 gic->handler = NULL; 1611 gic->arg = NULL; 1612 1613 gic->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1614 &gic->msix_e.vector, RF_ACTIVE | RF_SHAREABLE); 1615 if (unlikely(gic->res == NULL)) { 1616 rc = ENOMEM; 1617 device_printf(dev, "could not allocate resource " 1618 "for irq vector %d\n", gic->msix_e.vector); 1619 goto err_setup_irq; 1620 } 1621 1622 rc = bus_setup_intr(dev, gic->res, 1623 INTR_TYPE_NET | INTR_MPSAFE, NULL, mana_gd_intr, 1624 gic, &gic->cookie); 1625 if (unlikely(rc != 0)) { 1626 device_printf(dev, "failed to register interrupt " 1627 "handler for irq %ju vector %d: error %d\n", 1628 rman_get_start(gic->res), gic->msix_e.vector, rc); 1629 goto err_setup_irq; 1630 } 1631 gic->requested = true; 1632 1633 mana_dbg(NULL, "added msix vector %d irq %ju\n", 1634 gic->msix_e.vector, rman_get_start(gic->res)); 1635 } 1636 1637 rc = mana_gd_alloc_res_map(nvec, &gc->msix_resource, 1638 "gdma msix res lock"); 1639 if (rc != 0) { 1640 device_printf(dev, "failed to allocate memory " 1641 "for msix bitmap\n"); 1642 goto err_setup_irq; 1643 } 1644 1645 gc->max_num_msix = nvec; 1646 gc->num_msix_usable = nvec; 1647 1648 mana_dbg(NULL, "setup %d msix interrupts\n", nvec); 1649 1650 return (0); 1651 1652 err_setup_irq: 1653 for (; i >= 0; i--) { 1654 gic = &gc->irq_contexts[i]; 1655 rcc = 0; 1656 1657 /* 1658 * If gic->requested is true, we need to free both intr and 1659 * resources. 1660 */ 1661 if (gic->requested) 1662 rcc = bus_teardown_intr(dev, gic->res, gic->cookie); 1663 if (unlikely(rcc != 0)) 1664 device_printf(dev, "could not release " 1665 "irq vector %d, error: %d\n", 1666 gic->msix_e.vector, rcc); 1667 1668 rcc = 0; 1669 if (gic->res != NULL) { 1670 rcc = bus_release_resource(dev, SYS_RES_IRQ, 1671 gic->msix_e.vector, gic->res); 1672 } 1673 if (unlikely(rcc != 0)) 1674 device_printf(dev, "dev has no parent while " 1675 "releasing resource for irq vector %d\n", 1676 gic->msix_e.vector); 1677 gic->requested = false; 1678 gic->res = NULL; 1679 } 1680 1681 free(gc->irq_contexts, M_DEVBUF); 1682 gc->irq_contexts = NULL; 1683 err_setup_irq_release: 1684 pci_release_msi(dev); 1685 err_setup_irq_alloc: 1686 return (rc); 1687 } 1688 1689 static void 1690 mana_gd_remove_irqs(device_t dev) 1691 { 1692 struct gdma_context *gc = device_get_softc(dev); 1693 struct gdma_irq_context *gic; 1694 int rc, i; 1695 1696 mana_gd_free_res_map(&gc->msix_resource); 1697 1698 for (i = 0; i < gc->max_num_msix; i++) { 1699 gic = &gc->irq_contexts[i]; 1700 if (gic->requested) { 1701 rc = bus_teardown_intr(dev, gic->res, gic->cookie); 1702 if (unlikely(rc != 0)) { 1703 device_printf(dev, "failed to tear down " 1704 "irq vector %d, error: %d\n", 1705 gic->msix_e.vector, rc); 1706 } 1707 gic->requested = false; 1708 } 1709 1710 if (gic->res != NULL) { 1711 rc = bus_release_resource(dev, SYS_RES_IRQ, 1712 gic->msix_e.vector, gic->res); 1713 if (unlikely(rc != 0)) { 1714 device_printf(dev, "dev has no parent while " 1715 "releasing resource for irq vector %d\n", 1716 gic->msix_e.vector); 1717 } 1718 gic->res = NULL; 1719 } 1720 } 1721 1722 gc->max_num_msix = 0; 1723 gc->num_msix_usable = 0; 1724 free(gc->irq_contexts, M_DEVBUF); 1725 gc->irq_contexts = NULL; 1726 1727 pci_release_msi(dev); 1728 } 1729 1730 static int 1731 mana_gd_probe(device_t dev) 1732 { 1733 mana_vendor_id_t *ent; 1734 uint16_t pci_vendor_id = 0; 1735 uint16_t pci_device_id = 0; 1736 1737 pci_vendor_id = pci_get_vendor(dev); 1738 pci_device_id = pci_get_device(dev); 1739 1740 ent = mana_id_table; 1741 while (ent->vendor_id != 0) { 1742 if ((pci_vendor_id == ent->vendor_id) && 1743 (pci_device_id == ent->device_id)) { 1744 mana_dbg(NULL, "vendor=%x device=%x\n", 1745 pci_vendor_id, pci_device_id); 1746 1747 device_set_desc(dev, DEVICE_DESC); 1748 return (BUS_PROBE_DEFAULT); 1749 } 1750 1751 ent++; 1752 } 1753 1754 return (ENXIO); 1755 } 1756 1757 /** 1758 * mana_attach - Device Initialization Routine 1759 * @dev: device information struct 1760 * 1761 * Returns 0 on success, otherwise on failure. 1762 * 1763 * mana_attach initializes a GDMA adapter identified by a device structure. 1764 **/ 1765 static int 1766 mana_gd_attach(device_t dev) 1767 { 1768 struct gdma_context *gc; 1769 int msix_rid; 1770 int rc; 1771 1772 gc = device_get_softc(dev); 1773 gc->dev = dev; 1774 1775 pci_enable_io(dev, SYS_RES_IOPORT); 1776 pci_enable_io(dev, SYS_RES_MEMORY); 1777 1778 pci_enable_busmaster(dev); 1779 1780 gc->bar0 = mana_gd_alloc_bar(dev, GDMA_BAR0); 1781 if (unlikely(gc->bar0 == NULL)) { 1782 device_printf(dev, 1783 "unable to allocate bus resource for bar0!\n"); 1784 rc = ENOMEM; 1785 goto err_disable_dev; 1786 } 1787 1788 /* Store bar0 tage and handle for quick access */ 1789 gc->gd_bus.bar0_t = rman_get_bustag(gc->bar0); 1790 gc->gd_bus.bar0_h = rman_get_bushandle(gc->bar0); 1791 1792 /* Map MSI-x vector table */ 1793 msix_rid = pci_msix_table_bar(dev); 1794 1795 mana_dbg(NULL, "msix_rid 0x%x\n", msix_rid); 1796 1797 gc->msix = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1798 &msix_rid, RF_ACTIVE); 1799 if (unlikely(gc->msix == NULL)) { 1800 device_printf(dev, 1801 "unable to allocate bus resource for msix!\n"); 1802 rc = ENOMEM; 1803 goto err_free_pci_res; 1804 } 1805 gc->msix_rid = msix_rid; 1806 1807 if (unlikely(gc->gd_bus.bar0_h == 0)) { 1808 device_printf(dev, "failed to map bar0!\n"); 1809 rc = ENXIO; 1810 goto err_free_pci_res; 1811 } 1812 1813 mana_gd_init_registers(gc); 1814 1815 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1816 1817 rc = mana_gd_setup_irqs(dev); 1818 if (rc) { 1819 goto err_free_pci_res; 1820 } 1821 1822 sx_init(&gc->eq_test_event_sx, "gdma test event sx"); 1823 1824 rc = mana_hwc_create_channel(gc); 1825 if (rc) { 1826 mana_dbg(NULL, "Failed to create hwc channel\n"); 1827 if (rc == EIO) 1828 goto err_clean_up_gdma; 1829 else 1830 goto err_remove_irq; 1831 } 1832 1833 rc = mana_gd_verify_vf_version(dev); 1834 if (rc) { 1835 mana_dbg(NULL, "Failed to verify vf\n"); 1836 goto err_clean_up_gdma; 1837 } 1838 1839 rc = mana_gd_query_max_resources(dev); 1840 if (rc) { 1841 mana_dbg(NULL, "Failed to query max resources\n"); 1842 goto err_clean_up_gdma; 1843 } 1844 1845 rc = mana_gd_detect_devices(dev); 1846 if (rc) { 1847 mana_dbg(NULL, "Failed to detect mana device\n"); 1848 goto err_clean_up_gdma; 1849 } 1850 1851 rc = mana_probe(&gc->mana); 1852 if (rc) { 1853 mana_dbg(NULL, "Failed to probe mana device\n"); 1854 goto err_clean_up_gdma; 1855 } 1856 1857 return (0); 1858 1859 err_clean_up_gdma: 1860 mana_hwc_destroy_channel(gc); 1861 err_remove_irq: 1862 mana_gd_remove_irqs(dev); 1863 err_free_pci_res: 1864 mana_gd_free_pci_res(gc); 1865 err_disable_dev: 1866 pci_disable_busmaster(dev); 1867 1868 return(rc); 1869 } 1870 1871 /** 1872 * mana_detach - Device Removal Routine 1873 * @pdev: device information struct 1874 * 1875 * mana_detach is called by the device subsystem to alert the driver 1876 * that it should release a PCI device. 1877 **/ 1878 static int 1879 mana_gd_detach(device_t dev) 1880 { 1881 struct gdma_context *gc = device_get_softc(dev); 1882 1883 mana_remove(&gc->mana); 1884 1885 mana_hwc_destroy_channel(gc); 1886 1887 mana_gd_remove_irqs(dev); 1888 1889 mana_gd_free_pci_res(gc); 1890 1891 pci_disable_busmaster(dev); 1892 1893 return (bus_generic_detach(dev)); 1894 } 1895 1896 1897 /********************************************************************* 1898 * FreeBSD Device Interface Entry Points 1899 *********************************************************************/ 1900 1901 static device_method_t mana_methods[] = { 1902 /* Device interface */ 1903 DEVMETHOD(device_probe, mana_gd_probe), 1904 DEVMETHOD(device_attach, mana_gd_attach), 1905 DEVMETHOD(device_detach, mana_gd_detach), 1906 DEVMETHOD_END 1907 }; 1908 1909 static driver_t mana_driver = { 1910 "mana", mana_methods, sizeof(struct gdma_context), 1911 }; 1912 1913 DRIVER_MODULE(mana, pci, mana_driver, 0, 0); 1914 MODULE_PNP_INFO("U16:vendor;U16:device", pci, mana, mana_id_table, 1915 nitems(mana_id_table) - 1); 1916 MODULE_DEPEND(mana, pci, 1, 1, 1); 1917 MODULE_DEPEND(mana, ether, 1, 1, 1); 1918 1919 /*********************************************************************/ 1920