1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Microsoft Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/kthread.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/rman.h> 42 #include <sys/smp.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <sys/eventhandler.h> 48 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/in_cksum.h> 52 53 #include <net/if.h> 54 #include <net/if_var.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 59 #include "gdma_util.h" 60 #include "mana.h" 61 62 63 static mana_vendor_id_t mana_id_table[] = { 64 { PCI_VENDOR_ID_MICROSOFT, PCI_DEV_ID_MANA_VF}, 65 /* Last entry */ 66 { 0, 0} 67 }; 68 69 static inline uint32_t 70 mana_gd_r32(struct gdma_context *g, uint64_t offset) 71 { 72 uint32_t v = bus_space_read_4(g->gd_bus.bar0_t, 73 g->gd_bus.bar0_h, offset); 74 rmb(); 75 return (v); 76 } 77 78 #if defined(__amd64__) 79 static inline uint64_t 80 mana_gd_r64(struct gdma_context *g, uint64_t offset) 81 { 82 uint64_t v = bus_space_read_8(g->gd_bus.bar0_t, 83 g->gd_bus.bar0_h, offset); 84 rmb(); 85 return (v); 86 } 87 #else 88 static inline uint64_t 89 mana_gd_r64(struct gdma_context *g, uint64_t offset) 90 { 91 uint64_t v; 92 uint32_t *vp = (uint32_t *)&v; 93 94 *vp = mana_gd_r32(g, offset); 95 *(vp + 1) = mana_gd_r32(g, offset + 4); 96 rmb(); 97 return (v); 98 } 99 #endif 100 101 static int 102 mana_gd_query_max_resources(device_t dev) 103 { 104 struct gdma_context *gc = device_get_softc(dev); 105 struct gdma_query_max_resources_resp resp = {}; 106 struct gdma_general_req req = {}; 107 int err; 108 109 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 110 sizeof(req), sizeof(resp)); 111 112 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 113 if (err || resp.hdr.status) { 114 device_printf(gc->dev, 115 "Failed to query resource info: %d, 0x%x\n", 116 err, resp.hdr.status); 117 return err ? err : EPROTO; 118 } 119 120 mana_dbg(NULL, "max_msix %u, max_eq %u, max_cq %u, " 121 "max_sq %u, max_rq %u\n", 122 resp.max_msix, resp.max_eq, resp.max_cq, 123 resp.max_sq, resp.max_rq); 124 125 if (gc->num_msix_usable > resp.max_msix) 126 gc->num_msix_usable = resp.max_msix; 127 128 if (gc->num_msix_usable <= 1) 129 return ENOSPC; 130 131 gc->max_num_queues = mp_ncpus; 132 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 133 gc->max_num_queues = MANA_MAX_NUM_QUEUES; 134 135 if (gc->max_num_queues > resp.max_eq) 136 gc->max_num_queues = resp.max_eq; 137 138 if (gc->max_num_queues > resp.max_cq) 139 gc->max_num_queues = resp.max_cq; 140 141 if (gc->max_num_queues > resp.max_sq) 142 gc->max_num_queues = resp.max_sq; 143 144 if (gc->max_num_queues > resp.max_rq) 145 gc->max_num_queues = resp.max_rq; 146 147 return 0; 148 } 149 150 static int 151 mana_gd_detect_devices(device_t dev) 152 { 153 struct gdma_context *gc = device_get_softc(dev); 154 struct gdma_list_devices_resp resp = {}; 155 struct gdma_general_req req = {}; 156 struct gdma_dev_id gd_dev; 157 uint32_t i, max_num_devs; 158 uint16_t dev_type; 159 int err; 160 161 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 162 sizeof(resp)); 163 164 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 165 if (err || resp.hdr.status) { 166 device_printf(gc->dev, 167 "Failed to detect devices: %d, 0x%x\n", err, 168 resp.hdr.status); 169 return err ? err : EPROTO; 170 } 171 172 max_num_devs = min_t(uint32_t, MAX_NUM_GDMA_DEVICES, resp.num_of_devs); 173 174 for (i = 0; i < max_num_devs; i++) { 175 gd_dev = resp.devs[i]; 176 dev_type = gd_dev.type; 177 178 mana_dbg(NULL, "gdma dev %d, type %u\n", 179 i, dev_type); 180 181 /* HWC is already detected in mana_hwc_create_channel(). */ 182 if (dev_type == GDMA_DEVICE_HWC) 183 continue; 184 185 if (dev_type == GDMA_DEVICE_MANA) { 186 gc->mana.gdma_context = gc; 187 gc->mana.dev_id = gd_dev; 188 } 189 } 190 191 return gc->mana.dev_id.type == 0 ? ENODEV : 0; 192 } 193 194 int 195 mana_gd_send_request(struct gdma_context *gc, uint32_t req_len, 196 const void *req, uint32_t resp_len, void *resp) 197 { 198 struct hw_channel_context *hwc = gc->hwc.driver_data; 199 200 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 201 } 202 203 void 204 mana_gd_dma_map_paddr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 205 { 206 bus_addr_t *paddr = arg; 207 208 if (error) 209 return; 210 211 KASSERT(nseg == 1, ("too many segments %d!", nseg)); 212 *paddr = segs->ds_addr; 213 } 214 215 int 216 mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 217 struct gdma_mem_info *gmi) 218 { 219 bus_addr_t dma_handle; 220 void *buf; 221 int err; 222 223 if (!gc || !gmi) 224 return EINVAL; 225 226 if (length < PAGE_SIZE || (length != roundup_pow_of_two(length))) 227 return EINVAL; 228 229 err = bus_dma_tag_create(bus_get_dma_tag(gc->dev), /* parent */ 230 PAGE_SIZE, 0, /* alignment, boundary */ 231 BUS_SPACE_MAXADDR, /* lowaddr */ 232 BUS_SPACE_MAXADDR, /* highaddr */ 233 NULL, NULL, /* filter, filterarg */ 234 length, /* maxsize */ 235 1, /* nsegments */ 236 length, /* maxsegsize */ 237 0, /* flags */ 238 NULL, NULL, /* lockfunc, lockfuncarg*/ 239 &gmi->dma_tag); 240 if (err) { 241 device_printf(gc->dev, 242 "failed to create dma tag, err: %d\n", err); 243 return (err); 244 } 245 246 /* 247 * Must have BUS_DMA_ZERO flag to clear the dma memory. 248 * Otherwise the queue overflow detection mechanism does 249 * not work. 250 */ 251 err = bus_dmamem_alloc(gmi->dma_tag, &buf, 252 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &gmi->dma_map); 253 if (err) { 254 device_printf(gc->dev, 255 "failed to alloc dma mem, err: %d\n", err); 256 bus_dma_tag_destroy(gmi->dma_tag); 257 return (err); 258 } 259 260 err = bus_dmamap_load(gmi->dma_tag, gmi->dma_map, buf, 261 length, mana_gd_dma_map_paddr, &dma_handle, BUS_DMA_NOWAIT); 262 if (err) { 263 device_printf(gc->dev, 264 "failed to load dma mem, err: %d\n", err); 265 bus_dmamem_free(gmi->dma_tag, buf, gmi->dma_map); 266 bus_dma_tag_destroy(gmi->dma_tag); 267 return (err); 268 } 269 270 gmi->dev = gc->dev; 271 gmi->dma_handle = dma_handle; 272 gmi->virt_addr = buf; 273 gmi->length = length; 274 275 return 0; 276 } 277 278 void 279 mana_gd_free_memory(struct gdma_mem_info *gmi) 280 { 281 bus_dmamap_unload(gmi->dma_tag, gmi->dma_map); 282 bus_dmamem_free(gmi->dma_tag, gmi->virt_addr, gmi->dma_map); 283 bus_dma_tag_destroy(gmi->dma_tag); 284 } 285 286 static int 287 mana_gd_create_hw_eq(struct gdma_context *gc, 288 struct gdma_queue *queue) 289 { 290 struct gdma_create_queue_resp resp = {}; 291 struct gdma_create_queue_req req = {}; 292 int err; 293 294 if (queue->type != GDMA_EQ) 295 return EINVAL; 296 297 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 298 sizeof(req), sizeof(resp)); 299 300 req.hdr.dev_id = queue->gdma_dev->dev_id; 301 req.type = queue->type; 302 req.pdid = queue->gdma_dev->pdid; 303 req.doolbell_id = queue->gdma_dev->doorbell; 304 req.gdma_region = queue->mem_info.gdma_region; 305 req.queue_size = queue->queue_size; 306 req.log2_throttle_limit = queue->eq.log2_throttle_limit; 307 req.eq_pci_msix_index = queue->eq.msix_index; 308 309 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 310 if (err || resp.hdr.status) { 311 device_printf(gc->dev, 312 "Failed to create queue: %d, 0x%x\n", 313 err, resp.hdr.status); 314 return err ? err : EPROTO; 315 } 316 317 queue->id = resp.queue_index; 318 queue->eq.disable_needed = true; 319 queue->mem_info.gdma_region = GDMA_INVALID_DMA_REGION; 320 return 0; 321 } 322 323 static 324 int mana_gd_disable_queue(struct gdma_queue *queue) 325 { 326 struct gdma_context *gc = queue->gdma_dev->gdma_context; 327 struct gdma_disable_queue_req req = {}; 328 struct gdma_general_resp resp = {}; 329 int err; 330 331 if (queue->type != GDMA_EQ) 332 mana_warn(NULL, "Not event queue type 0x%x\n", 333 queue->type); 334 335 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 336 sizeof(req), sizeof(resp)); 337 338 req.hdr.dev_id = queue->gdma_dev->dev_id; 339 req.type = queue->type; 340 req.queue_index = queue->id; 341 req.alloc_res_id_on_creation = 1; 342 343 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 344 if (err || resp.hdr.status) { 345 device_printf(gc->dev, 346 "Failed to disable queue: %d, 0x%x\n", err, 347 resp.hdr.status); 348 return err ? err : EPROTO; 349 } 350 351 return 0; 352 } 353 354 #define DOORBELL_OFFSET_SQ 0x0 355 #define DOORBELL_OFFSET_RQ 0x400 356 #define DOORBELL_OFFSET_CQ 0x800 357 #define DOORBELL_OFFSET_EQ 0xFF8 358 359 static void 360 mana_gd_ring_doorbell(struct gdma_context *gc, uint32_t db_index, 361 enum gdma_queue_type q_type, uint32_t qid, 362 uint32_t tail_ptr, uint8_t num_req) 363 { 364 union gdma_doorbell_entry e = {}; 365 void __iomem *addr; 366 367 addr = (char *)gc->db_page_base + gc->db_page_size * db_index; 368 switch (q_type) { 369 case GDMA_EQ: 370 e.eq.id = qid; 371 e.eq.tail_ptr = tail_ptr; 372 e.eq.arm = num_req; 373 374 addr = (char *)addr + DOORBELL_OFFSET_EQ; 375 break; 376 377 case GDMA_CQ: 378 e.cq.id = qid; 379 e.cq.tail_ptr = tail_ptr; 380 e.cq.arm = num_req; 381 382 addr = (char *)addr + DOORBELL_OFFSET_CQ; 383 break; 384 385 case GDMA_RQ: 386 e.rq.id = qid; 387 e.rq.tail_ptr = tail_ptr; 388 e.rq.wqe_cnt = num_req; 389 390 addr = (char *)addr + DOORBELL_OFFSET_RQ; 391 break; 392 393 case GDMA_SQ: 394 e.sq.id = qid; 395 e.sq.tail_ptr = tail_ptr; 396 397 addr = (char *)addr + DOORBELL_OFFSET_SQ; 398 break; 399 400 default: 401 mana_warn(NULL, "Invalid queue type 0x%x\n", q_type); 402 return; 403 } 404 405 /* Ensure all writes are done before ring doorbell */ 406 wmb(); 407 408 #if defined(__amd64__) 409 writeq(addr, e.as_uint64); 410 #else 411 uint32_t *p = (uint32_t *)&e.as_uint64; 412 writel(addr, *p); 413 writel((char *)addr + 4, *(p + 1)); 414 #endif 415 } 416 417 void 418 mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 419 { 420 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 421 queue->id, queue->head * GDMA_WQE_BU_SIZE, 1); 422 } 423 424 void 425 mana_gd_arm_cq(struct gdma_queue *cq) 426 { 427 struct gdma_context *gc = cq->gdma_dev->gdma_context; 428 429 uint32_t num_cqe = cq->queue_size / GDMA_CQE_SIZE; 430 431 uint32_t head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 432 433 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 434 head, SET_ARM_BIT); 435 } 436 437 static void 438 mana_gd_process_eqe(struct gdma_queue *eq) 439 { 440 uint32_t head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 441 struct gdma_context *gc = eq->gdma_dev->gdma_context; 442 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 443 union gdma_eqe_info eqe_info; 444 enum gdma_eqe_type type; 445 struct gdma_event event; 446 struct gdma_queue *cq; 447 struct gdma_eqe *eqe; 448 uint32_t cq_id; 449 450 eqe = &eq_eqe_ptr[head]; 451 eqe_info.as_uint32 = eqe->eqe_info; 452 type = eqe_info.type; 453 454 switch (type) { 455 case GDMA_EQE_COMPLETION: 456 cq_id = eqe->details[0] & 0xFFFFFF; 457 if (cq_id >= gc->max_num_cqs) { 458 mana_warn(NULL, 459 "failed: cq_id %u > max_num_cqs %u\n", 460 cq_id, gc->max_num_cqs); 461 break; 462 } 463 464 cq = gc->cq_table[cq_id]; 465 if (!cq || cq->type != GDMA_CQ || cq->id != cq_id) { 466 mana_warn(NULL, 467 "failed: invalid cq_id %u\n", cq_id); 468 break; 469 } 470 471 if (cq->cq.callback) 472 cq->cq.callback(cq->cq.context, cq); 473 474 break; 475 476 case GDMA_EQE_TEST_EVENT: 477 gc->test_event_eq_id = eq->id; 478 479 mana_dbg(NULL, 480 "EQE TEST EVENT received for EQ %u\n", eq->id); 481 482 complete(&gc->eq_test_event); 483 break; 484 485 case GDMA_EQE_HWC_INIT_EQ_ID_DB: 486 case GDMA_EQE_HWC_INIT_DATA: 487 case GDMA_EQE_HWC_INIT_DONE: 488 if (!eq->eq.callback) 489 break; 490 491 event.type = type; 492 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 493 eq->eq.callback(eq->eq.context, eq, &event); 494 break; 495 496 default: 497 break; 498 } 499 } 500 501 static void 502 mana_gd_process_eq_events(void *arg) 503 { 504 uint32_t owner_bits, new_bits, old_bits; 505 union gdma_eqe_info eqe_info; 506 struct gdma_eqe *eq_eqe_ptr; 507 struct gdma_queue *eq = arg; 508 struct gdma_context *gc; 509 uint32_t head, num_eqe; 510 struct gdma_eqe *eqe; 511 unsigned int arm_bit; 512 int i, j; 513 514 gc = eq->gdma_dev->gdma_context; 515 516 num_eqe = eq->queue_size / GDMA_EQE_SIZE; 517 eq_eqe_ptr = eq->queue_mem_ptr; 518 519 bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 520 BUS_DMASYNC_POSTREAD); 521 522 /* Process up to 5 EQEs at a time, and update the HW head. */ 523 for (i = 0; i < 5; i++) { 524 eqe = &eq_eqe_ptr[eq->head % num_eqe]; 525 eqe_info.as_uint32 = eqe->eqe_info; 526 owner_bits = eqe_info.owner_bits; 527 528 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 529 530 /* No more entries */ 531 if (owner_bits == old_bits) 532 break; 533 534 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 535 if (owner_bits != new_bits) { 536 /* Something wrong. Log for debugging purpose */ 537 device_printf(gc->dev, 538 "EQ %d: overflow detected, " 539 "i = %d, eq->head = %u " 540 "got owner_bits = %u, new_bits = %u " 541 "eqe addr %p, eqe->eqe_info 0x%x, " 542 "eqe type = %x, reserved1 = %x, client_id = %x, " 543 "reserved2 = %x, owner_bits = %x\n", 544 eq->id, i, eq->head, 545 owner_bits, new_bits, 546 eqe, eqe->eqe_info, 547 eqe_info.type, eqe_info.reserved1, 548 eqe_info.client_id, eqe_info.reserved2, 549 eqe_info.owner_bits); 550 551 uint32_t *eqe_dump = (uint32_t *) eq_eqe_ptr; 552 for (j = 0; j < 20; j++) { 553 device_printf(gc->dev, "%p: %x\t%x\t%x\t%x\n", 554 &eqe_dump[j * 4], eqe_dump[j * 4], eqe_dump[j * 4 + 1], 555 eqe_dump[j * 4 + 2], eqe_dump[j * 4 + 3]); 556 } 557 break; 558 } 559 560 mana_gd_process_eqe(eq); 561 562 eq->head++; 563 } 564 565 bus_dmamap_sync(eq->mem_info.dma_tag, eq->mem_info.dma_map, 566 BUS_DMASYNC_PREREAD); 567 568 /* Always rearm the EQ for HWC. */ 569 if (mana_gd_is_hwc(eq->gdma_dev)) { 570 arm_bit = SET_ARM_BIT; 571 } else if (eq->eq.work_done < eq->eq.budget && 572 eq->eq.do_not_ring_db == false) { 573 arm_bit = SET_ARM_BIT; 574 } else { 575 arm_bit = 0; 576 } 577 578 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 579 580 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 581 head, arm_bit); 582 } 583 584 #define MANA_POLL_BUDGET 8 585 #define MANA_RX_BUDGET 256 586 587 static void 588 mana_poll(void *arg, int pending) 589 { 590 struct gdma_queue *eq = arg; 591 int i; 592 593 eq->eq.work_done = 0; 594 eq->eq.budget = MANA_RX_BUDGET; 595 596 for (i = 0; i < MANA_POLL_BUDGET; i++) { 597 /* 598 * If this is the last loop, set the budget big enough 599 * so it will arm the EQ any way. 600 */ 601 if (i == (MANA_POLL_BUDGET - 1)) 602 eq->eq.budget = CQE_POLLING_BUFFER + 1; 603 604 mana_gd_process_eq_events(eq); 605 606 if (eq->eq.work_done < eq->eq.budget) 607 break; 608 609 eq->eq.work_done = 0; 610 } 611 } 612 613 static void 614 mana_gd_schedule_task(void *arg) 615 { 616 struct gdma_queue *eq = arg; 617 618 taskqueue_enqueue(eq->eq.cleanup_tq, &eq->eq.cleanup_task); 619 } 620 621 static int 622 mana_gd_register_irq(struct gdma_queue *queue, 623 const struct gdma_queue_spec *spec) 624 { 625 static int mana_last_bind_cpu = -1; 626 struct gdma_dev *gd = queue->gdma_dev; 627 bool is_mana = mana_gd_is_mana(gd); 628 struct gdma_irq_context *gic; 629 struct gdma_context *gc; 630 struct gdma_resource *r; 631 unsigned int msi_index; 632 int err; 633 634 gc = gd->gdma_context; 635 r = &gc->msix_resource; 636 637 mtx_lock_spin(&r->lock_spin); 638 639 msi_index = find_first_zero_bit(r->map, r->size); 640 if (msi_index >= r->size) { 641 err = ENOSPC; 642 } else { 643 bitmap_set(r->map, msi_index, 1); 644 queue->eq.msix_index = msi_index; 645 err = 0; 646 } 647 648 mtx_unlock_spin(&r->lock_spin); 649 650 if (err) 651 return err; 652 653 if (unlikely(msi_index >= gc->num_msix_usable)) { 654 device_printf(gc->dev, 655 "chose an invalid msix index %d, usable %d\n", 656 msi_index, gc->num_msix_usable); 657 return ENOSPC; 658 } 659 660 gic = &gc->irq_contexts[msi_index]; 661 662 if (is_mana) { 663 struct mana_port_context *apc = if_getsoftc(spec->eq.ndev); 664 queue->eq.do_not_ring_db = false; 665 666 NET_TASK_INIT(&queue->eq.cleanup_task, 0, mana_poll, queue); 667 queue->eq.cleanup_tq = 668 taskqueue_create_fast("mana eq cleanup", 669 M_WAITOK, taskqueue_thread_enqueue, 670 &queue->eq.cleanup_tq); 671 672 if (mana_last_bind_cpu < 0) 673 mana_last_bind_cpu = CPU_FIRST(); 674 queue->eq.cpu = mana_last_bind_cpu; 675 mana_last_bind_cpu = CPU_NEXT(mana_last_bind_cpu); 676 677 /* XXX Name is not optimal. However we have to start 678 * the task here. Otherwise, test eq will have no 679 * handler. 680 */ 681 if (apc->bind_cleanup_thread_cpu) { 682 cpuset_t cpu_mask; 683 CPU_SETOF(queue->eq.cpu, &cpu_mask); 684 taskqueue_start_threads_cpuset(&queue->eq.cleanup_tq, 685 1, PI_NET, &cpu_mask, 686 "mana eq poll msix %u on cpu %d", 687 msi_index, queue->eq.cpu); 688 } else { 689 690 taskqueue_start_threads(&queue->eq.cleanup_tq, 1, 691 PI_NET, "mana eq poll on msix %u", msi_index); 692 } 693 } 694 695 if (unlikely(gic->handler || gic->arg)) { 696 device_printf(gc->dev, 697 "interrupt handler or arg already assigned, " 698 "msix index: %d\n", msi_index); 699 } 700 701 gic->arg = queue; 702 703 if (is_mana) 704 gic->handler = mana_gd_schedule_task; 705 else 706 gic->handler = mana_gd_process_eq_events; 707 708 mana_dbg(NULL, "registered msix index %d vector %d irq %ju\n", 709 msi_index, gic->msix_e.vector, rman_get_start(gic->res)); 710 711 return 0; 712 } 713 714 static void 715 mana_gd_deregiser_irq(struct gdma_queue *queue) 716 { 717 struct gdma_dev *gd = queue->gdma_dev; 718 struct gdma_irq_context *gic; 719 struct gdma_context *gc; 720 struct gdma_resource *r; 721 unsigned int msix_index; 722 723 gc = gd->gdma_context; 724 r = &gc->msix_resource; 725 726 /* At most num_online_cpus() + 1 interrupts are used. */ 727 msix_index = queue->eq.msix_index; 728 if (unlikely(msix_index >= gc->num_msix_usable)) 729 return; 730 731 gic = &gc->irq_contexts[msix_index]; 732 gic->handler = NULL; 733 gic->arg = NULL; 734 735 mtx_lock_spin(&r->lock_spin); 736 bitmap_clear(r->map, msix_index, 1); 737 mtx_unlock_spin(&r->lock_spin); 738 739 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 740 741 mana_dbg(NULL, "deregistered msix index %d vector %d irq %ju\n", 742 msix_index, gic->msix_e.vector, rman_get_start(gic->res)); 743 } 744 745 int 746 mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 747 { 748 struct gdma_generate_test_event_req req = {}; 749 struct gdma_general_resp resp = {}; 750 device_t dev = gc->dev; 751 int err; 752 753 sx_xlock(&gc->eq_test_event_sx); 754 755 init_completion(&gc->eq_test_event); 756 gc->test_event_eq_id = INVALID_QUEUE_ID; 757 758 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 759 sizeof(req), sizeof(resp)); 760 761 req.hdr.dev_id = eq->gdma_dev->dev_id; 762 req.queue_index = eq->id; 763 764 err = mana_gd_send_request(gc, sizeof(req), &req, 765 sizeof(resp), &resp); 766 if (err) { 767 device_printf(dev, "test_eq failed: %d\n", err); 768 goto out; 769 } 770 771 err = EPROTO; 772 773 if (resp.hdr.status) { 774 device_printf(dev, "test_eq failed: 0x%x\n", 775 resp.hdr.status); 776 goto out; 777 } 778 779 if (wait_for_completion_timeout(&gc->eq_test_event, 30 * hz)) { 780 device_printf(dev, "test_eq timed out on queue %d\n", 781 eq->id); 782 goto out; 783 } 784 785 if (eq->id != gc->test_event_eq_id) { 786 device_printf(dev, 787 "test_eq got an event on wrong queue %d (%d)\n", 788 gc->test_event_eq_id, eq->id); 789 goto out; 790 } 791 792 err = 0; 793 out: 794 sx_xunlock(&gc->eq_test_event_sx); 795 return err; 796 } 797 798 static void 799 mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 800 struct gdma_queue *queue) 801 { 802 int err; 803 804 if (flush_evenets) { 805 err = mana_gd_test_eq(gc, queue); 806 if (err) 807 device_printf(gc->dev, 808 "Failed to flush EQ: %d\n", err); 809 } 810 811 mana_gd_deregiser_irq(queue); 812 813 if (mana_gd_is_mana(queue->gdma_dev)) { 814 while (taskqueue_cancel(queue->eq.cleanup_tq, 815 &queue->eq.cleanup_task, NULL)) 816 taskqueue_drain(queue->eq.cleanup_tq, 817 &queue->eq.cleanup_task); 818 819 taskqueue_free(queue->eq.cleanup_tq); 820 } 821 822 if (queue->eq.disable_needed) 823 mana_gd_disable_queue(queue); 824 } 825 826 static int mana_gd_create_eq(struct gdma_dev *gd, 827 const struct gdma_queue_spec *spec, 828 bool create_hwq, struct gdma_queue *queue) 829 { 830 struct gdma_context *gc = gd->gdma_context; 831 device_t dev = gc->dev; 832 uint32_t log2_num_entries; 833 int err; 834 835 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 836 837 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 838 839 if (spec->eq.log2_throttle_limit > log2_num_entries) { 840 device_printf(dev, 841 "EQ throttling limit (%lu) > maximum EQE (%u)\n", 842 spec->eq.log2_throttle_limit, log2_num_entries); 843 return EINVAL; 844 } 845 846 err = mana_gd_register_irq(queue, spec); 847 if (err) { 848 device_printf(dev, "Failed to register irq: %d\n", err); 849 return err; 850 } 851 852 queue->eq.callback = spec->eq.callback; 853 queue->eq.context = spec->eq.context; 854 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 855 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 856 857 if (create_hwq) { 858 err = mana_gd_create_hw_eq(gc, queue); 859 if (err) 860 goto out; 861 862 err = mana_gd_test_eq(gc, queue); 863 if (err) 864 goto out; 865 } 866 867 return 0; 868 out: 869 device_printf(dev, "Failed to create EQ: %d\n", err); 870 mana_gd_destroy_eq(gc, false, queue); 871 return err; 872 } 873 874 static void 875 mana_gd_create_cq(const struct gdma_queue_spec *spec, 876 struct gdma_queue *queue) 877 { 878 uint32_t log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 879 880 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 881 queue->cq.parent = spec->cq.parent_eq; 882 queue->cq.context = spec->cq.context; 883 queue->cq.callback = spec->cq.callback; 884 } 885 886 static void 887 mana_gd_destroy_cq(struct gdma_context *gc, 888 struct gdma_queue *queue) 889 { 890 uint32_t id = queue->id; 891 892 if (id >= gc->max_num_cqs) 893 return; 894 895 if (!gc->cq_table[id]) 896 return; 897 898 gc->cq_table[id] = NULL; 899 } 900 901 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 902 const struct gdma_queue_spec *spec, 903 struct gdma_queue **queue_ptr) 904 { 905 struct gdma_context *gc = gd->gdma_context; 906 struct gdma_mem_info *gmi; 907 struct gdma_queue *queue; 908 int err; 909 910 queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 911 if (!queue) 912 return ENOMEM; 913 914 gmi = &queue->mem_info; 915 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 916 if (err) 917 goto free_q; 918 919 queue->head = 0; 920 queue->tail = 0; 921 queue->queue_mem_ptr = gmi->virt_addr; 922 queue->queue_size = spec->queue_size; 923 queue->monitor_avl_buf = spec->monitor_avl_buf; 924 queue->type = spec->type; 925 queue->gdma_dev = gd; 926 927 if (spec->type == GDMA_EQ) 928 err = mana_gd_create_eq(gd, spec, false, queue); 929 else if (spec->type == GDMA_CQ) 930 mana_gd_create_cq(spec, queue); 931 932 if (err) 933 goto out; 934 935 *queue_ptr = queue; 936 return 0; 937 out: 938 mana_gd_free_memory(gmi); 939 free_q: 940 free(queue, M_DEVBUF); 941 return err; 942 } 943 944 static void 945 mana_gd_destroy_dma_region(struct gdma_context *gc, uint64_t gdma_region) 946 { 947 struct gdma_destroy_dma_region_req req = {}; 948 struct gdma_general_resp resp = {}; 949 int err; 950 951 if (gdma_region == GDMA_INVALID_DMA_REGION) 952 return; 953 954 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 955 sizeof(resp)); 956 req.gdma_region = gdma_region; 957 958 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), 959 &resp); 960 if (err || resp.hdr.status) 961 device_printf(gc->dev, 962 "Failed to destroy DMA region: %d, 0x%x\n", 963 err, resp.hdr.status); 964 } 965 966 static int 967 mana_gd_create_dma_region(struct gdma_dev *gd, 968 struct gdma_mem_info *gmi) 969 { 970 unsigned int num_page = gmi->length / PAGE_SIZE; 971 struct gdma_create_dma_region_req *req = NULL; 972 struct gdma_create_dma_region_resp resp = {}; 973 struct gdma_context *gc = gd->gdma_context; 974 struct hw_channel_context *hwc; 975 uint32_t length = gmi->length; 976 uint32_t req_msg_size; 977 int err; 978 int i; 979 980 if (length < PAGE_SIZE || !is_power_of_2(length)) { 981 mana_err(NULL, "gmi size incorrect: %u\n", length); 982 return EINVAL; 983 } 984 985 if (offset_in_page((uint64_t)gmi->virt_addr) != 0) { 986 mana_err(NULL, "gmi not page aligned: %p\n", 987 gmi->virt_addr); 988 return EINVAL; 989 } 990 991 hwc = gc->hwc.driver_data; 992 req_msg_size = sizeof(*req) + num_page * sizeof(uint64_t); 993 if (req_msg_size > hwc->max_req_msg_size) { 994 mana_err(NULL, "req msg size too large: %u, %u\n", 995 req_msg_size, hwc->max_req_msg_size); 996 return EINVAL; 997 } 998 999 req = malloc(req_msg_size, M_DEVBUF, M_WAITOK | M_ZERO); 1000 if (!req) 1001 return ENOMEM; 1002 1003 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 1004 req_msg_size, sizeof(resp)); 1005 req->length = length; 1006 req->offset_in_page = 0; 1007 req->gdma_page_type = GDMA_PAGE_TYPE_4K; 1008 req->page_count = num_page; 1009 req->page_addr_list_len = num_page; 1010 1011 for (i = 0; i < num_page; i++) 1012 req->page_addr_list[i] = gmi->dma_handle + i * PAGE_SIZE; 1013 1014 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 1015 if (err) 1016 goto out; 1017 1018 if (resp.hdr.status || resp.gdma_region == GDMA_INVALID_DMA_REGION) { 1019 device_printf(gc->dev, "Failed to create DMA region: 0x%x\n", 1020 resp.hdr.status); 1021 err = EPROTO; 1022 goto out; 1023 } 1024 1025 gmi->gdma_region = resp.gdma_region; 1026 out: 1027 free(req, M_DEVBUF); 1028 return err; 1029 } 1030 1031 int 1032 mana_gd_create_mana_eq(struct gdma_dev *gd, 1033 const struct gdma_queue_spec *spec, 1034 struct gdma_queue **queue_ptr) 1035 { 1036 struct gdma_context *gc = gd->gdma_context; 1037 struct gdma_mem_info *gmi; 1038 struct gdma_queue *queue; 1039 int err; 1040 1041 if (spec->type != GDMA_EQ) 1042 return EINVAL; 1043 1044 queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 1045 if (!queue) 1046 return ENOMEM; 1047 1048 gmi = &queue->mem_info; 1049 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 1050 if (err) 1051 goto free_q; 1052 1053 err = mana_gd_create_dma_region(gd, gmi); 1054 if (err) 1055 goto out; 1056 1057 queue->head = 0; 1058 queue->tail = 0; 1059 queue->queue_mem_ptr = gmi->virt_addr; 1060 queue->queue_size = spec->queue_size; 1061 queue->monitor_avl_buf = spec->monitor_avl_buf; 1062 queue->type = spec->type; 1063 queue->gdma_dev = gd; 1064 1065 err = mana_gd_create_eq(gd, spec, true, queue); 1066 if (err) 1067 goto out; 1068 1069 *queue_ptr = queue; 1070 return 0; 1071 1072 out: 1073 mana_gd_free_memory(gmi); 1074 free_q: 1075 free(queue, M_DEVBUF); 1076 return err; 1077 } 1078 1079 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 1080 const struct gdma_queue_spec *spec, 1081 struct gdma_queue **queue_ptr) 1082 { 1083 struct gdma_context *gc = gd->gdma_context; 1084 struct gdma_mem_info *gmi; 1085 struct gdma_queue *queue; 1086 int err; 1087 1088 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 1089 spec->type != GDMA_RQ) 1090 return EINVAL; 1091 1092 queue = malloc(sizeof(*queue), M_DEVBUF, M_WAITOK | M_ZERO); 1093 if (!queue) 1094 return ENOMEM; 1095 1096 gmi = &queue->mem_info; 1097 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 1098 if (err) 1099 goto free_q; 1100 1101 err = mana_gd_create_dma_region(gd, gmi); 1102 if (err) 1103 goto out; 1104 1105 queue->head = 0; 1106 queue->tail = 0; 1107 queue->queue_mem_ptr = gmi->virt_addr; 1108 queue->queue_size = spec->queue_size; 1109 queue->monitor_avl_buf = spec->monitor_avl_buf; 1110 queue->type = spec->type; 1111 queue->gdma_dev = gd; 1112 1113 if (spec->type == GDMA_CQ) 1114 mana_gd_create_cq(spec, queue); 1115 1116 *queue_ptr = queue; 1117 return 0; 1118 1119 out: 1120 mana_gd_free_memory(gmi); 1121 free_q: 1122 free(queue, M_DEVBUF); 1123 return err; 1124 } 1125 1126 void 1127 mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 1128 { 1129 struct gdma_mem_info *gmi = &queue->mem_info; 1130 1131 switch (queue->type) { 1132 case GDMA_EQ: 1133 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 1134 break; 1135 1136 case GDMA_CQ: 1137 mana_gd_destroy_cq(gc, queue); 1138 break; 1139 1140 case GDMA_RQ: 1141 break; 1142 1143 case GDMA_SQ: 1144 break; 1145 1146 default: 1147 device_printf(gc->dev, 1148 "Can't destroy unknown queue: type = %d\n", 1149 queue->type); 1150 return; 1151 } 1152 1153 mana_gd_destroy_dma_region(gc, gmi->gdma_region); 1154 mana_gd_free_memory(gmi); 1155 free(queue, M_DEVBUF); 1156 } 1157 1158 int 1159 mana_gd_verify_vf_version(device_t dev) 1160 { 1161 struct gdma_context *gc = device_get_softc(dev); 1162 struct gdma_verify_ver_resp resp = {}; 1163 struct gdma_verify_ver_req req = {}; 1164 int err; 1165 1166 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 1167 sizeof(req), sizeof(resp)); 1168 1169 req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 1170 req.protocol_ver_max = GDMA_PROTOCOL_LAST; 1171 1172 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1173 if (err || resp.hdr.status) { 1174 device_printf(gc->dev, 1175 "VfVerifyVersionOutput: %d, status=0x%x\n", 1176 err, resp.hdr.status); 1177 return err ? err : EPROTO; 1178 } 1179 1180 return 0; 1181 } 1182 1183 int 1184 mana_gd_register_device(struct gdma_dev *gd) 1185 { 1186 struct gdma_context *gc = gd->gdma_context; 1187 struct gdma_register_device_resp resp = {}; 1188 struct gdma_general_req req = {}; 1189 int err; 1190 1191 gd->pdid = INVALID_PDID; 1192 gd->doorbell = INVALID_DOORBELL; 1193 gd->gpa_mkey = INVALID_MEM_KEY; 1194 1195 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 1196 sizeof(resp)); 1197 1198 req.hdr.dev_id = gd->dev_id; 1199 1200 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1201 if (err || resp.hdr.status) { 1202 device_printf(gc->dev, 1203 "gdma_register_device_resp failed: %d, 0x%x\n", 1204 err, resp.hdr.status); 1205 return err ? err : -EPROTO; 1206 } 1207 1208 gd->pdid = resp.pdid; 1209 gd->gpa_mkey = resp.gpa_mkey; 1210 gd->doorbell = resp.db_id; 1211 1212 mana_dbg(NULL, "mana device pdid %u, gpa_mkey %u, doorbell %u \n", 1213 gd->pdid, gd->gpa_mkey, gd->doorbell); 1214 1215 return 0; 1216 } 1217 1218 int 1219 mana_gd_deregister_device(struct gdma_dev *gd) 1220 { 1221 struct gdma_context *gc = gd->gdma_context; 1222 struct gdma_general_resp resp = {}; 1223 struct gdma_general_req req = {}; 1224 int err; 1225 1226 if (gd->pdid == INVALID_PDID) 1227 return EINVAL; 1228 1229 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 1230 sizeof(resp)); 1231 1232 req.hdr.dev_id = gd->dev_id; 1233 1234 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1235 if (err || resp.hdr.status) { 1236 device_printf(gc->dev, 1237 "Failed to deregister device: %d, 0x%x\n", 1238 err, resp.hdr.status); 1239 if (!err) 1240 err = EPROTO; 1241 } 1242 1243 gd->pdid = INVALID_PDID; 1244 gd->doorbell = INVALID_DOORBELL; 1245 gd->gpa_mkey = INVALID_MEM_KEY; 1246 1247 return err; 1248 } 1249 1250 uint32_t 1251 mana_gd_wq_avail_space(struct gdma_queue *wq) 1252 { 1253 uint32_t used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 1254 uint32_t wq_size = wq->queue_size; 1255 1256 if (used_space > wq_size) { 1257 mana_warn(NULL, "failed: used space %u > queue size %u\n", 1258 used_space, wq_size); 1259 } 1260 1261 return wq_size - used_space; 1262 } 1263 1264 uint8_t * 1265 mana_gd_get_wqe_ptr(const struct gdma_queue *wq, uint32_t wqe_offset) 1266 { 1267 uint32_t offset = 1268 (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 1269 1270 if ((offset + GDMA_WQE_BU_SIZE) > wq->queue_size) { 1271 mana_warn(NULL, "failed: write end out of queue bound %u, " 1272 "queue size %u\n", 1273 offset + GDMA_WQE_BU_SIZE, wq->queue_size); 1274 } 1275 1276 return (uint8_t *)wq->queue_mem_ptr + offset; 1277 } 1278 1279 static uint32_t 1280 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 1281 enum gdma_queue_type q_type, 1282 uint32_t client_oob_size, uint32_t sgl_data_size, 1283 uint8_t *wqe_ptr) 1284 { 1285 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 1286 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 1287 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 1288 uint8_t *ptr; 1289 1290 memset(header, 0, sizeof(struct gdma_wqe)); 1291 header->num_sge = wqe_req->num_sge; 1292 header->inline_oob_size_div4 = client_oob_size / sizeof(uint32_t); 1293 1294 if (oob_in_sgl) { 1295 if (!pad_data || wqe_req->num_sge < 2) { 1296 mana_warn(NULL, "no pad_data or num_sge < 2\n"); 1297 } 1298 1299 header->client_oob_in_sgl = 1; 1300 1301 if (pad_data) 1302 header->last_vbytes = wqe_req->sgl[0].size; 1303 } 1304 1305 if (q_type == GDMA_SQ) 1306 header->client_data_unit = wqe_req->client_data_unit; 1307 1308 /* 1309 * The size of gdma_wqe + client_oob_size must be less than or equal 1310 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1311 * the queue memory buffer boundary. 1312 */ 1313 ptr = wqe_ptr + sizeof(header); 1314 1315 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1316 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1317 1318 if (client_oob_size > wqe_req->inline_oob_size) 1319 memset(ptr + wqe_req->inline_oob_size, 0, 1320 client_oob_size - wqe_req->inline_oob_size); 1321 } 1322 1323 return sizeof(header) + client_oob_size; 1324 } 1325 1326 static void 1327 mana_gd_write_sgl(struct gdma_queue *wq, uint8_t *wqe_ptr, 1328 const struct gdma_wqe_request *wqe_req) 1329 { 1330 uint32_t sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1331 const uint8_t *address = (uint8_t *)wqe_req->sgl; 1332 uint8_t *base_ptr, *end_ptr; 1333 uint32_t size_to_end; 1334 1335 base_ptr = wq->queue_mem_ptr; 1336 end_ptr = base_ptr + wq->queue_size; 1337 size_to_end = (uint32_t)(end_ptr - wqe_ptr); 1338 1339 if (size_to_end < sgl_size) { 1340 memcpy(wqe_ptr, address, size_to_end); 1341 1342 wqe_ptr = base_ptr; 1343 address += size_to_end; 1344 sgl_size -= size_to_end; 1345 } 1346 1347 memcpy(wqe_ptr, address, sgl_size); 1348 } 1349 1350 int 1351 mana_gd_post_work_request(struct gdma_queue *wq, 1352 const struct gdma_wqe_request *wqe_req, 1353 struct gdma_posted_wqe_info *wqe_info) 1354 { 1355 uint32_t client_oob_size = wqe_req->inline_oob_size; 1356 struct gdma_context *gc; 1357 uint32_t sgl_data_size; 1358 uint32_t max_wqe_size; 1359 uint32_t wqe_size; 1360 uint8_t *wqe_ptr; 1361 1362 if (wqe_req->num_sge == 0) 1363 return EINVAL; 1364 1365 if (wq->type == GDMA_RQ) { 1366 if (client_oob_size != 0) 1367 return EINVAL; 1368 1369 client_oob_size = INLINE_OOB_SMALL_SIZE; 1370 1371 max_wqe_size = GDMA_MAX_RQE_SIZE; 1372 } else { 1373 if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1374 client_oob_size != INLINE_OOB_LARGE_SIZE) 1375 return EINVAL; 1376 1377 max_wqe_size = GDMA_MAX_SQE_SIZE; 1378 } 1379 1380 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1381 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1382 sgl_data_size, GDMA_WQE_BU_SIZE); 1383 if (wqe_size > max_wqe_size) 1384 return EINVAL; 1385 1386 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1387 gc = wq->gdma_dev->gdma_context; 1388 device_printf(gc->dev, "unsuccessful flow control!\n"); 1389 return ENOSPC; 1390 } 1391 1392 if (wqe_info) 1393 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1394 1395 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1396 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1397 sgl_data_size, wqe_ptr); 1398 if (wqe_ptr >= (uint8_t *)wq->queue_mem_ptr + wq->queue_size) 1399 wqe_ptr -= wq->queue_size; 1400 1401 mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1402 1403 wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1404 1405 bus_dmamap_sync(wq->mem_info.dma_tag, wq->mem_info.dma_map, 1406 BUS_DMASYNC_PREWRITE); 1407 1408 return 0; 1409 } 1410 1411 int 1412 mana_gd_post_and_ring(struct gdma_queue *queue, 1413 const struct gdma_wqe_request *wqe_req, 1414 struct gdma_posted_wqe_info *wqe_info) 1415 { 1416 struct gdma_context *gc = queue->gdma_dev->gdma_context; 1417 int err; 1418 1419 err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1420 if (err) 1421 return err; 1422 1423 mana_gd_wq_ring_doorbell(gc, queue); 1424 1425 return 0; 1426 } 1427 1428 static int 1429 mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1430 { 1431 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1432 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1433 uint32_t owner_bits, new_bits, old_bits; 1434 struct gdma_cqe *cqe; 1435 1436 cqe = &cq_cqe[cq->head % num_cqe]; 1437 owner_bits = cqe->cqe_info.owner_bits; 1438 1439 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1440 /* Return 0 if no more entries. */ 1441 if (owner_bits == old_bits) 1442 return 0; 1443 1444 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1445 /* Return -1 if overflow detected. */ 1446 if (owner_bits != new_bits) 1447 return -1; 1448 1449 comp->wq_num = cqe->cqe_info.wq_num; 1450 comp->is_sq = cqe->cqe_info.is_sq; 1451 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1452 1453 return 1; 1454 } 1455 1456 int 1457 mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1458 { 1459 int cqe_idx; 1460 int ret; 1461 1462 bus_dmamap_sync(cq->mem_info.dma_tag, cq->mem_info.dma_map, 1463 BUS_DMASYNC_POSTREAD); 1464 1465 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1466 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1467 1468 if (ret < 0) { 1469 cq->head -= cqe_idx; 1470 return ret; 1471 } 1472 1473 if (ret == 0) 1474 break; 1475 1476 cq->head++; 1477 } 1478 1479 return cqe_idx; 1480 } 1481 1482 static void 1483 mana_gd_intr(void *arg) 1484 { 1485 struct gdma_irq_context *gic = arg; 1486 1487 if (gic->handler) { 1488 gic->handler(gic->arg); 1489 } 1490 } 1491 1492 int 1493 mana_gd_alloc_res_map(uint32_t res_avail, 1494 struct gdma_resource *r, const char *lock_name) 1495 { 1496 int n = howmany(res_avail, BITS_PER_LONG); 1497 1498 r->map = 1499 malloc(n * sizeof(unsigned long), M_DEVBUF, M_WAITOK | M_ZERO); 1500 if (!r->map) 1501 return ENOMEM; 1502 1503 r->size = res_avail; 1504 mtx_init(&r->lock_spin, lock_name, NULL, MTX_SPIN); 1505 1506 mana_dbg(NULL, 1507 "total res %u, total number of unsigned longs %u\n", 1508 r->size, n); 1509 return (0); 1510 } 1511 1512 void 1513 mana_gd_free_res_map(struct gdma_resource *r) 1514 { 1515 if (!r || !r->map) 1516 return; 1517 1518 free(r->map, M_DEVBUF); 1519 r->map = NULL; 1520 r->size = 0; 1521 } 1522 1523 static void 1524 mana_gd_init_registers(struct gdma_context *gc) 1525 { 1526 uint64_t bar0_va = rman_get_bushandle(gc->bar0); 1527 1528 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 1529 1530 gc->db_page_base = 1531 (void *) (bar0_va + mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET)); 1532 1533 gc->shm_base = 1534 (void *) (bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET)); 1535 1536 mana_dbg(NULL, "db_page_size 0x%xx, db_page_base %p," 1537 " shm_base %p\n", 1538 gc->db_page_size, gc->db_page_base, gc->shm_base); 1539 } 1540 1541 static struct resource * 1542 mana_gd_alloc_bar(device_t dev, int bar) 1543 { 1544 struct resource *res = NULL; 1545 struct pci_map *pm; 1546 int rid, type; 1547 1548 if (bar < 0 || bar > PCIR_MAX_BAR_0) 1549 goto alloc_bar_out; 1550 1551 pm = pci_find_bar(dev, PCIR_BAR(bar)); 1552 if (!pm) 1553 goto alloc_bar_out; 1554 1555 if (PCI_BAR_IO(pm->pm_value)) 1556 type = SYS_RES_IOPORT; 1557 else 1558 type = SYS_RES_MEMORY; 1559 if (type < 0) 1560 goto alloc_bar_out; 1561 1562 rid = PCIR_BAR(bar); 1563 res = bus_alloc_resource_any(dev, type, &rid, RF_ACTIVE); 1564 #if defined(__amd64__) 1565 if (res) 1566 mana_dbg(NULL, "bar %d: rid 0x%x, type 0x%jx," 1567 " handle 0x%jx\n", 1568 bar, rid, res->r_bustag, res->r_bushandle); 1569 #endif 1570 1571 alloc_bar_out: 1572 return (res); 1573 } 1574 1575 static void 1576 mana_gd_free_pci_res(struct gdma_context *gc) 1577 { 1578 if (!gc || gc->dev) 1579 return; 1580 1581 if (gc->bar0 != NULL) { 1582 bus_release_resource(gc->dev, SYS_RES_MEMORY, 1583 PCIR_BAR(GDMA_BAR0), gc->bar0); 1584 } 1585 1586 if (gc->msix != NULL) { 1587 bus_release_resource(gc->dev, SYS_RES_MEMORY, 1588 gc->msix_rid, gc->msix); 1589 } 1590 } 1591 1592 static int 1593 mana_gd_setup_irqs(device_t dev) 1594 { 1595 unsigned int max_queues_per_port = mp_ncpus; 1596 struct gdma_context *gc = device_get_softc(dev); 1597 struct gdma_irq_context *gic; 1598 unsigned int max_irqs; 1599 int nvec; 1600 int rc, rcc, i; 1601 1602 if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1603 max_queues_per_port = MANA_MAX_NUM_QUEUES; 1604 1605 max_irqs = max_queues_per_port * MAX_PORTS_IN_MANA_DEV; 1606 1607 /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 1608 max_irqs++; 1609 1610 nvec = max_irqs; 1611 rc = pci_alloc_msix(dev, &nvec); 1612 if (unlikely(rc != 0)) { 1613 device_printf(dev, 1614 "Failed to allocate MSIX, vectors %d, error: %d\n", 1615 nvec, rc); 1616 rc = ENOSPC; 1617 goto err_setup_irq_alloc; 1618 } 1619 1620 if (nvec != max_irqs) { 1621 if (nvec == 1) { 1622 device_printf(dev, 1623 "Not enough number of MSI-x allocated: %d\n", 1624 nvec); 1625 rc = ENOSPC; 1626 goto err_setup_irq_release; 1627 } 1628 device_printf(dev, "Allocated only %d MSI-x (%d requested)\n", 1629 nvec, max_irqs); 1630 } 1631 1632 gc->irq_contexts = malloc(nvec * sizeof(struct gdma_irq_context), 1633 M_DEVBUF, M_WAITOK | M_ZERO); 1634 if (!gc->irq_contexts) { 1635 rc = ENOMEM; 1636 goto err_setup_irq_release; 1637 } 1638 1639 for (i = 0; i < nvec; i++) { 1640 gic = &gc->irq_contexts[i]; 1641 gic->msix_e.entry = i; 1642 /* Vector starts from 1. */ 1643 gic->msix_e.vector = i + 1; 1644 gic->handler = NULL; 1645 gic->arg = NULL; 1646 1647 gic->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1648 &gic->msix_e.vector, RF_ACTIVE | RF_SHAREABLE); 1649 if (unlikely(gic->res == NULL)) { 1650 rc = ENOMEM; 1651 device_printf(dev, "could not allocate resource " 1652 "for irq vector %d\n", gic->msix_e.vector); 1653 goto err_setup_irq; 1654 } 1655 1656 rc = bus_setup_intr(dev, gic->res, 1657 INTR_TYPE_NET | INTR_MPSAFE, NULL, mana_gd_intr, 1658 gic, &gic->cookie); 1659 if (unlikely(rc != 0)) { 1660 device_printf(dev, "failed to register interrupt " 1661 "handler for irq %ju vector %d: error %d\n", 1662 rman_get_start(gic->res), gic->msix_e.vector, rc); 1663 goto err_setup_irq; 1664 } 1665 gic->requested = true; 1666 1667 mana_dbg(NULL, "added msix vector %d irq %ju\n", 1668 gic->msix_e.vector, rman_get_start(gic->res)); 1669 } 1670 1671 rc = mana_gd_alloc_res_map(nvec, &gc->msix_resource, 1672 "gdma msix res lock"); 1673 if (rc != 0) { 1674 device_printf(dev, "failed to allocate memory " 1675 "for msix bitmap\n"); 1676 goto err_setup_irq; 1677 } 1678 1679 gc->max_num_msix = nvec; 1680 gc->num_msix_usable = nvec; 1681 1682 mana_dbg(NULL, "setup %d msix interrupts\n", nvec); 1683 1684 return (0); 1685 1686 err_setup_irq: 1687 for (; i >= 0; i--) { 1688 gic = &gc->irq_contexts[i]; 1689 rcc = 0; 1690 1691 /* 1692 * If gic->requested is true, we need to free both intr and 1693 * resources. 1694 */ 1695 if (gic->requested) 1696 rcc = bus_teardown_intr(dev, gic->res, gic->cookie); 1697 if (unlikely(rcc != 0)) 1698 device_printf(dev, "could not release " 1699 "irq vector %d, error: %d\n", 1700 gic->msix_e.vector, rcc); 1701 1702 rcc = 0; 1703 if (gic->res != NULL) { 1704 rcc = bus_release_resource(dev, SYS_RES_IRQ, 1705 gic->msix_e.vector, gic->res); 1706 } 1707 if (unlikely(rcc != 0)) 1708 device_printf(dev, "dev has no parent while " 1709 "releasing resource for irq vector %d\n", 1710 gic->msix_e.vector); 1711 gic->requested = false; 1712 gic->res = NULL; 1713 } 1714 1715 free(gc->irq_contexts, M_DEVBUF); 1716 gc->irq_contexts = NULL; 1717 err_setup_irq_release: 1718 pci_release_msi(dev); 1719 err_setup_irq_alloc: 1720 return (rc); 1721 } 1722 1723 static void 1724 mana_gd_remove_irqs(device_t dev) 1725 { 1726 struct gdma_context *gc = device_get_softc(dev); 1727 struct gdma_irq_context *gic; 1728 int rc, i; 1729 1730 mana_gd_free_res_map(&gc->msix_resource); 1731 1732 for (i = 0; i < gc->max_num_msix; i++) { 1733 gic = &gc->irq_contexts[i]; 1734 if (gic->requested) { 1735 rc = bus_teardown_intr(dev, gic->res, gic->cookie); 1736 if (unlikely(rc != 0)) { 1737 device_printf(dev, "failed to tear down " 1738 "irq vector %d, error: %d\n", 1739 gic->msix_e.vector, rc); 1740 } 1741 gic->requested = false; 1742 } 1743 1744 if (gic->res != NULL) { 1745 rc = bus_release_resource(dev, SYS_RES_IRQ, 1746 gic->msix_e.vector, gic->res); 1747 if (unlikely(rc != 0)) { 1748 device_printf(dev, "dev has no parent while " 1749 "releasing resource for irq vector %d\n", 1750 gic->msix_e.vector); 1751 } 1752 gic->res = NULL; 1753 } 1754 } 1755 1756 gc->max_num_msix = 0; 1757 gc->num_msix_usable = 0; 1758 free(gc->irq_contexts, M_DEVBUF); 1759 gc->irq_contexts = NULL; 1760 1761 pci_release_msi(dev); 1762 } 1763 1764 static int 1765 mana_gd_probe(device_t dev) 1766 { 1767 mana_vendor_id_t *ent; 1768 char adapter_name[60]; 1769 uint16_t pci_vendor_id = 0; 1770 uint16_t pci_device_id = 0; 1771 1772 pci_vendor_id = pci_get_vendor(dev); 1773 pci_device_id = pci_get_device(dev); 1774 1775 ent = mana_id_table; 1776 while (ent->vendor_id != 0) { 1777 if ((pci_vendor_id == ent->vendor_id) && 1778 (pci_device_id == ent->device_id)) { 1779 mana_dbg(NULL, "vendor=%x device=%x\n", 1780 pci_vendor_id, pci_device_id); 1781 1782 sprintf(adapter_name, DEVICE_DESC); 1783 device_set_desc_copy(dev, adapter_name); 1784 return (BUS_PROBE_DEFAULT); 1785 } 1786 1787 ent++; 1788 } 1789 1790 return (ENXIO); 1791 } 1792 1793 /** 1794 * mana_attach - Device Initialization Routine 1795 * @dev: device information struct 1796 * 1797 * Returns 0 on success, otherwise on failure. 1798 * 1799 * mana_attach initializes a GDMA adapter identified by a device structure. 1800 **/ 1801 static int 1802 mana_gd_attach(device_t dev) 1803 { 1804 struct gdma_context *gc; 1805 int msix_rid; 1806 int rc; 1807 1808 gc = device_get_softc(dev); 1809 gc->dev = dev; 1810 1811 pci_enable_io(dev, SYS_RES_IOPORT); 1812 pci_enable_io(dev, SYS_RES_MEMORY); 1813 1814 pci_enable_busmaster(dev); 1815 1816 gc->bar0 = mana_gd_alloc_bar(dev, GDMA_BAR0); 1817 if (unlikely(gc->bar0 == NULL)) { 1818 device_printf(dev, 1819 "unable to allocate bus resource for bar0!\n"); 1820 rc = ENOMEM; 1821 goto err_disable_dev; 1822 } 1823 1824 /* Store bar0 tage and handle for quick access */ 1825 gc->gd_bus.bar0_t = rman_get_bustag(gc->bar0); 1826 gc->gd_bus.bar0_h = rman_get_bushandle(gc->bar0); 1827 1828 /* Map MSI-x vector table */ 1829 msix_rid = pci_msix_table_bar(dev); 1830 1831 mana_dbg(NULL, "msix_rid 0x%x\n", msix_rid); 1832 1833 gc->msix = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1834 &msix_rid, RF_ACTIVE); 1835 if (unlikely(gc->msix == NULL)) { 1836 device_printf(dev, 1837 "unable to allocate bus resource for msix!\n"); 1838 rc = ENOMEM; 1839 goto err_free_pci_res; 1840 } 1841 gc->msix_rid = msix_rid; 1842 1843 if (unlikely(gc->gd_bus.bar0_h == 0)) { 1844 device_printf(dev, "failed to map bar0!\n"); 1845 rc = ENXIO; 1846 goto err_free_pci_res; 1847 } 1848 1849 mana_gd_init_registers(gc); 1850 1851 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1852 1853 rc = mana_gd_setup_irqs(dev); 1854 if (rc) { 1855 goto err_free_pci_res; 1856 } 1857 1858 sx_init(&gc->eq_test_event_sx, "gdma test event sx"); 1859 1860 rc = mana_hwc_create_channel(gc); 1861 if (rc) { 1862 mana_dbg(NULL, "Failed to create hwc channel\n"); 1863 if (rc == EIO) 1864 goto err_clean_up_gdma; 1865 else 1866 goto err_remove_irq; 1867 } 1868 1869 rc = mana_gd_verify_vf_version(dev); 1870 if (rc) { 1871 mana_dbg(NULL, "Failed to verify vf\n"); 1872 goto err_clean_up_gdma; 1873 } 1874 1875 rc = mana_gd_query_max_resources(dev); 1876 if (rc) { 1877 mana_dbg(NULL, "Failed to query max resources\n"); 1878 goto err_clean_up_gdma; 1879 } 1880 1881 rc = mana_gd_detect_devices(dev); 1882 if (rc) { 1883 mana_dbg(NULL, "Failed to detect mana device\n"); 1884 goto err_clean_up_gdma; 1885 } 1886 1887 rc = mana_probe(&gc->mana); 1888 if (rc) { 1889 mana_dbg(NULL, "Failed to probe mana device\n"); 1890 goto err_clean_up_gdma; 1891 } 1892 1893 return (0); 1894 1895 err_clean_up_gdma: 1896 mana_hwc_destroy_channel(gc); 1897 if (gc->cq_table) 1898 free(gc->cq_table, M_DEVBUF); 1899 gc->cq_table = NULL; 1900 err_remove_irq: 1901 mana_gd_remove_irqs(dev); 1902 err_free_pci_res: 1903 mana_gd_free_pci_res(gc); 1904 err_disable_dev: 1905 pci_disable_busmaster(dev); 1906 1907 return(rc); 1908 } 1909 1910 /** 1911 * mana_detach - Device Removal Routine 1912 * @pdev: device information struct 1913 * 1914 * mana_detach is called by the device subsystem to alert the driver 1915 * that it should release a PCI device. 1916 **/ 1917 static int 1918 mana_gd_detach(device_t dev) 1919 { 1920 struct gdma_context *gc = device_get_softc(dev); 1921 1922 mana_remove(&gc->mana); 1923 1924 mana_hwc_destroy_channel(gc); 1925 free(gc->cq_table, M_DEVBUF); 1926 gc->cq_table = NULL; 1927 1928 mana_gd_remove_irqs(dev); 1929 1930 mana_gd_free_pci_res(gc); 1931 1932 pci_disable_busmaster(dev); 1933 1934 return (bus_generic_detach(dev)); 1935 } 1936 1937 1938 /********************************************************************* 1939 * FreeBSD Device Interface Entry Points 1940 *********************************************************************/ 1941 1942 static device_method_t mana_methods[] = { 1943 /* Device interface */ 1944 DEVMETHOD(device_probe, mana_gd_probe), 1945 DEVMETHOD(device_attach, mana_gd_attach), 1946 DEVMETHOD(device_detach, mana_gd_detach), 1947 DEVMETHOD_END 1948 }; 1949 1950 static driver_t mana_driver = { 1951 "mana", mana_methods, sizeof(struct gdma_context), 1952 }; 1953 1954 devclass_t mana_devclass; 1955 DRIVER_MODULE(mana, pci, mana_driver, mana_devclass, 0, 0); 1956 MODULE_PNP_INFO("U16:vendor;U16:device", pci, mana, mana_id_table, 1957 nitems(mana_id_table) - 1); 1958 MODULE_DEPEND(mana, pci, 1, 1, 1); 1959 MODULE_DEPEND(mana, ether, 1, 1, 1); 1960 1961 /*********************************************************************/ 1962